JPH05250302A - Multi-microprocessor system and serial data transfer circuit - Google Patents

Abstract

PURPOSE:To constitute a high-speed serial data transfer line by connecting plural microprocessor systems by a looped data transmission line when the microprocessor systems are used and transmit and receive data to one another. CONSTITUTION:Microprocessor systems (A)101-(n)10n as (n) microprocessor systems are mutually connected in a loop shape by a data transmission line CH and a receiving node select signal line L. IN regard to the microprocessor, only the desired receiving node receives the data by sending a receiving node select signal S specifying a receiving node as a previously set state through the receiving node select signal line L in the previously set state; and other nodes are bypassed to eliminate the need for data reception, thereby speeding up the data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-microprocessor system and a serial data transfer circuit, and more particularly to a multi-microprocessor system for executing serial data transfer between a plurality of microprocessor systems connected by a loop-shaped data transmission path. And a serial data transfer circuit.

[0002]

2. Description of the Related Art Conventionally, in this kind of multi-microprocessor system, various methods have been realized as a data transfer technique between individual microprocessor systems.

These data transfer techniques are roughly classified into two types: parallel data transfer technique and serial data transfer technique.

In parallel data transfer, it is general that the microprocessor systems are connected by a control signal bus, an address bus and a data bus.

In this method, although the number of signals to be connected is large,
Since multiple bits of data can be transferred at the same time, high-speed data transfer is possible.

However, since the above-mentioned bus line is shared by a plurality of microprocessors, a bus arbiter for arbitrating the shared bus is required.

Famous examples of this parallel data transfer system are IEEE-796 (multi-bus) and IEEE-P1.
014 (VME bus), IEEE-488 (GPIB)
Etc.

On the other hand, in serial data transfer, data inside the microprocessor is once converted into serial data and transferred.

This method has the advantage that the number of interface signals connected is smaller and the connection is easier than the parallel data transfer method, but the amount of transfer data per unit time is lower than that of the parallel data transfer method. To do.

Famous serial data transfer methods include a simple and widely used start-stop synchronization method, SDLC and HDLC which are famous as packet communication.

FIG. 6 shows an example of the format of packet data in the conventional packet communication technology.

In FIG. 6, the opening (openi)
ng) flag 301 and closing (close)
g) Flag 306 specifies the start and end of the frame,
An 8-bit flag sequence having a pattern of 01111110 shown in the figure is used.

The secondary address 302 indicates the address of a node as a microprocessor that should receive this packet data in an 8-bit structure. Generally, one node has one secondary address, and one packet data is received by one node. However, since this one-to-one communication is inconvenient, there is an address designation called a global address (generally FFH), and when this global address is designated as the secondary address, all nodes can receive this packet data. Becomes

The control field 303 shows what kind of frame this frame is in an 8-bit structure.

The data field 304 is transmission data, and is generally configured as an arbitrary bit length designated by 8 × n bits.

The frame check sequence 305 designates a frame error control sequence with 16 bits.

FIG. 5 shows an example of a conventional multi-microprocessor system composed of a plurality of microprocessors connected by a loop-shaped data transmission line and a microprocessor system for arbitrating the loop-shaped data transmission line. Indicates.

In FIG. 5, nodes A201 to H
The node of 208 that wants to transmit data outputs a transmission request signal to the loop arbitration processor 200.

The loop arbitration processor 200 checks the transmission / reception ready signal e from each node when the looped data transmission path is idle, and if all nodes involved in data transmission / reception can transmit / receive data. , The data of the node which outputs the node setting instruction signal b to the arbitrary one or a plurality of nodes which should receive the data output by the node which wants to make the transmission request and instructs the data reception preparation, and which does not receive the data. The transmission line is set to the bypass state by the node bypass signal a.

Thereafter, the loop arbitration processor 200
The node making the data transmission request is informed that the node is the data transmission node by the node setting instruction signal b and the node signal c, and the data transmission is permitted.

According to such a system, a node that does not need data does not need to receive the data, and arbitrary packet data can be received by any one or a plurality of nodes. There is a high degree of freedom in the transfer of data between each other, and changes are easy.

[0022]

The multi-bus and VME bus, which are well known as parallel data transfer systems, have been developed as an extension of the system bus of a large-scale multi-microprocessor system, and therefore have a large number of interface signals. Large circuits are needed. Moreover, since the interface signal line is shared by a plurality of microprocessor systems, a control circuit for arbitrating the interface signal line is also required, and the circuit scale becomes larger.

For this reason, the parallel data transfer method has a drawback that it is not suitable for a control multi-microprocessor system which requires interface conditions and simplicity of constituent circuits.

On the other hand, in the method using start-stop synchronization, which is famous as a serial data transfer method, the circuit configuration is very simple, but due to the characteristics of the method, the data transfer rate is slow and high speed control multi-micro is required. Not suitable for processor systems.

In order to solve this drawback, SDL as a method for performing the above-mentioned high-speed serial data transfer
There are packet communication technologies that represent C, HDLC, and the like.

However, in such a packet communication technique, the secondary address 30 following the opening flag 301 in the packet data shown in FIG.
The node that receives this packet data is determined by 2. However, in general, this secondary address 302 differs from node to node, and a packet with a certain secondary address cannot be received by arbitrary multiple microprocessor systems. There is.

The global address method solves this problem. When the global address is designated as the secondary address, all nodes can receive this packet.

However, in this method, the microprocessor system that does not need to receive the packet data must also receive the data, and this process has a problem that it takes time.

That is, in the method using only the global address, it is necessary to receive all packets generated in the multi-microprocessor system.
The larger the number of nodes forming the multi-microprocessor system, the longer the processing time for a received packet not used by the own microprocessor system.

In order to solve this problem, as described above, as shown in FIG. 5, a plurality of nodes connected by a loop data transmission line and a microprocessor system for arbitrating the loop transmission line. There is a system configured by the loop arbitration processor 200.

In this system, a plurality of arbitrary nodes receive one packet data while using the global address, and a node which does not need to receive this packet data receives the packet by the bypass function of the data transmission path. It had the advantage of not having to receive it.

However, since this system realizes various node control by connecting the loop arbitration processor and each node with a plurality of control units, a complicated protocol is required not only in terms of hardware scale but also in software. There is a drawback that

An object of the present invention is to solve the above-mentioned problems of the conventional data transfer system, and to realize a relatively high speed serial data transfer with a simple circuit and interface signal and a simple program processing. It is to provide a system and a serial data transfer circuit.

[0034]

A multi-microprocessor system according to the present invention is a multi-microprocessor system in which a plurality of microprocessor systems are operated in an integrated manner to divide and speed up processing.
A reception node selection signal line for connecting the plurality of microprocessor systems by a loop-shaped serial data transmission line and transmitting a reception node selection signal designating at least one other microprocessor system from any microprocessor system. Is connected to the plurality of microprocessor systems in a loop, and data is transmitted in one direction via the serial data transmission path using the microprocessor system designated by the reception node selection signal as a reception node.

The serial data transfer circuit of the present invention is
A reception node selection signal in which a plurality of microprocessor systems are connected in a loop by a serial data transmission line and a reception node selection signal for designating at least one other microprocessor as a data reception destination from any microprocessor is transmitted. A serial data transfer circuit arranged in each microprocessor system that constitutes a multiprocessor system that is connected in a loop by a line to transfer serial data. The serial data transfer circuit receives a reception node selection signal from an upstream microprocessor system and outputs it. A reception node signal decoding unit that determines whether the processor system is a reception node,
An input data selection unit for inputting data sent from an upstream microprocessor system and selecting and outputting whether or not the data is addressed to its own microprocessor system based on the judgment result of the reception node signal decoding unit, and its own microprocessor. A data communication unit for transmitting and receiving data relating to the system, an output data selection unit for selectively outputting output data of either the data communication unit or the input data processing unit based on the judgment result of the reception node signal decoding unit, and the reception An I / O port for inputting a node selection signal and outputting the reception node selection signal when the own microprocessor system transmits data, and the reception node output from the upstream microprocessor system or the I / O port No output to select and output any of the selection signals A signal selector configured to include a microprocessor for connecting said I / O port and the data communication unit and the address bus and via the data bus.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a microprocessor system including a serial data transfer circuit according to an embodiment of the present invention.

In the embodiment shown in FIG. 1, a microprocessor 10, an I / O port 11, a data communication unit 12 for transmitting and receiving data, and a node to be received sent from an upstream microprocessor system are designated. Reception node signal decoding unit 1 for decoding reception node selection signal 20
3, an input data selection unit 14 for selecting whether to supply or bypass the input data to the data communication unit 12, and an output data output from the data communication unit 12 or a bypass output of the input data selection unit 14. An output data selection unit 15 for selecting whether to perform or not, and a node signal selection unit for selectively outputting either the reception node signal 21 received via the I / O port 11 or the reception node selection signal 20 transmitted from the upstream microprocessor system. 16 and 16.

Next, the operation of this embodiment will be described.

The reception node selection signal 20 output from the upstream microprocessor system and designating whether or not the node should receive the packet data is sent to the reception node signal decoding unit 13, the I / O port 11 and the node signal selection unit 16. Is entered.

The reception node signal decoding unit 13 decodes the input reception node selection signal 20, determines whether or not the reception data 27 and the reception node selection signal 20 should be bypassed, and specifies whether or not the reception data 27 is bypassed. The reception data bypass signal 23 and the reception node bypass signal 24 designating the presence / absence of bypass to the node are output.

The received data bypass signal 23 is supplied to the input data selection section 14 and the output data selection section 15, and when the received data bypass signal 23 specifies bypass, the input data selection section 14 receives the received data 27. Is not supplied to the data communication unit 12, but is sent to the output data selection unit 15 as received data 30.

The output data selection unit 15 sends the data provided from the input data selection unit 14 to the downstream microprocessor system as the transmission data 31.

On the contrary, when the specified content of the reception data bypass signal 23 is not data bypass, the input data selection unit 14 supplies the reception data 27 to the data communication unit 12 and does not flow it to the output data selection unit 15. ..

The output data selection unit 15 is the data communication unit 1
The output data 29 from 2 is sent to the downstream microprocessor system as transmission data 31.

The receiving node signal decoding unit 13 also
The reception node selection signal 20 transmitted by the upstream microprocessor system is decoded and the reception node selection signal 20
When the designated state of indicates that the data transmission path is empty (open) or the local microprocessor system can transmit data, the receiving node bypass signal 2
4 is turned off (state not bypassed).

The reception node bypass signal 24 is input to the node signal selection unit 16, and when the reception node bypass signal 24 specifies bypass, the node signal selection unit 16
Selects the reception node selection signal 20 input from the upstream microprocessor system, and the reception node selection signal 2
2 to the downstream microprocessor system.

On the contrary, when the receiving node bypass signal 24 does not specify bypass, the node signal selecting section 16 causes the I / O.
The reception node selection signal 21 output from the port 11 is selected and sent as a reception node selection signal 22 to the downstream microprocessor system.

The microprocessor 10 receives I / O when its own microprocessor system sends data.
The reception node selection signal 20 from the upstream microprocessor system is input through the O port 11 and it is checked whether or not the transmission path is empty.

If the transmission line shows an empty state, the corresponding reception node selection signal 21 is output to the node signal selection unit 6 via the I / O port 11. When this microprocessor system is not transmitting data, the receiving node selection signal 21 outputs a state in which the transmission path is empty.

The microprocessor 10 requesting the data transmission sends the reception node selection signal 20 output from the upstream microprocessor system to the I / O port 11
The data can be transmitted if the received node selection signal 21 output from its own microprocessor is input and checked via the.

On the contrary, if the upstream microprocessor system makes a data transmission request and outputs the reception node selection signal 20, the reception node signal decoding unit 13
Determines whether or not the selected node is designated by its own microprocessor system, and turns on / off the reception data bypass signal 23 according to whether or not it is designated. Also at this time,
The reception node bypass signal 24 is in the bypass designation state, and the reception node selection signal 20 is the reception node selection signal 22.
Is output from the node signal selection unit 16 and is transferred to the downstream microprocessor system.

The received data 27 input to the input data selection unit 14 bypasses the data communication unit 28 as the received data 30 when the received data bypass signal 23 specifies the bypass, and the received data 27 is sent from the data selection unit 15. 31 is transferred to the downstream microprocessor system.

On the contrary, when the received data bypass signal 23 does not specify bypass, the received data 27 is supplied to the data communication section 12 as the received data 28 via the input data selecting section 14.

The microprocessor 10 reads the received data from the data communication unit 12 via the data bus 26 during data reception. The data being received is output as the output data 29 of the data communication unit 12 by the output data selection unit 15.
To the microprocessor system further downstream as transmission data 31.

On the other hand, the microprocessor 10 which is transmitting data writes the data to be transmitted via the data bus 26 into the data transmitting unit 12. The written data is transferred from the data communication unit 12 to the output data selection unit 15 as the output data 29, and is sent as the transmission data 31 to the downstream microprocessor system.

FIG. 2 shows an example of a multi-microprocessor system in which the high-speed serial data transfer circuit shown in FIG. 1 is used and connected by a loop-shaped data transmission line CH and a reception node selection signal line L.

In the multi-microprocessor system shown in FIG. 2, the reception-node selection signal S sent out on the reception-node selection signal line L is a number representing the number (kind) of packets flowing in the multi-microprocessor system + 1 at the maximum.
It suffices if the state of can be expressed. For example, if there are 15 types of packets flowing in the multi-microprocessor system, the reception node selection signal can be composed of 4 bits.

FIG. 2 shows n microprocessor systems, that is, microprocessor system (A) (node (A)) 101 to microprocessor system (n).
The (node (n)) 10n is connected in a loop by the data transmission line CH, and the reception node selection signal S is also sequentially transmitted through the respective microprocessor systems via the reception node selection signal line L.

In the loop network shown in FIG.
It is assumed that one microprocessor can send data to any one or a plurality of microprocessor systems.

When the loop system of FIG. 2 is compared with FIG. 5 showing a conventional example in which the same loop system is used, it is not necessary to have a loop arbitration processor that arbitrates the loop transmission line, so that the total system is The hardware scale and software scale can be significantly reduced.

FIG. 3 is a block diagram showing the state of the transmission path at the time of data transfer in the multi-microprocessor system of FIG. 2, and FIG. 4 is a diagram showing the contents of the reception node selection signal S in FIG.

In the configuration of the multi-microprocessor system shown in FIG. 3, eight microprocessor systems, node (A) 101 to node (H) 108, are connected in a loop by a data transmission line CH, and also in a loop. The state in which the reception node selection signal S is next transferred between the nodes via the reception node selection signal line L is shown. Each data communication unit 12 is also shown in each node.

Now, as an example, the node (A) 101 is the generation source, and the node (C) 103 and the node (E) 10 are
5, when the receiving node selection signal S is changed from the "empty state" to the "state a" when trying to transfer the data to the node 5, the node (C) 1
03 and node (E) 105 are the receiving nodes,
The data communication units 12 of the other nodes are bypassed from the data transmission path CH as shown in FIG.

Further, the reception node selection signal S in the "state a"
Returns to the originating node (A) 101 via the looped reception node selection signal line L, so that the node (A) 101 can transmit data.

After the data transmission is completed, the node (A) 101 returns the receiving node selection signal S to the "vacant state".

In this way, in the microprocessor systems other than the microprocessor systems involved in the data transmission and the medical examination, the data flowing on the data transmission path is bypassed by the hardware and is not input to the data communication unit, so that the data receiving section receives the data. It is not necessary to perform the accompanying processing.

Further, even when a plurality of microprocessor systems generate a request for data transmission at substantially the same time, the data transmission node is determined with priority in terms of hardware so that the data transmission node can be realized by software. No complicated protocols are needed.

The only protocol required is the following rules for the microprocessor system on the data transmission side.

That is, the microprocessor system for transmitting data checks the reception node selection signal output from the upstream microprocessor system, and if it is in the unused state, applies the reception node selection signal to the downstream microprocessor system. To select signal.
After that, the microprocessor that made the data transmission request checks the reception node selection signal output from the upstream microprocessor system again, and only when this becomes the same as the reception node selection signal output from its own microprocessor system, The data communication unit is set to the data transmission mode and packet data is transmitted. In other cases, the data reception mode is set, and it is sufficient to wait for this reception node selection signal to change.

Since a global address can be used as the secondary address in this system, the data communication unit can be easily realized by using the conventional SDLC and HDLC architectures.

In this way, a relatively high-speed serial data transfer can be ensured by the interface signal of which the structure of the data transfer circuit is remarkably simplified and the number of which is greatly reduced.

[0073]

As described above, according to the present invention, by performing a relatively high-speed serial data transfer with a data transfer circuit having a simple structure and a significantly compressed interface signal, a conventional loop-shaped multi-micro Compared with the processor system, the waiting time required for arbitration of the data transmission line is significantly reduced, and the protocol required for arbitration of the data transmission line can be greatly simplified.

Further, similarly to the conventional example, the microprocessor system which is not related to the data transmission / reception can operate independently of the data transfer and requires no software intervention, so that the processing capacity of the microprocessor is utilized to the maximum extent. The effect is that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microprocessor system including a serial data transfer circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a multi-microprocessor system according to an embodiment of the present invention.

3 is a block diagram showing a state of a transmission line at the time of data transfer in the multi-microprocessor system of FIG.

FIG. 4 is a diagram showing the node decode contents of a reception node selection signal S in FIG.

FIG. 5 is a block diagram showing a configuration of a conventional multi-microprocessor system connected by a loop data transmission line.

FIG. 6 SDLC and HDL of conventional serial data communication
It is a figure which shows the format of the packet data of C.

[Explanation of symbols]

10 Microprocessor 11 I / O Port 12 Data Communication Unit 13 Reception Node Signal Decoding Unit 14 Input Data Selection Unit 15 Output Data Selection Unit 16 Node Signal Selection Unit 101 to 10n Microprocessor System (A)
(Node (A))-Microprocessor system (n)
(Node (n)) 200 Loop arbitration processor 201 to 208 Node A to node H

Claims (2)

[Claims] 1. A multi-microprocessor system in which a plurality of microprocessor systems are operated in an integrated manner to divide and speed up processing, and the plurality of microprocessor systems are connected by a lube-shaped serial data transmission line. In addition, a receiving node selecting signal line for sending a receiving node selecting signal designating at least one other arbitrary microprocessor system from any microprocessor system is connected to the plurality of microprocessor systems in a loop form, and the receiving node selecting signal line is connected to the plurality of microprocessor systems. A multi-microprocessor system in which data is transmitted in one direction through the serial data transmission path by using a microprocessor system designated by a node selection signal as a receiving node. 2. A plurality of microprocessor systems are connected in a loop by a serial data transmission line, and an arbitrary microprocessor sends a reception node selection signal designating at least one other arbitrary microprocessor as a data receiving destination. A serial data transfer circuit arranged in each microprocessor system forming a multiprocessor system for transferring serial data connected in a loop by a receiving node selection signal line From the receiving node signal decoding unit that receives the data from the upstream microprocessor system and that receives the data sent from the upstream microprocessor system. Based on the judgment results of the input data selection unit for selectively outputting whether or not it is addressed to the own microprocessor system, the data communication unit for transmitting and receiving data relating to the own microprocessor system, and the reception node signal decoding unit. An output data selection unit that selectively outputs output data of either the data communication unit or the input data processing unit, and the reception node selection signal when the reception node selection signal is input and the own microprocessor system transmits data. I / O that outputs
A port, a node signal selecting section for selectively outputting either the receiving node selecting signal output from an upstream microprocessor system or the I / O port, the I / O port, the data communication section, an address bus, and A serial data transfer circuit comprising a microprocessor connected through a data bus.