JPH05244602A - Satellite broadcasting transmission/reception device - Google Patents

Satellite broadcasting transmission/reception device

Info

Publication number
JPH05244602A
JPH05244602A JP4044104A JP4410492A JPH05244602A JP H05244602 A JPH05244602 A JP H05244602A JP 4044104 A JP4044104 A JP 4044104A JP 4410492 A JP4410492 A JP 4410492A JP H05244602 A JPH05244602 A JP H05244602A
Authority
JP
Japan
Prior art keywords
circuit
value
signal
error flag
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4044104A
Other languages
Japanese (ja)
Inventor
Satoshi Nonaka
聡 野中
Masashi Ota
正志 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4044104A priority Critical patent/JPH05244602A/en
Publication of JPH05244602A publication Critical patent/JPH05244602A/en
Pending legal-status Critical Current

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  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Picture Signal Circuits (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To set the control of a noise removal circuit to be satisfactory with simple circuit constitution by executing control in accordance with the error flag of an error correction circuit so as to return a signal to a correct PCM sound signal. CONSTITUTION:The pulse of the error flag in the error correction circuit of a PCM decoder 2 is supplied to an integrating circuit 16. It obtains a pulse as a DC detection signal corresponding to a duty ratio and supplies it to the variable gain amplifier circuit 1e of the noise removal circuit 1 as a gain control signal. When a C/N value is deteriorated, the duty ratio in the high level of the error flag becomes large, and a DC detection signal becomes large. Since the circuit 1 is controlled in accordance with the error flag of the error correction circuit provided for the PCM decoder 2, the DC detection signal obtained through the circuit 16 is proportional to the C/N value of an input signal. Thus, the circuit 1 is controlled by the C/N value and noise removal quantity increases in accordance with the deterioration of the C/N value. Then, the detection circuit of the detection value of the C/N value becomes unnecessary, and the circuit 1 can satisfactorily be controlled with simple constitution.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は衛星放送を受信する衛星
放送受信装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcast receiver for receiving satellite broadcasts.

【0002】[0002]

【従来の技術】一般に衛星放送を受信する衛星放送受信
装置の映像の信号対雑音比(S/N)の値は入力電波信
号の電界強度ではなく受信電力対雑音比(C/N)の値
によって一義的に決まる。この衛星放送受信装置のC/
N値は衛星から送られてくる送信電力、気象条件、コン
バータの性能、アンテナの口径で決まる。
2. Description of the Related Art Generally, the value of the signal-to-noise ratio (S / N) of the image of a satellite broadcast receiving apparatus that receives satellite broadcast is not the electric field strength of the input radio signal but the value of the received power-to-noise ratio (C / N) Is uniquely determined by C / of this satellite broadcasting receiver
The N value is determined by the transmission power sent from the satellite, weather conditions, converter performance, and antenna diameter.

【0003】従来、衛星放送受信装置において、このC
/N値が悪化したときにも映像S/N値の悪化を少しで
も少なくする為に、映像信号系に入力映像信号に入力映
像信号よりハイパスフィルタを介して得た雑音成分を極
性反転して混合するようにした雑音除去回路を設け、こ
のC/N値が悪化したときにこの雑音除去回路を手動的
又は自動的に動作させる如くしていた。
Conventionally, in a satellite broadcast receiving apparatus, this C
In order to reduce the deterioration of the video S / N value as much as possible even when the / N value deteriorates, the polarity of the noise component obtained from the input video signal through the high-pass filter in the video signal system is inverted. A noise eliminating circuit adapted to be mixed is provided, and when the C / N value is deteriorated, the noise eliminating circuit is operated manually or automatically.

【0004】この雑音除去回路を自動的に動作させると
きは、このC/N値を検出する必要があるが、このC/
N値を検出するのに衛星放送信号の帯域外の雑音を検出
して、その雑音量をC/N値に換算する等が行われてい
た。
When the noise eliminating circuit is automatically operated, it is necessary to detect the C / N value.
In order to detect the N value, noise outside the band of the satellite broadcast signal is detected, and the noise amount is converted into a C / N value.

【0005】[0005]

【発明が解決しようとする課題】然しながら、この衛星
放送信号の帯域外の雑音を検出して、その雑音量をC/
N値に換算するときは、比較的その回路構成が複雑で、
比較的高価となる不都合があった。
However, the noise outside the band of the satellite broadcast signal is detected, and the noise amount is calculated as C /
When converting to N value, the circuit configuration is relatively complicated,
There was the inconvenience of becoming relatively expensive.

【0006】本発明は斯る点に鑑み比較的簡単な回路構
成で良好に雑音除去回路を制御することができるように
することを目的とする。
SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to make it possible to favorably control a noise elimination circuit with a relatively simple circuit configuration.

【0007】[0007]

【課題を解決するための手段】本発明衛星放送受信装置
は例えば図1に示す如く、映像信号系に設けた雑音除去
回路1を正しいPCM音声信号に戻すPCMデコーダ2
に設けたエラー訂正回路のエラーフラッグに応じて制御
するようにしたものである。また、本発明衛星放送受信
装置は例えば図1に示す如く映像信号系に設けた雑音除
去回路1と、正しいPCM音声信号に戻すPCMデコー
ダ2とを有し、このPCMデコーダ2に設けたエラー訂
正回路のエラーフラッグに応じた直流検出信号を得るよ
うになし、この直流検出信号により、この雑音除去回路
1の雑音除去量を制御するようにしたものである。
A satellite broadcast receiving apparatus of the present invention, for example, as shown in FIG. 1, has a PCM decoder 2 for returning a noise removing circuit 1 provided in a video signal system to a correct PCM audio signal.
The control is performed according to the error flag of the error correction circuit provided in. Further, the satellite broadcast receiving apparatus of the present invention has, for example, as shown in FIG. 1, a noise removing circuit 1 provided in a video signal system and a PCM decoder 2 for returning a correct PCM audio signal, and an error correction provided in the PCM decoder 2 is provided. A DC detection signal corresponding to the error flag of the circuit is obtained, and the noise removal amount of the noise removal circuit 1 is controlled by the DC detection signal.

【0008】[0008]

【作用】本発明によればPCMデコーダ2に設けたエラ
ー訂正回路のエラーフラッグに応じて雑音除去回路1を
制御するようにしており、このPCMデコーダ2のエラ
ー訂正回路のエラーフラッグは入力信号のC/N値に比
例しているので、このC/N値で雑音除去回路1を制御
したのと同等であり、この雑音除去回路1を良好に制御
できると共にPCMデコーダ2のエラーフラッグを兼用
するので、C/N値を検出する回路構成が不要である。
According to the present invention, the noise removal circuit 1 is controlled in accordance with the error flag of the error correction circuit provided in the PCM decoder 2. The error flag of the error correction circuit of the PCM decoder 2 is the input signal. Since it is proportional to the C / N value, it is equivalent to controlling the noise removing circuit 1 with this C / N value. This noise removing circuit 1 can be well controlled and also serves as an error flag of the PCM decoder 2. Therefore, the circuit configuration for detecting the C / N value is unnecessary.

【0009】また、本発明によればこのエラー訂正回路
のエラーフラッグに応じて雑音除去回路1の雑音除去量
を制御しているのでC/N値の悪いときは雑音除去量を
多くし(解像度犠牲にし)、C/N値が良いときは雑音
除去量を少なくするので、映像S/Nを略一定に保つこ
とができる。
Further, according to the present invention, since the noise removal amount of the noise removal circuit 1 is controlled according to the error flag of this error correction circuit, when the C / N value is bad, the noise removal amount is increased (resolution). If the C / N value is good, the noise removal amount is reduced, so that the image S / N can be kept substantially constant.

【0010】[0010]

【実施例】以下図面を参照して、本発明衛星放送受信装
置の一実施例につき説明しよう。図1において3は放送
衛星を示し、この放送衛星3よりの12GHz帯の衛星
放送信号をBSアンテナ4にて受信する如くする。この
BSアンテナ4のBSコンバータ4aにより1GHz帯
に変換された衛星放送信号をBSケーブル5を介してB
Sチューナ6に供給する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the satellite broadcast receiving apparatus of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 3 denotes a broadcasting satellite, and the satellite broadcasting signal in the 12 GHz band from the broadcasting satellite 3 is received by the BS antenna 4. The satellite broadcasting signal converted into the 1 GHz band by the BS converter 4a of the BS antenna 4 is transmitted to the B via the BS cable 5.
Supply to the S tuner 6.

【0011】このBSチューナ6よりの信号を映像信号
系を構成するバッファ増幅回路7及び4.5MHz以下
の信号を通過するローパスフィルタ8を介してディエン
ファシス回路9に供給し、このディエンファシス回路9
の出力側に得られる映像信号をクランプ回路10を介し
て輝度信号とクロマ信号とに分離するY/C分離回路1
1に供給する。
The signal from the BS tuner 6 is supplied to a de-emphasis circuit 9 through a buffer amplifier circuit 7 which constitutes a video signal system and a low-pass filter 8 which passes a signal of 4.5 MHz or less, and the de-emphasis circuit 9 is supplied.
Y / C separation circuit 1 that separates the video signal obtained at the output side of the
Supply to 1.

【0012】このY/C分離回路11に得られるクロマ
信号Cをクロマ信号出力端子11Cに供給すると共にこ
のY/C分離回路11に得られる輝度信号Yを雑音除去
回路1を介して輝度信号出力端子12に供給する如くす
る。
The chroma signal C obtained by the Y / C separating circuit 11 is supplied to the chroma signal output terminal 11C, and the luminance signal Y obtained by the Y / C separating circuit 11 is outputted through the noise eliminating circuit 1 as a luminance signal. It is supplied to the terminal 12.

【0013】この雑音除去回路1としては入力輝度信号
を混合回路1aに供給すると共にこの入力輝度信号をハ
イパスフィルタ1bに供給して雑音成分を抽出し、この
雑音成分をリミッタ回路1cを介して極性を反転する極
性反転回路1dに供給し、この極性反転回路1dの出力
側に得られる極性が反転された雑音成分を可変利得増幅
回路1eを介してこの混合回路1aに供給し、この混合
回路1aの出力信号を輝度信号出力端子12に供給する
如くする。この混合回路1aにおいては入力輝度信号に
極性が反転された雑音成分が加算され、入力輝度信号の
雑音成分がキャンセルされる。また、この可変利得増幅
回路1eの利得は後述するPCMデコーダ2のエラー訂
正回路のエラーフラグにより制御する如くする。
The noise removing circuit 1 supplies the input luminance signal to the mixing circuit 1a and also supplies the input luminance signal to the high-pass filter 1b to extract a noise component, and the noise component is polarized through the limiter circuit 1c. Is supplied to the polarity inverting circuit 1d for inverting, and the noise component whose polarity has been obtained at the output side of the polarity inverting circuit 1d is supplied to the mixing circuit 1a via the variable gain amplifying circuit 1e, and the mixing circuit 1a is supplied. The output signal of is supplied to the luminance signal output terminal 12. In this mixing circuit 1a, the noise component whose polarity is inverted is added to the input luminance signal, and the noise component of the input luminance signal is canceled. The gain of the variable gain amplifier circuit 1e is controlled by an error flag of an error correction circuit of the PCM decoder 2 which will be described later.

【0014】このクロマ信号出力端子11Cに得られる
クロマ信号Cと輝度信号出力端子12に得られる輝度信
号Yとを周知の如く映像信号処理回路に供給して赤色信
号R、緑色信号G及び青色信号Bを得、之等を例えばカ
ラー陰極線管に供給する如くする。
The chroma signal C obtained at the chroma signal output terminal 11C and the luminance signal Y obtained at the luminance signal output terminal 12 are supplied to a video signal processing circuit, as is well known, and a red signal R, a green signal G and a blue signal are supplied. B is obtained and the information is supplied to, for example, a color cathode ray tube.

【0015】またBSチューナ6の出力側に得られる信
号を音声信号系を構成する5.73MHzの信号を通過
するバンドパスフィルタ13を介してQPSK復調回路
14に供給し、このQPSK復調回路14の出力信号を
PCMデコーダ2に供給する。
The signal obtained at the output side of the BS tuner 6 is supplied to a QPSK demodulation circuit 14 via a bandpass filter 13 which passes a 5.73 MHz signal forming an audio signal system. The output signal is supplied to the PCM decoder 2.

【0016】このPCMデコーダ2は周知の如くPCM
の符合列の信号をデスクランブル及びデインターリーブ
して元の正しいディジタル信号にするもので、ビット誤
りの訂正をするエラー訂正回路及び補間回路等が含まれ
ている。
As is well known, the PCM decoder 2 is a PCM decoder.
The signal of the code string is descrambled and deinterleaved to the original correct digital signal, which includes an error correction circuit and an interpolation circuit for correcting bit errors.

【0017】このPCMデコーダ2のエラー訂正回路の
エラーフラッグはビット誤り検出信号出力、訂正能力を
越えるビット誤りが存在する区間ハイレベル“H”とな
る。この場合C/N値が劣化していくと音声データのビ
ット誤りが発生し始め、ビット誤りが多くなるとハイレ
ベル“H”の区間が多くなり、パルスの形としては図2
Cに示す如くハイレベル“H”の区間の大きいデューテ
ィ比のパルスが得られる。
The error flag of the error correction circuit of the PCM decoder 2 is at the high level "H" in the section where there is a bit error detection signal output and a bit error exceeding the correction capability. In this case, as the C / N value deteriorates, bit errors in the audio data begin to occur, and as the number of bit errors increases, the high level “H” section increases, and the pulse shape is as shown in FIG.
As shown in C, a pulse having a large duty ratio in the high level "H" section is obtained.

【0018】図2AはC/N値の劣化がないときのエラ
ーフラッグであり、図2BはこのC/N値の劣化が発生
し始めたときのエラーフラッグであり、従ってこのPC
Mデコーダ2のエラー訂正回路のエラーフラッグはC/
N値に応じたディーテ比のパルスが得られる。
FIG. 2A is an error flag when there is no deterioration of the C / N value, and FIG. 2B is an error flag when the deterioration of the C / N value starts to occur, and therefore this PC
The error flag of the error correction circuit of the M decoder 2 is C /
A pulse having a duty ratio according to the N value can be obtained.

【0019】このPCMデコーダ2に得られるPCM音
声信号をPCM音声信号処理回路15に供給し、このP
CM音声信号処理回路15においてアナログ音声信号に
変換してスピーカに供給する如くする。
The PCM audio signal obtained by the PCM decoder 2 is supplied to the PCM audio signal processing circuit 15, and the P
The CM audio signal processing circuit 15 converts the analog audio signal and supplies it to the speaker.

【0020】本例においては、このPCMデコーダ2の
エラー訂正回路の図2に示す如きエラーフラッグのパル
スを積分回路16に供給する。この積分回路16にてエ
ラーフラッグのパルスをデューティ比に応じた直流値の
直流検出信号を得、この直流検出信号を雑音除去回路1
の可変利得増幅回路1eに利得制御信号として供給する
如くする。
In this example, the error flag pulse of the error correction circuit of the PCM decoder 2 as shown in FIG. 2 is supplied to the integration circuit 16. The integration circuit 16 obtains a DC detection signal having a DC value corresponding to the duty ratio of the error flag pulse, and the DC detection signal is supplied to the noise removal circuit 1
The variable gain amplifying circuit 1e is supplied as a gain control signal.

【0021】この場合、C/N値の劣化がないときには
図2Aに示す如くエラーフラッグのハイレベル“H”区
間がないので積分回路16の出力側の直流検出信号は零
であり、このときは可変利得増幅回路1eは不動作とな
り混合回路1aに供給される雑音成分がなく、この雑音
のキャンセル量はなく、この雑音除去回路1は不動作と
なる。
In this case, when there is no deterioration of the C / N value, there is no high level "H" section of the error flag as shown in FIG. 2A, so that the DC detection signal on the output side of the integrating circuit 16 is zero. The variable gain amplifier circuit 1e does not operate, there is no noise component supplied to the mixing circuit 1a, there is no canceling amount of this noise, and the noise removing circuit 1 does not operate.

【0022】また、可変利得増幅回路1eの利得はこの
直流検出信号の大きさにより決まりC/N値が劣化した
ときには、それだけエラーフラッグのハイレベル“H”
のディーティ比が大となり、それだけ直流検出信号が大
きくなるので、この可変利得増幅回路1eよりの雑音成
分が大きくなり、混合回路1aにおける雑音成分のキャ
ンセル量がそれだけ大きくなる。この場合輝度信号中の
このキャンセル量に応じて高域成分がそれだけ少なくな
るので解像度をそれだけ犠牲にすることとなる。その他
は従来の衛星放送受信装置と同様に構成する。
Further, the gain of the variable gain amplifier circuit 1e is determined by the magnitude of the DC detection signal, and when the C / N value is deteriorated, the high level "H" of the error flag is correspondingly increased.
Since the duty ratio of the variable gain amplifier circuit 1e becomes large and the DC detection signal becomes large accordingly, the noise component from the variable gain amplifier circuit 1e becomes large, and the canceling amount of the noise component in the mixing circuit 1a becomes large accordingly. In this case, the amount of high frequency components is reduced according to the amount of cancellation in the luminance signal, so that the resolution is sacrificed. Others are configured similarly to the conventional satellite broadcast receiving device.

【0023】本例は上述の如く構成されているのでPC
Mデコーダ2に設けたエラー訂正回路のエラーフラッグ
に応じて雑音除去回路1を制御しており、このPCMデ
コーダ2のエラー訂正回路のエラーフラッグを積分回路
16を介して得られる直流検出信号は入力信号のC/N
値に比例しているので、このC/N値でこの雑音除去回
路1を制御したのと同等であり、この雑音除去回路1を
良好に制御できると共に、このPCMデコーダ2のエラ
ーフラッグを兼用するので、C/N値を検出する回路構
成が不要であり、それだけ回路構成が簡単となり、それ
だけ安価となる。
Since this example is constructed as described above, a PC
The noise removal circuit 1 is controlled according to the error flag of the error correction circuit provided in the M decoder 2, and the error detection circuit of the error correction circuit of the PCM decoder 2 receives the DC detection signal obtained via the integration circuit 16 as an input. C / N of signal
Since it is proportional to the value, it is equivalent to controlling the noise eliminating circuit 1 with this C / N value, and the noise eliminating circuit 1 can be well controlled and also serves as an error flag of the PCM decoder 2. Therefore, the circuit configuration for detecting the C / N value is unnecessary, the circuit configuration is simpler, and the cost is lower.

【0024】また本例によれば、このPCMデコーダ2
のエラー訂正回路のエラーフラッグに応じた直流検出信
号を得、この直流検出信号に応じて雑音除去回路1の雑
音除去量を制御しC/N値の劣化に応じて雑音除去量を
多くしているので映像S/Nを略一定に保つことができ
る利益がある。
According to this example, the PCM decoder 2
The DC detection signal corresponding to the error flag of the error correction circuit is obtained, the noise removal amount of the noise removal circuit 1 is controlled according to the DC detection signal, and the noise removal amount is increased according to the deterioration of the C / N value. Therefore, there is an advantage that the image S / N can be kept substantially constant.

【0025】尚上述実施例においては直流検出信号を得
るのにエラーフラッグを直接積分回路16に供給して得
たが、この代わりにエラーフラッグのパルスのハイレベ
ル“H”の区間に対応する数のパルスを得、このパルス
数に応じた直流を得るようにして直流検出信号を得るこ
ともできる。また本発明は上述実施例に限ることなく本
発明の要旨を逸脱することなく、その他種々の構成が採
り得ることは勿論である。
In the above embodiment, the error flag was directly supplied to the integrating circuit 16 to obtain the DC detection signal, but instead of this, the number corresponding to the high level "H" section of the error flag pulse is obtained. It is also possible to obtain a DC pulse and obtain a DC corresponding to the number of pulses to obtain a DC detection signal. Further, the present invention is not limited to the above-described embodiments, and needless to say, various other configurations can be adopted without departing from the gist of the present invention.

【0026】[0026]

【発明の効果】本発明によればPCMデコーダ2に設け
たエラー訂正回路のエラーフラッグに応じて雑音除去回
路1を制御しているので、この雑音除去回路を良好に制
御できると共にこのエラーフラッグを兼用するのでC/
N値を検出する回路構成が不要であり、それだけ回路構
成が簡単となり、それだけ安価となる。
According to the present invention, since the noise removing circuit 1 is controlled according to the error flag of the error correcting circuit provided in the PCM decoder 2, the noise removing circuit can be well controlled and the error flag can be controlled. Since it is also used, C /
A circuit configuration for detecting the N value is not necessary, the circuit configuration is simpler, and the cost is lower.

【0027】また本発明によればこのPCMデコーダの
エラーフラッグに応じた直流検出信号を得、この直流検
出信号に応じて雑音除去回路1の雑音除去量を多くして
いるので映像S/Nを略一定に保つことができる利益が
ある。
Further, according to the present invention, the DC detection signal corresponding to the error flag of the PCM decoder is obtained, and the noise removal amount of the noise removal circuit 1 is increased in accordance with the DC detection signal, so that the video S / N is improved. There are benefits that can be kept approximately constant.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明衛星放送受信装置の一実施例を示す構成
図である。
FIG. 1 is a block diagram showing an embodiment of a satellite broadcast receiving apparatus of the present invention.

【図2】本発明の説明に供する線図である。FIG. 2 is a diagram for explaining the present invention.

【符号の説明】 1 雑音除去回路 1a 混合回路 1b ハイパスフィルタ 1d 極性反転回路 1e 可変利得増幅回路 2 PCMデコーダ[Description of Reference Signs] 1 noise elimination circuit 1a mixing circuit 1b high-pass filter 1d polarity reversing circuit 1e variable gain amplification circuit 2 PCM decoder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 映像信号系に設けた雑音除去回路を正し
いPCM音声信号に戻すPCMデコーダに設けたエラー
訂正回路のエラーフラッグに応じて制御するようにした
ことを特徴とする衛星放送受信装置。
1. A satellite broadcast receiving apparatus, characterized in that a noise removing circuit provided in a video signal system is controlled according to an error flag of an error correction circuit provided in a PCM decoder for returning a correct PCM audio signal.
【請求項2】 映像信号系に設けた雑音除去回路と、正
しいPCM音声信号に戻すPCMデコーダとを有し、該
PCMデコーダに設けたエラー訂正回路のエラーフラッ
グに応じた直流検出信号を得るようになし、該直流検出
信号により上記雑音除去回路の雑音除去量を制御するよ
うにしたことを特徴とする衛星放送受信装置。
2. A noise removing circuit provided in a video signal system and a PCM decoder for returning to a correct PCM audio signal so as to obtain a DC detection signal according to an error flag of an error correction circuit provided in the PCM decoder. According to another aspect of the present invention, there is provided a satellite broadcast receiving apparatus characterized in that the noise removal amount of the noise removal circuit is controlled by the DC detection signal.
JP4044104A 1992-02-28 1992-02-28 Satellite broadcasting transmission/reception device Pending JPH05244602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4044104A JPH05244602A (en) 1992-02-28 1992-02-28 Satellite broadcasting transmission/reception device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4044104A JPH05244602A (en) 1992-02-28 1992-02-28 Satellite broadcasting transmission/reception device

Publications (1)

Publication Number Publication Date
JPH05244602A true JPH05244602A (en) 1993-09-21

Family

ID=12682311

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4044104A Pending JPH05244602A (en) 1992-02-28 1992-02-28 Satellite broadcasting transmission/reception device

Country Status (1)

Country Link
JP (1) JPH05244602A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018078507A (en) * 2016-11-11 2018-05-17 株式会社東芝 Electronic apparatus and display control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018078507A (en) * 2016-11-11 2018-05-17 株式会社東芝 Electronic apparatus and display control method

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