JPH05244584A - Decoding circuit - Google Patents

Abstract

PURPOSE:To improve the waveform characteristic of a horizontal synchronizing signal in a prediction decoding circuit for a Video signal. CONSTITUTION:A predicted decoding value of a horizontal synchronizing signal on a predetermined specific horizontal scanning line of a video signal is stored in a memory 12. A predicted decoding value (c) outputted from the memory 12 or a predicted decoding value (b) outputted from a prediction decoder 11 is selected by a changeover device 13 to obtain an analog reproduced value (f). Since the changeover device 13 is used to restore quantizer switching information (g) generated by a coding circuit, the predicted decoding value (c) is in use when a rough quantizer is selected and deterioration of bit segmentation noise having been generated in a linear quantizer onto a horizontal synchronizing signal is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal decoding circuit, and more particularly, to a video signal prediction including a plurality of quantizers which are switch-controlled in units of horizontal scanning lines and one or more predictors. The present invention relates to a decoding circuit that receives the output of an encoding circuit and performs predictive decoding of a video signal.

[0002]

2. Description of the Related Art Conventionally, a video signal coding circuit and a decoding circuit based on a predictive coding system are constructed as shown in FIGS. 2 and 3, respectively.

In the encoding circuit, an analog video input signal i is input to an A / D (analog / digital) converter 21 and converted into a digital signal. This A / D converter 21
Is output to the subtractor 22. The subtractor 22 detects the difference between the predicted value of the predictor 25 and the output value of the A / D converter 21, and the difference is supplied to the quantizer 23. A plurality of quantizers 23 are provided in parallel. A quantizer switching controller 26 is connected to the plurality of quantizers 23,
One of the quantizers 23 is selected based on the quantizer switching information g output from the quantizer switching controller 26, and is connected to the subtractor 22. Selected quantizer 23
Receives the output of the subtractor 22, quantizes it, and outputs it to the transmission line as the prediction error signal a. The quantizer 23 is a non-linear quantizer (DPCM) or a linear quantizer (PCM).
The switching is performed in units of horizontal scanning lines.

The quantizer switching controller 26 outputs the quantizer switching information g based on the buffer memory occupancy information j.
Here, the buffer memory occupancy information j is shown in the form of the difference between the transmission rate f _L and the information rate f _P of the prediction error signal in the transmission section that transmits the prediction error signal a obtained by this prediction encoding circuit. ing. If the occupancy is high, the difference between f _L and f _P is large. At this time, in the quantizer group, the quantizer 23 that performs coarse quantization is selected, and the degree of occupancy is reduced by performing coarse quantization and increasing f _P. On the other hand, if the occupancy is low, the difference between f _L and f _P will be small. At this time, in the quantizer group, the quantizer 23 that performs fine quantization is selected, and the occupation degree is increased by decreasing f _P.

A measurement error signal a output from the quantizer 23
Is also input to the adder 24. The output signal of the predictor 25 is also input to the adder 24, the added value of both is input again to the predictor 25, and a new predicted value is output.

On the other hand, in the decoding circuit, as shown in FIG. 3, the prediction error signal a from the transmission line is first input to the prediction decoder 11. In the prediction decoder 11, the prediction error signal a is input to both the predictor 18 and the adder 17. The adder 17 adds the prediction error signal a and the prediction value output from the predictor 18, and outputs the prediction decoded value b. This predicted composite value b is a D / A converter (digital / analog)
It is input to 14, converted into an analog signal, and output as an analog reproduction signal f.

[0007]

As described above, in the conventional coding circuit, the quantizer group is composed of a plurality of quantizers 23, and these quantizers 23 also store the buffer memory occupancy information j. And can be switched for each horizontal scanning line unit.

However, when a linear quantizer is used as the quantizer 23, a difference may occur between the bit number of the resolution of the A / D converter 21 and the bit number of the selected quantizer 23. is there. For example, when the resolution of the A / D converter 21 is set to 8 bits, the coarse quantization is 6 bits, 5
When the bit quantizer 23 is selected, the bits that cannot be quantized by the quantizer 23 are truncated, and the bit truncation amounts are 2 bits and 3 bits, respectively.

When bits are truncated in the quantizer 23 in this way, bit truncation noise occurs in that case. The bit truncation noise appears visually as streaking noise (horizontal stripes) when the quantizer 23 is switched in units of horizontal scanning lines. This is because the DC level of the horizontal sync signal changed due to the bit truncation. For this reason, there is a problem that streaking noise appears visually when a coarse quantization mode used to reduce the information speed f _P of the prediction error signal a is selected.

Conventionally, there is a so-called synchronization changing system in which a horizontal synchronizing signal is generated on the decoding circuit side. However, this system has a problem that the horizontal synchronizing signal level does not change even if the level of the input signal changes. It was

The present invention has been made in view of the above problems, and an object thereof is to prevent generation of noise due to switching of a quantizer and to change an output level in accordance with an input signal level. It is to provide a decoding circuit capable of

[0012]

SUMMARY OF THE INVENTION The present invention comprises a plurality of quantizers which are switch-controlled for each horizontal scanning line of a video signal.
A decoding circuit for decoding a video signal with a prediction error signal output from a prediction coding circuit including the above predictor, the prediction circuit having the same configuration as the predictor of the prediction coding circuit. A predictive decoder that receives the predictive error signal output from the predictive encoding circuit and outputs the predictive decoded value of the horizontal synchronizing signal present for each horizontal scanning line as the first predictive decoded value; A predicted decoded value storage unit that stores the predicted decoded value of the horizontal synchronization signal existing in the specified horizontal scanning line as a second predicted decoded value, and the second predicted value for each horizontal scanning line from the predicted decoded value storage unit. Reading means for reading a decoded value, and decoded value selecting means for selecting either the first predicted decoded value or the second predicted decoded value based on the quantizer switching information output from the predictive coding circuit. And this decrypted value selection means The-option prediction decoded value and a digital / analog conversion means for converting the analog signal. Here, the quantizer is in particular a linear quantizer.

In this decoding circuit, the prediction error signal obtained by the coding circuit is converted into the first prediction decoded value by the prediction decoder. A decoded value corresponding to a horizontal synchronization signal of a predetermined specific horizontal scanning line among the predicted decoded values is stored in the predicted decoded value storage means (memory) as a second predicted decoded value. From the memory, the second predictive decoded value is read out for each horizontal scanning line at any time. Based on the quantizer switching information from the encoding circuit, one of the two predicted decoded values is selected and reproduced as an analog value.

With such a structure, when a quantizer having a coarse quantization precision is selected, the horizontal synchronizing signal on the scanning line is changed to the horizontal synchronizing signal included in a predetermined specific horizontal scanning line. It is possible to switch to the decoded value (second predictive decoded value), whereby the analog reproduction value can be obtained. Therefore, the horizontal sync signal is not deteriorated by the bit truncation noise that has been generated when a quantizer having a coarse quantization precision is selected, and the streaking noise is not visually generated. Further, even if the level of the input signal changes, the horizontal sync signal level does not change.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a concrete structure of a decoding circuit according to an embodiment of the present invention. The same components as those of the conventional decoding circuit shown in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted.

In this decoding circuit, the prediction error signal a sent from the predictive coding circuit via a transmission line (not shown) is first input to the predictive decoder 11. The predictive decoder 11 converts the predictive error signal a into a predictive decoded value b. The predictive decoded value b output from the predictive decoder 11 is supplied to one input end of the switch 13. Further, of the predicted decoded value b, the predicted decoded value of the horizontal synchronizing signal corresponding to a specific horizontal scanning line predetermined by the scanning line switching unit 15 is stored in the memory 12.

The predictive decoded value stored in the memory 12 is read out as a predictive decoded value c for each horizontal scanning line at any time under the control of the switching signal d output from the scanning line switching unit 15. . The predicted decoded value c read from the memory 12 is supplied to the other input end of the switch 13. The switching device 13 further includes a switching controller 16
Are connected. The switching controller 16 outputs the predictive decoded value switching signal h to the switching device 13 based on the quantizer switching information g sent from the encoding circuit.

Under the control of the switching controller 16, the switch 13 selects either the predicted decoded value b or c and supplies it as the predicted decoded value e to the D / A converter 14.
The D / A converter 14 converts the predicted decoded value e into an analog signal and outputs it as an analog reproduction value f.

Next, the operation of the decoding circuit of this embodiment will be described.

The predictive error signal a output from the predictive coding circuit shown in FIG.
Is converted to. The predicted decoded value b is input to one input terminal of the switch 13. Further, of the predicted decoded value b, the predicted decoded value of the horizontal synchronizing signal corresponding to a specific horizontal scanning line predetermined by the scanning line switching unit 15 is stored in the memory 12. The predictive decoded value c is read from the memory 12 for each horizontal scanning line at any time. On the other hand, the switching controller 16 outputs a predictive decoded value switching signal h based on the quantizer switching information g generated in the predictive coding circuit. Based on the predicted decoded value switching signal h, the switch 13 selects either the predicted decoded value b or the predicted decoded value c, and outputs this as the predicted decoded value e. The predicted decoded value e is converted by the D / A converter 14 and output as the analog reproduction value f.

The switching controller 16 is controlled by the quantizer switching information g based on the buffer occupancy information j.
Table 1 shows the buffer occupancy and the selection result of the quantizer 23.
And a simple example of the resulting predictive decoded value is given. The occupancy is expressed by an index, and the higher the occupancy is, the larger the index is, and further, the quantization accuracy is coarse.
Note that the predicted decoded value b is "1" and the predicted decoded value b is "2" here.

[0023]

[Table 1]

4 (A)-(D) and 5 (A)-
(D) shows the temporal relationship with the video signal based on the relationship in Table 1. FIG. 4 shows the relationship between the video signal, the switching timing of the quantizer 23, and the predicted decoded value in units of field intervals. Further, FIG. 5 shows the same relationship in units of horizontal scanning lines. Here, the buffer occupancy is an example. In addition, here, the head value of the video signal in the field is used as the decoded value stored in the memory 12, but this means the head scanning line often used for initial value setting in the case of DPCM (Differential Pulse Code Modulation). , The best value is used for the quantization in this section.

As described above, in the decoding circuit of this embodiment, two predictive decoded values b and c are obtained as predictive decoded values of the horizontal synchronizing signal in the horizontal scanning line. Therefore, in the encoding circuit using the linear quantizer as the quantizer 23,
When the quantizer 23 having coarse quantization accuracy is selected,
As the predictive decoded value, the predictive decoded value c of the horizontal synchronizing signal included in the specific scanning line predetermined by the switch 13 is selected. By obtaining the analog reproduction value as the predicted decoded value e of the horizontal synchronizing signal on the scanning line, deterioration of the horizontal synchronizing signal due to bit truncation noise is eliminated, and visually streaking noise does not occur. Further, when the input signal level changes, the output signal level also follows and changes, so that an analog reproduction value with good reproducibility can be obtained.

The present invention is not limited to the above embodiment, and can be applied to the case where the type of the quantizer 23, the buffer occupancy expression, and the predictive code value switching control method are changed. is there.

[0027]

As described above, according to the decoding circuit of the present invention, when a quantizer having a coarse quantization precision is selected, the horizontal synchronizing signal on the scanning line is set to a predetermined specific value. Since the analog reproduction value can be obtained by switching to the decoded value of the horizontal synchronizing signal included in the scanning line, there is an advantage that the horizontal synchronizing signal is not deteriorated by the bit truncation noise and the streaking noise is not visually generated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a decoding circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an encoding circuit according to a conventional predictive encoding method.

FIG. 3 is a block diagram showing a configuration of a decoding circuit according to a conventional predictive coding method.

FIG. 4 is a diagram showing a relationship between a quantizer switching timing and a prediction decoded value in units of field intervals.

FIG. 5 is a diagram showing a relationship between a switching timing of a quantizer in units of horizontal scanning lines and a predicted decoded value.

[Explanation of symbols]

 11 Predictive Decoder 12 Memory 13 Switcher 14 D / A Converter 15 Scan Line Switcher 16 Switching Controller 17 Adder 18 Predictor a Prediction Error Signal b, c, e Predictive Decoded Value f Analog Reproduced Value g Quantizer Switching information h Predicted decoded value switching signal i Analog video input signal j Buffer memory occupancy information

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Shibuya, Toru Shibuya, 2nd Raijin, Yoshioka, Yamato-cho, Kurokawa-gun, Miyagi Miyagi NEC Corporation (72) Tadashi Ishii, 3-20-4 Nishishinbashi, Minato-ku, Tokyo No. Nippon Electric Engineering Co., Ltd.

Claims (2)

[Claims] 1. Decoding of a video signal using as input a prediction error signal output from a predictive coding circuit including a plurality of quantizers that are switched and controlled for each horizontal scanning line of the video signal and one or more predictors. A decoding circuit for performing encoding, having a predictor of the same configuration as the predictor of the predictive coding circuit, receiving a prediction error signal output from the predictive coding circuit, for each horizontal scanning line A predictive decoder that outputs the predictive decoded value of the existing horizontal synchronizing signal as a first predictive decoded value, and a predictive decoded value of the horizontal synchronous signal that exists in a predetermined specific horizontal scanning line as a second predictive decoded value And a predictive decoded value storage means for storing the second predictive decoded value for each horizontal scanning line from the predictive decoded value storage means, and quantizer switching information output from the predictive coding circuit. And the first predicted decoded value and the second A decoding circuit comprising: a decoded value selecting means for selecting any of the predicted decoded values; and a digital / analog converting means for converting the predicted decoded value selected by the decoded value selecting means into an analog signal. . 2. The decoding circuit according to claim 1, wherein the quantizer is a linear quantizer.