JPH05244439A - Picture processing unit - Google Patents

Abstract

PURPOSE:To quicken the compression efficiently by rearranging extracted picture data in an NXN block in the order in response to the arrangement of threshold levels of a quantization matrix and outputting the result and compressing the outputted picture. CONSTITUTION:Picture data D0 read in the order of the arrangement of threshold levels from picture memories 301, 302 are rearranged in latch circuits 310d-310a in the order of the threshold level and the rearranged data are subject to parallel serial conversion by a shift register 311 and the result is written in a memory 316. In this case, the moment data among the data D0 reaching a 0 level fastest synchronously with a clock pulse f0 from the shift register 311 is in existence, a clock gate 313 closes an AND gate 314 to stop the addressing of a line address counter 315. Thus, when the storage of 4 picture elements to the memory 316 is finished, the write of the data D0 to the memory 316 is again started. Thus, the picture data are compressed to 1/4 and data compression between 1/4-4/4 is obtained even from an intermediate tone picture.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus which quantizes input image data using an N.times.N block quantization matrix and compresses it in N.times.N block units.

[0002]

2. Description of the Related Art Conventionally, in a binary display type image processing apparatus such as a plasma panel, a liquid crystal display, a facsimile or a dot printer, which outputs an image using a display cell which can theoretically only display binary in black and white or light and dark. , Halftone (shading) such as photographs by digital image signals
In general, the dither method is often used for the reproduction of the above because of the gradation reproducibility and the easiness of the hardware configuration. Among them, in the systematic dither method, a predetermined threshold value is set for one pixel of an input image signal by a dither matrix as shown in FIG. 1 to determine whether the display cell is on or off. FIG. 2 illustrates an ON / OFF output pattern for a halftone input image performed using the 4 × 4 dither matrix of FIG. If the dots of the display output are displayed according to the output pattern of such a dither image,
Since it is possible to make the brightness of the input image proportional to the number of cells that are turned on, it is possible to reproduce the halftone of a photograph or the like in a pseudo manner.

On the other hand, in an image transmission device such as a facsimile, high efficiency coding (hereinafter referred to as data compression) is performed in order to speed up the transmission time. This data compression often uses run-length coding, which generally encodes a continuous length of white or black to reduce the number of transmission bits. In this case, if there are many continuous whites or continuous blacks, The greater the number, the higher the data compression rate. However, even in such a facsimile, reproduction of halftones is an essential element from the viewpoint of improving image quality. Therefore, in facsimiles and the like, run-length encoding of binary information that is generally processed using the dither method (hereinafter referred to as dither processing) is performed to improve data compression and to enable reproduction of a certain degree of halftone. ing. However, in terms of data compression, the dither method deteriorates the efficiency of data compression by run-length coding. This is because the appearance rate of "white continuation" or "black continuation", which is the basis of pattern run length encoding, is extremely reduced by the dither processing due to the nature of the dither matrix.

In addition, various data compression methods suitable for the dither method have been proposed. For example, an in-block pixel order in which a pixel of interest is predicted from the preceding four neighboring pixels and a threshold value in the dither matrix, and the prediction error is replaced with reference to the pixel of the previous scanning line and then run-length encoded. Swap method, bit interleaving method of performing run-length coding after grouping (sorting) corresponding to threshold values close to each other in the dither matrix, separating into 2-state patterns according to the threshold value of the dither matrix, or 4-state Screens obtained by processing by the state separation run length method, in which each pattern is separated into run patterns and then run length encoded separately, or the systematic dither method, is divided into n × m sub-matrixes, and the sub-matrix patterns are formed. Pattern matching method that assigns numbers and transmits the numbers, block prediction Patent Act, R
A / L direct switching method has been proposed.

[0005]

As described above, when image processing is performed using the dither method to compress image data, the data array peculiar to the dither matrix is focused on, or the data compression is performed. Various data compression methods such as compression by MR encoding and MH encoding have been proposed, but all of these conventional methods have a drawback that they are not very efficient in terms of data compression efficiency.

Further, it has not been considered that the image data to be raster-input is efficiently rearranged within a block of a predetermined size.

Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks, to quantize input image data using a quantization matrix of N × N blocks, and to compress the data in units of N × N blocks. An object of the present invention is to provide an image processing device capable of performing good compression at high speed with a simple circuit configuration.

[0008]

To achieve the above object, the present invention quantizes input image data by using a quantization matrix of N × N blocks and compresses the image data in units of N × N blocks. In the processing device, input means for inputting image data line by line, storage means for storing N lines of image data input by the input means, and N × N image data stored by the storage means.
Extraction means for extracting in block units, output means for rearranging and outputting the image data extracted by the extraction means in N × N blocks in an order corresponding to the threshold value arrangement of the quantization matrix, and the output means. And a compression unit that compresses the image data output by.

[0009]

In the present invention, the input image data is quantized by using the quantization matrix of N × N blocks, and the N × N blocks are quantized.
When compressing in units of N blocks, efficient compression is performed at high speed with a simple circuit configuration.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 3 shows an example of the structure of the high-efficiency encoding means of the image processing apparatus of the present invention for compressing the image data after dither processing, in which 301 and 302 are binary images processed by the dither method. An image memory having an N-bit capacity for storing data. In the image memory 301, the image data dithered by the threshold value of the first row of the 2 × 2 dither matrix as shown in FIG.
A, C, A, C, ... are stored in this order, and the image memory 302 stores the image data dithered by the threshold value of the second row of the dither matrix in the order of threshold values D, B, D, B. The threshold values A to D in FIG. 4 correspond to “3” to “0”, and A to D in the memories 301 and 302 indicate corresponding threshold values of image data.

Reference numerals 303 and 304 are address counters for addressing the corresponding image memory 301 or 302, and reference numerals 305 and 306 are the logical product of the basic clock pulse f ₀ and the gate pulse G ₁ or G ₂ and the clock pulse f ₁ or It is an AND gate that sends out f ₂ . The address counter 303 receives the image memory 30 in response to the clock pulse f ₁ given from the AND gate 305.
1 is supplied with an addressing signal ADR 301 for data reading, and the address counter 304 responds to a clock pulse f ₂ supplied from an AND gate 306 to the image memory 3
An addressing signal ADR 302 for reading data is supplied to 01. Reference numeral 307 is a gate pulse generation circuit that alternately outputs the gate pulses G ₁ and G _{2 according} to the basic clock pulse f ₀ , and 308 is a clock pulse generation circuit that generates the basic clock pulse f ₀ .

The gate pulse generating circuit 307 is composed of, for example, a pair of toggle flip-flops, and as shown in the signal waveform diagram of FIG. 5, gate pulses G ₁ and G having a pulse number of 1/4 of the pulse number of the input pulse f _0. Send ₂ . As a result, the clock pulses f ₁ and f ₂ are alternately generated every two times in synchronization with the basic clock pulse f ₀ (FIG. 5).
reference). On the other hand, each of the image memories 301 and 302 sequentially outputs the image data D ₀ after storing the image data that has been subjected to the dither processing up to N bits. At that time, the addressing signals ADR 301 and ADR 301 are generated according to the clock pulses f ₁ and f _2. Since the ADRs 302 are supplied alternately, binary (“0” or “1”) image data D ₀ is alternately sent from the image memories 301 and 302 for every two pixels.

Reference numeral 309 denotes a selection pulse generating circuit, which is the image data D output from the image memories 301 and 302.
₀ for D, C, B, A fixed threshold order (threshold size order)
The selection pulses t ₁ , t ₂ , t ₃ and t _{4 used} for switching to the output are switched and output according to the rising of the basic clock pulse f ₀ (see FIG. 5). This selection pulse generation circuit 3
Reference numeral 09 is, for example, a 1/4 ring counter including a 4-stage shift register. 310a to 310d are respectively D
Image data D ₀ read out from the image memories 301 and 302.
Are latched pixel by pixel according to the selection pulses t _{1 to} t ₄ .

At this time, the selection pulse t _{1 is changed} to the gate pulse G
_{Since the data} is supplied to the latch circuit 310a in synchronization with the rising edge of 1 (see FIG. 5), the image data D ₀ dithered with the threshold value A is first latched by the latch circuit 310a. Subsequent selection pulses t _{2 to} t ₄ are generated at equal intervals so as to be synchronized with the rising edges of the threshold values C, D, and B (see FIG. 5), and are sequentially supplied to the latch circuits 310c, 310d, and 310b. Threshold A from the image memories 301 and 302,
The image data D ₀ sequentially read out in the order of C, D and B are latch circuits 310a, 310c, 31.
It is latched in the order of 0d and 310b. Therefore, the image data D ₀ read out in the order of the thresholds A, C, D and B
The latch circuit by the selection pulse t ₁ ~t ₄ 310d~3
The threshold values D, C, B and A are rearranged in the order of 10a. Reference numeral 311 denotes a shift register that performs parallel-serial conversion, and D, C, B, stored in the latch circuits 310d to 310a.
The image data in the output order of A is parallel-serial converted.

Reference numeral 312 denotes a quarter of the basic clock pulse f ₀ .
A quarter circuit 313 for dividing the frequency into 2 is a clock gate composed of an RS flip-flop configured by directly connecting two NAND gates. The clock gate 313 is a quarter circuit 3
12 output pulse f ₃ (see FIG. 5) and shift register 3
A clock for closing the AND gate 314 is generated according to the binary data (image data) from 11. The AND gate 314 outputs the basic clock pulse f ₀ and the clock gate 3
A logical product with the output of 13 is taken and a clock pulse is generated. Reference numeral 315 is a write address counter, 316 is a memory for storing image data from the shift register 311, and the write address counter 315 is an AND gate 31.
Addressing of the memory 316 at the time of writing data is performed according to the clock pulse of 4.

In this way, the image memories 301 and 30
Image data D ₀ read out in the order of threshold values A, C, D and B from D to C in latch circuits 310d to 310a.
B and A are rearranged in a fixed threshold value order (size order), and this is parallel-serial converted by the shift register 311 to perform the memory 31.
6 is written in the shift register 311
From the image data D ₀ output in synchronization with the clock pulse f ₀ from D to C → B → A, the AND gate 314 is closed by the clock gate 313 at the moment when the first one is at the zero level. The addressing of the line address counter 315 is stopped. In this way, the memory 31
When the storage of 4 pixels in 6 is completed, the 1/4 circuit 312
Output clock gate 313 and reset by f ₃ (see FIG. 5), to start writing to the memory 316 of the image data D ₀ again.

Therefore, in the case of a completely white image, the image data D
_Since all _0s are “0”, only the first pixel of the 4 pixels, that is, only the pixel data processed by the threshold value D is written in the memory 316, so that the data compression can be performed to 1/4 of the conventional one. Similarly, in the case of a halftone image, 1/4 to 4 /
Data compression is obtained between four.

In this example, a circuit configuration example using a 2 × 2 dither matrix is shown in order to facilitate understanding of the description, but even if a 4 × 4 dither matrix is used, each circuit configuration is different. The same configuration can be achieved only by increasing the number of constituent elements, etc., and a completely white image can be compressed to 1/16. The same applies to other types of dither matrix.

FIG. 6 shows an example of the construction of the image data decoding means of the image processing apparatus of the present invention which restores the image data compressed by the apparatus of FIG. 3 to almost the original state.
Reference numeral 514 is substantially the same as the constituent elements 301 to 314 in FIG. 3, and 515 is a read address counter for performing read addressing of the memory 516 similar to the memory 316 in FIG. 3, and 517 is image data read from the memory 316. Gate signal GP of D ₀ and clock gate 513
₃ (see FIG. 7), and is the AND gate which supplies the result to the register 511. Further, in the memory 516, binary image data D ₀ subjected to data compression processing by the high-efficiency encoding means (data compression means) of FIG.
Is “1,1,1,1”, “1,1,1,” for every 4 pixels
It is assumed that the threshold values D, C, B, and A are stored in the order of 0, “1, 1, 0”, “1, 0”, and “0”.

At the time of data decoding, the image data D ₀ is read from the memory 516 in the order of the threshold values D, C, B and A by the addressing of the read address counter 515, and passes through the AND gate 517 gated by the gate signal GP ₃ to the register 511. To store. At this time, when the image data D ₀ has a signal of “0”, the clock gate 513
Gate signal GP ₃ of "0" becomes AND gate 51
4, the read address counter 51 is closed.
Through 5, the addressing of memory 516 ceases. On the other hand, the 1/4 circuit 512 changes the clock gate 513 to 4
Since it is reset for each pixel, the addressing of the memory 516 is 1 if there is a signal of “0” in the image data D _0.
At the same time, the output of the / 4 circuit 512 is stopped, and at the same time, the image data D ₀ of the remaining pixels in the subsequent 4 pixels become all “0” and exit from the AND gate 517. Since this operation is performed in units of 4 pixels by the output of the 1/4 circuit 512, the image data strings "1, 1, 1, 1" and "1, 1, 1, 0" which have not been subjected to data compression in 4 pixels. "Is not changed at all, but the compressed image data is restored with the value of" 0 ", and" 1,1,0 "becomes" 1,1,0,0 ".
“1,0” is “1,0,0,0”, “0” is “0,
It becomes 0, 0, 0 "and enters the register 511.

This will be described with reference to the signal waveform diagram (timing chart) of FIG. 7. The image signal D read from the memory 516 at the second clock of the basic clock pulse f _p of the first block divided in units of 4 pixels. _{If 0} becomes “0” for the first time, then the gate signal GP ₃ becomes low level, and the gates 514 and 51
The gate of No. 7 is closed to stop the addressing of the memory 516, and thereafter the output of the gate 517 continues to be "0",
Binary data “1” → “0” → “0” → “0” is shifted to the register 511 in the order of threshold values D → C → B → A, and 4
When a bit is entered, it is latched by the latch circuits 510d to 510a by the pulse generated from the 1/4 circuit 512.

Then, AND gates 518a to 518d.
And selection pulses t _{p1 to} t of the selection pulse generation circuit 509
_{By p4} (see FIG. 7), the operation opposite to the operation of the apparatus of FIG. 3 is performed and the image data D of the latch circuits 510d to 510a is obtained.
₀ is rearranged in the order of threshold values C → A → B → D, and the image memory 5
01 and 502 are stored in the order of C → A → B → D. At this time, the address counters 503 and 504 feed two pixels into the memories 501 and 502, respectively, and the same arrangement as that in the original main scanning (during dither processing) is set (see FIG. 3). 505 is an AND gate for outputting the clock f _p1 , 506 is an AND gate for outputting the clock f _p2 , 507 is a gate pulse generating circuit for generating the gate pulses GP ₁ and GP ₂ , and 508 is a basic clock pulse f _p . 3 is a clock pulse generating circuit for generating a clock pulse, and these circuits 505 to 508 are respectively circuits 305 of FIG.
The same operation as that of ˜308 is performed (see FIG. 7).

As described above, according to the present example, if the image data after dithering is replaced in the block of the dither matrix in a fixed threshold order and the bit of the image data becomes "0" according to the order of the threshold, Bits following this are also regarded as "0" for data compression, and "0" is added to the compressed data for decoding, so that it is relatively white background such as design drawings and text manuscripts. It has the effect of significantly compressing the data in a manuscript containing a lot of data.

The present embodiment is not limited to this, and can be applied to an original having many black backgrounds. For example, the sorting order of the image data is set to a threshold value order opposite to that of this example, and the bit of the image data is “1”.
In this case, if the following bits are also regarded as "1" and the data compression and decoding processing is performed, it is possible to perform a significant data compression on an original having a lot of black background such as a photographic original contrary to the present example. .. Furthermore, the data compression of this example is a lossy encoding method in which the subsequent bits are regarded as “0” and compressed, and therefore, when the original image data is decoded after being encoded, It may not be an exact match with However, considering the matrix unit, the frequency of non-coincidence is extremely low due to the characteristics of the dither matrix, and in the case of an image of almost uniform density in the unit of the matrix that has a high frequency of occurrence, it is completely original. Since it can be decrypted, there is no practical problem.

As described above, according to this embodiment,
The order of the image data after the binarization processing by the dither method or the like is replaced with a certain threshold value order within a block of a matrix such as a dither matrix,
If there is a signal of a predetermined value, it is considered that the data following it is also the same signal, and data compression means for compressing the data, and if there is a signal of the above-mentioned predetermined value in the image data compressed by the data compression means, Since the data decoding means for decoding the data assuming that the data following the data is also the same signal is provided, the image data can be significantly compressed.

The present invention is not limited to the dither method and can be applied to binary data processed by the density pattern method or the like.
That is, the dither matrix referred to in this example includes a matrix used in the density pattern method.

[0028]

As described above, according to the present invention, when the input image data is quantized by using the N × N block quantization matrix and compressed in the unit of N × N blocks, the efficiency is improved. Good compression can be performed at high speed with a simple circuit configuration.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an example of a 4 × 4 dither matrix.

FIG. 2 is an explanatory diagram showing an operation example of a display cell when dithering a halftone image using the dither matrix of FIG.

FIG. 3 is a circuit diagram showing a configuration example of a main part of an image processing apparatus of the present invention.

FIG. 4 is an explanatory diagram showing a dither matrix used in the apparatus of FIG.

5 is a timing chart showing an example of a signal waveform of each part of FIG.

6 is a circuit diagram showing a configuration example of a main part of an image processing apparatus of the present invention which decodes image data processed by the apparatus of FIG.

FIG. 7 is a timing chart showing an example of a signal waveform of each part of FIG.

[Explanation of symbols]

301, 302, 501, 502 Image memory 303, 304, 503, 504 Address counter 305, 306, 505, 506 AND gate 307, 507 Gate pulse generation circuit 308, 508 Clock pulse generation circuit 309, 509 Select pulse generation circuit, 310a -310d, 510a-510d Latch circuit 311, 511 Register 312, 512 1/4 circuit 313, 513 Clock gate 314, 514 AND gate 315 Write address counter 515 Read address counter 316, 516 Memory 517 AND gate f ₀ , f ₁ , f ₂ , f ₃ , f _p1 , f _p2 clocks G ₁ , G ₂ , GP ₁ , GP ₂ , GP ₃ gate signals t _{1 to} t ₄ , t _{p1 to} t _p4 timing signals D ₀ image data A, B, C , D threshold

Claims (1)

[Claims] 1. An image processing apparatus for quantizing input image data using a quantization matrix of N × N blocks and compressing the image data in N × N block units, and input means for inputting image data in line units. A storage unit for storing N lines of image data input by the input unit; an extraction unit for extracting the image data stored by the storage unit in N × N block units; and an image extracted by the extraction unit In the N × N block, there is provided output means for rearranging and outputting the data in an order according to the threshold value arrangement of the quantization matrix, and compression means for compressing the image data output by the output means. Image processing device.