JPH05244207A - Digital direct phase modulation method and circuit - Google Patents

Abstract

PURPOSE:To reduce the storage capacity of a memory storing a waveform pattern. CONSTITUTION:Waveform data of a modulation wave to be outputted are stored into plural number, e.g. two ROMs 23, 24 in advance separately, and the plural waveform data read from the said two ROMs 23, 24 are timewise synthesized by a synthesis circuit 27 via inversion control sections 25, 26 in response to transmission data for each modulation phase, the synthesized data are converted into analog data by a D/A converter section 28 to generate a modulation wave corresponding to the transmission data. Thus, not all of the transmission data of a modulation wave to be outputted are stored in one ROM but stored in the plural ROMs separately and the waveform data are generated by combining the waveform data of the modulation wave.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital direct phase modulation method and circuit for directly phase modulating digital data as transmission data.

[0002]

2. Description of the Related Art In the conventional digital direct phase modulation method, waveform data corresponding to the modulated wave itself is preliminarily stored in a ROM for all the modulated waves that can be taken according to the contents of transmission data.
The method is to read the waveform data of the modulated wave corresponding to the data to be actually transmitted from the ROM and perform D / A conversion to generate the modulated wave. The basic circuit configuration is shown in FIG. As shown.

In the figure, a digital direct phase modulation circuit includes a shift register 11 to which transmission data is input, and a ROM 12 to store all waveform data of modulated waves to be output.
And a D / A converter 13. The ROM 12 reads the waveform data of the corresponding modulated wave based on the actual transmission data held in the shift register 11, and the read waveform data is analogized by the D / A converter 13 and output as a modulated wave. It is supposed to be done.

[0004]

In the digital direct phase modulation circuit having the above-mentioned configuration, the waveform data of all the modulation waves that can be taken in accordance with the content of the transmission data are preliminarily R.
It has to be stored in the OM, which has the drawback of requiring a ROM with a very large storage capacity.

That is, as is well known, a modulated wave is a symbol value of modulation (here, one symbol is one unit of transmission data for modulation. For example, in the case of QPSK (quadrature phase shift keying), This is because even if one symbol is composed of 2 bits as described later), it has a correlation with the symbol values before and after that, and the waveform pattern differs depending on what the preceding and following symbol values are.

For example, in the case of QPSK which is a four-phase phase modulation, the QPSK modulated wave is modulated using 2-bit data corresponding to 0-π phase and π / 2-3π / 2 phase, and therefore 1
The symbol consists of 2 bits. Therefore, when the QPSK modulated wave is generated by the digital direct phase modulation circuit having the above configuration, even if the symbol value has a correlation only with the immediately preceding symbol, there are 64 types (=
2 ⁶ It is necessary to store the waveform pattern of) in the ROM 12, and in addition, since the correlation of a wider range is actually taken,
Much more waveform patterns need to be stored in ROM 12 than this.

The present invention has been made in view of the above circumstances, and an object thereof is a digital direct phase modulation method capable of reducing the storage capacity of a memory for storing a waveform pattern. And to provide a circuit.

[0008]

That is, according to the present invention, the baseband waveform data of the modulated wave to be output is divided and stored in advance in a plurality of ROMs, and the modulation data is transmitted in accordance with the transmission data for each modulation phase. A plurality of waveform data read from a plurality of ROMs are temporally combined and then D / A converted,
A modulation wave corresponding to the transmission data is generated, and instead of storing all the waveform data of the modulation wave to be output in one ROM, it is possible to store the modulation wave divided into a plurality of ROMs and stored. Since the waveform data is generated by combining the waveform data, it is possible to relatively reduce the storage capacity required for the ROM.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to QPSK which is four-phase modulation will be described below with reference to the drawings. The QPSK signal is in phase with 0 to π phase (hereinafter “I
2) corresponding to a π / 2-3π / 2 phase (hereinafter abbreviated as “Q phase”) which is a quadrature phase with the “phase”).

FIG. 1 shows the basic circuit configuration. The I-phase transmission data is sent to the shift register 21 and the Q-phase transmission data.
The phase transmission data is input and held in the shift register 22, respectively. The number of bits of each of these shift registers 21 and 22 is determined by the extent to which the correlation of the symbol value is taken into consideration before and after, and in the case of QPSK modulation, if the correlation is 1 bit before and after, a total of 3 bits are used. If 2 bits are used, a total of 5 bits are required.

Then, the I held in the shift register 21
The phase transmission data is read in the ROM 23, and the Q phase transmission data held by the shift register 22 is read in the ROM 24. R
The OM23 obtains all waveform pattern data for each symbol length (bandwidth limitation data of the waveform pattern) that can be taken by the band-limited I-phase baseband signal within the one-symbol length td time of the baseband signal ( The level value of td: a time interval corresponding to ½ cycle of the carrier) is stored as one set (one pattern). Then, from the plurality of sets of level value data of the I-phase baseband signal stored in the ROM 23, only one set corresponding to the transmission signal held in the shift register 21 is selectively read out and read out. One set of level value data is the inversion control unit 25.
Sent to.

Also, the ROM 24, like the ROM 23,
All waveform pattern data for each symbol length that the band-limited Q-phase baseband signal can take are stored as one set (one pattern) of the level value of the td time of the baseband signal obtained within one symbol length. This is the R
Of the plurality of sets of level value data of the Q-phase baseband signal stored in the OM 24, only one set corresponding to the transmission data held in the shift register 22 is selectively read out, and one set is read out. The level value data is sent to the inversion control unit 26.

The inversion controller 25 stores a set of level value data read from the ROM 23 and stores the stored td.
The synthesizing circuit by alternately inverting the level value for each time at a speed twice as high as the carrier clock CK (shown as "2CK" in the figure)
Output to 27.

The reversing control unit 26, like the reversing control unit 25, has the R
A set of level value data read from the OM 24 is stored, and the stored level value for each td time is alternately inverted at a speed twice as high as the carrier clock CK and output to the synthesis circuit 27.

The synthesizing circuit 27 alternately selects the outputs of the inversion control unit 25 and the inversion control unit 26 at a speed four times as high as the carrier clock CK (shown as "4CK" in the figure) and temporally synthesizes both outputs. It is composed of a switching circuit, and temporally combined continuous level value data is a D / A converter.
It is converted to analog at 28 and output as a modulation signal. Next, the operation of the above embodiment will be described with reference to FIG. 2 assuming that one cycle of the carrier is half the symbol length as described above.

Waveforms shown in FIGS. 2A and 2B are band-limited baseband signals corresponding to the I phase and the Q phase, respectively. The baseband signal is sampled at a sampling period td.
If the height of each pulse signal shown in FIGS. 2 (c) and 2 (d) sampled in FIG. 2 represents the level value of the baseband signal in FIGS. 2 (a) and 2 (b) at every td time, R
The level value data for each symbol length of the I-phase and Q-phase baseband signals stored in the OMs 23, 24 are within the intervals divided by each symbol length in FIGS. 2C and 2D, respectively. The four level value data represented by the four pulses of are set as one set.

2 (c) from the ROMs 23, 24 depending on the transmission data held in the shift registers 21, 22 for each modulation phase in which a new 1 bit of the transmission data is input to the shift registers 21, 22. , (D), the level value data of the baseband signal are collectively selected and read out for each group with four level value data within one symbol length as one group, and are sent to the inversion control units 25, 26. ..

In the inversion control units 25 and 26, the ROM 2
Figure 2 shows the level value data input from 3 and 24 for each group.
As shown in (e) and (f), the clock "2CK" alternately inverts at a speed twice as high as the carrier frequency, and outputs it to the synthesizing circuit 27.

In the synthesizing circuit 27, the outputs from the inversion control units 25 and 26 are alternately selected at a speed four times the carrier frequency by the clock "4CK", and both outputs are temporally synthesized. The outputs of the inversion control units 25 and 26 in (e) and (f) are selected during the period of the hatched portion, and the combined signal shown in FIG. 2 (g) is converted into an analog signal by the D / A converter 28. And is output as a QPSK modulated wave.

In the above embodiment, the ROM 23 and 24 store the level value data of the baseband signal at every td time, and the inversion control units 25 and 26 perform the post-processing to alternately invert the level value data. Alternatively, the ROM 23 and 24 may be preliminarily stored with the level value data subjected to the alternating inversion process. In this case, the inversion control units 25 and 26 are ROM
One set of level value data from 23, 24 is temporarily stored and
The level data of the set is td at a speed twice the carrier frequency.
It will be replaced with a buffer register that outputs every time.

Further, when the ROMs 23 and 24 can read one level value data in parallel at a speed four times as high as the carrier frequency every td / 2 hours, the inversion control units 25 and 26 and the buffer register are unnecessary. Needless to say.
Furthermore, the present invention is not limited to the exemplified QPSK modulation, but π /
The present invention can be applied to other phase modulation methods such as 4-shift QPSK modulation and 8-phase PSK modulation.

For example, in the case of π / 4 shift QPSK modulation, the carrier phase is rotated by π / 4 for each symbol, so that the inverted 0-π shown in FIGS. 3A and 3B is used. Of phase and π / 2-3π / 2 phase carriers, and π
As shown in FIG. 3A, the synthesizing circuit 27 synthesizes the waveform data of the carrier pairs of / 4-5π / 4 phase and 3π / 4-7π / 4 phase into a signal as shown in FIG. 3C. , (B) inverted waveform data (when the inversion control unit is replaced by a buffer register) or non-inverted waveform data are divided into two and stored in the ROMs 23 and 24. By alternately selecting the waveform data of the groups at a speed eight times the carrier frequency and temporally combining them, a π / 4 shift QPSK signal as shown in FIG. 3C can be generated.

In the case of 8-phase PSK modulation in which one symbol is composed of 3-bit data, a shift register,
Although it is possible to provide three sets of ROM and inversion control units and temporally combine the outputs of these sets with a combining circuit, one symbol value composed of 3-bit data is processed by data processing. By rearranging the transmission data of two systems, a modulated wave can be generated by the circuit shown in FIG.

[0024]

As described above, according to the present invention, the baseband waveform data of the modulated wave to be output is previously stored as a plurality of R's.
Corresponding to the transmission data by dividing and storing in the OM and synthesizing a plurality of waveform data read from the plurality of ROMs temporally according to the transmission data for each modulation phase and then performing D / A conversion. Since all the modulated wave waveform data to be output is not stored in one ROM, the modulated wave waveform data that are divided and stored in a plurality of ROMs are combined. A digital direct phase modulation method that can relatively reduce the storage capacity required for the ROM to generate waveform data and can reduce the storage capacity of the memory for storing the waveform pattern. And a circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of FIG.

FIG. 3 is a diagram showing an application example of another phase modulation method of the present invention.

FIG. 4 is a block diagram showing a basic configuration of a conventional digital direct phase modulation circuit.

[Explanation of symbols]

11, 21, 22 ... Shift register, 12, 23, 24 ... ROM, 1
3, 28 ... D / A converter, 25, 26 ... Inversion control section, 27 ... Combining circuit.

Claims (3)

[Claims] 1. The waveform data of a modulated wave to be output is divided and stored in advance in a plurality of ROMs, and the plurality of waveform data read from the plurality of ROMs according to the transmission data for each modulation phase is timed. The digital direct phase modulation method is characterized in that the modulated waves corresponding to the transmission data are generated by performing D / A conversion after being combined dynamically. 2. A plurality of registers for respectively storing transmission data of a plurality of systems, and one-to-one correspondence with the plurality of registers for storing band limiting signals of all waveform patterns corresponding to the transmission data of the corresponding systems. A plurality of Rs for selectively outputting the band-limited signal based on the transmission data stored in the corresponding register.
OM, a synthesizing unit for sequentially selecting the band-limited signal data output from the plurality of ROMs and temporally synthesizing all outputs, and the band-limited signal data synthesized by the synthesizing unit is D / A.
A digital direct phase modulation circuit comprising: a D / A conversion means for converting to create a modulated signal. 3. A plurality of registers for respectively storing transmission data of a plurality of systems, and one-to-one correspondence with the plurality of registers for storing band limiting signals of all waveform patterns corresponding to the transmission data of the corresponding systems. A plurality of Rs for selectively outputting the band-limited signal based on the transmission data stored in the corresponding register.
OM and the RO corresponding to the ROMs in a one-to-one correspondence
A plurality of inversion control means for sequentially inverting and outputting the band-limited signal data output from M at appropriate intervals, and the band-limited signal data output from the plurality of inversion controlling means are sequentially selected to temporally output all outputs. And the band-limited signal data synthesized by this synthesizing means.
A digital direct phase modulation circuit comprising: a D / A conversion means for converting to create a modulated signal.