JPH05243966A - Logic circuit - Google Patents

Abstract

PURPOSE:To operate an emitter-follower circuit at high speed even at the time of heavy load and to operate it with low power consumption in a logical circuit having the emitter-follower circuit. CONSTITUTION:A block A is the logic circuit having the emitter-follower circuit. A block B is an active pull-down circuit including the emitter-follower circuit which quickly discharges the charge of load when the potential levels of output terminals 3 and 4 are about to change from high potential to low potential. The active pull-down circuit consists of transistors 20 and 21 to make constant emitter-follower current flow to transistors 11 and 12 composing the emitter follower circuit, and transistors 24, 25, 28, etc., composing a bias circuit controlling emitter-follower current made to flow the transistors 20 and 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit which realizes high speed and low power consumption.

[0002]

2. Description of the Related Art As a conventional logic circuit, there is a logic circuit as shown in the circuit diagram of FIG. The logic circuit shown in FIG.
The input terminal 10, the reference voltage terminal 1, the current source voltage terminal 2, the output terminals 3 and 4 which are mutually complementary output terminals, the transistors 5 and 6 and the resistors 7 and 8 which form the current switch circuit, and the constant current circuit. A transistor 9 and a resistor 34 which constitute the transistor, transistors 11 and 12 and resistors 15 and 16 which constitute an emitter follower circuit, a VEE power source 13 of a constant current circuit, a VT power source 14 of an emitter follower circuit.
It is composed of

Next, the operation of the conventional logic circuit configured as described above will be described. FIG. 7 is a waveform diagram showing voltage waveforms at the input and output terminals in the logic circuit shown in FIG. As shown in the section (b) in the voltage waveform (1) of the input terminal shown in FIG. 7, when a signal having a higher potential than the reference voltage terminal 1 is input to the input terminal 10, the transistor 5 in the current switch circuit is turned on. Then, the transistor 6 is turned off. At this time, a constant current Ics, which is determined by the voltage of the current source voltage terminal 2 and the VEE power supply 13 and the resistance value of the resistor 34, always flows through the constant current circuit regardless of the potential level of the input terminal 10. This current Ics flows through the side that is turned on among the transistors 5 and 6 that form the current switch circuit. Therefore, in the case of the above-mentioned input condition, the current Ics is supplied to the transistor 5 through the resistor 7. It will flow. As a result, a voltage drop occurs in the resistor 7, and the collector potential of the transistor 5 changes from a high potential to a low potential. The potential of the output terminal 4 changes from the high potential to the low potential similarly to the collector potential of the transistor 5, because the collector potential of the transistor 5 is level-shifted by the transistor 12. Therefore, at the output terminal 4, a logic level having a polarity opposite to that of the logic level at the input terminal 10 and having a low potential is obtained.

On the other hand, at this time, no current flows through the transistor 6 on the opposite side of the transistor 5 in the current switch circuit, and the collector potential becomes high. Therefore, the output connected to the emitter of the transistor 11 forming the emitter follower circuit. A logic level having the same polarity as that of the input terminal 10 is output to the terminal 3.

As shown in the section (a) in the voltage waveform (1) of the input terminal shown in FIG. 7, when a signal having a lower potential than the reference voltage terminal 1 is input to the input terminal 10, that is, the section (b) described above. ), The ON / OFF state of the transistors 5 and 6 in the current switch circuit is opposite to that in the section (b), and the output terminal 4 To a high potential, and the output terminal 3 outputs a low potential logic level.

In the above operation, when the load connected to the output terminal 3 or the output terminal 4 is light, as shown in the light load (a) in the voltage waveform (2) of the output terminal shown in FIG. The change in the potential level of the output terminals 3 and 4 follows the change in the potential of the input terminal 10 and changes at high speed. this is,
Load capacity and resistance in emitter follower circuit 1
Since the time constant determined by 5 and 16 is small, charging and discharging with respect to the load is performed at high speed.

However, when the load connected to the output terminal 3 or the output terminal 4 becomes heavy, the time constant of charging / discharging with respect to the load becomes large, and when the load waveform (2) shown in FIG. As shown in b), the change in the potential level of the output terminals 3 and 4 becomes slow. Output terminals 3, 4
When the potential level of 1 changes from a low potential to a high potential, the load is charged by the transistors 11 and 12 that form the emitter follower circuit having a high driving capability, so that the delay is small even at a high load. On the other hand, when the potential level of the output terminals 3 and 4 changes from a high potential to a low potential, the discharge from the load is delayed due to the time constant determined by the capacitance of the load and the resistors 15 and 16 forming the emitter follower circuit. Since the degree is determined, the higher the load, the greater the degree of delay.

Therefore, in order to increase the speed of the conventional logic circuit, it is necessary to shorten the time required for the output level to change from the high potential to the low potential. To this end, the resistors 15 and 1 that form the emitter follower circuit
Although the resistance value of 6 may be reduced, the current flowing through the emitter follower circuit is increased accordingly and the power consumption is increased.

[0009]

However, in the above-described conventional logic circuit, a large power consumption is required in the emitter follower circuit in order to increase the speed under a heavy load. In general, the conventional logic circuit has
The emitter follower circuit occupies 50 to 70% of the total power consumption per gate, which poses a problem that it is a major obstacle in promoting high speed and high integration of the circuit.

The present invention has been made in view of the above problems, and in a logic circuit having an emitter follower circuit, the emitter follower circuit can operate at high speed even when the load is high, and the power consumption is low. It is an object of the present invention to provide a logic circuit that can be operated in.

[0011]

SUMMARY OF THE INVENTION A logic circuit according to the present invention includes a logic circuit for outputting mutually complementary first logic signals and second logic signals whose potentials change in response to changes in input signals. An emitter follower circuit that outputs a load drive signal that drives a load based on the first and second logic signals, and rapidly discharges the charge of the load when the load drive signal changes from a high potential to a low potential. When the load drive signal changes from a low potential to a high potential, the load is rapidly charged through the emitter follower circuit, and when the load drive signal is in a stable state, the first and second logic signals And an active pull-down circuit for controlling so that an emitter follower current higher than that of a low potential is flown therein.

[0012]

In the logic circuit according to the present invention, the active pull-down circuit is provided in the logic circuit having the emitter follower circuit which outputs the first and second logic signals complementary to each other and drives the load based on these logic signals. The circuit discharges the load charge rapidly when the load drive signal changes from high potential to low potential, and rapidly charges the load through the emitter follower circuit when the load drive signal changes from low potential to high potential. Then, when the load drive signal is in a stable state, control is performed so that a larger emitter follower current having a lower potential flows through the logic signal having a higher potential among the first and second logic signals. As a result, the logic circuit according to the present invention rapidly withdraws charges from the load when the output logic level changes from the high potential to the low potential, and loads the load when the output logic level changes from the low potential to the high potential. Since the charge is rapidly supplied to, it is possible to drive a high-speed load,
Further, when the logic signal of the logic circuit is in the stable state of high potential, the emitter follower current is increased, and when the logic signal of the logic circuit is in the stable state of low potential, the emitter follower current is reduced, so that low power consumption is maintained. Can operate at high speed.

[0013]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a logic circuit according to the first embodiment of the present invention. Note that, in FIG. 1, the same components as those of the conventional logic circuit shown in FIG. In FIG. 1, a block A is a logic circuit configured the same as the conventional logic circuit shown in FIG. In the logic circuit according to the first embodiment shown in FIG. 1, a different constituent part from the conventional logic circuit shown in FIG. 6 is a part forming a block B.

The block B includes the function of the emitter follower circuit. Further, the block B is an active pull-down circuit including an emitter follower circuit for rapidly discharging the electric charge of the load when the potential level of the output terminals 3 and 4 is going to change from the high potential to the low potential. This active pull-down circuit transmits transistors 20 and 21 for supplying a constant emitter follower current to the transistors 11 and 12 which form the emitter follower circuit, and the change in the output logic level in the block A to the bases of the transistors 20 and 21. Capacitors 22 and 23 for
Transistors 24 and 2 forming a bias circuit for controlling the emitter follower current flowing in the transistors 20 and 21.
5, 28, resistors 26, 27, 29, bias voltage terminal 3
0, current source voltage terminal 31 and VEE power supply terminal 32
And the VT power supply terminal 33 of the emitter follower circuit.

Next, the operation of the logic circuit according to the first embodiment constructed as described above will be described. FIG. 2 is a waveform diagram showing voltage and current waveforms at various parts in the logic circuit according to the first embodiment shown in FIG.

In the logic circuit shown in FIG. 1, similarly to the operation of the conventional logic circuit shown in FIG. 6, the output terminal 3 outputs a signal having the same polarity with respect to the logic level input to the input terminal 10, and outputs it. A signal of opposite polarity is output from the terminal 4. For example, when a signal having a lower potential than the reference voltage terminal 1 is input to the input terminal 10 as shown in the section (a) in the voltage waveform (1) of the input terminal shown in FIG. A high-potential signal is output from the output terminal 4. On the other hand, the bias circuit in the block B has the same circuit configuration as that of the current switching type logic circuit as in the block A, and one of the current switch transistors 24 and 25 forming the bias circuit is turned on. , The other is off. Transistor 2
Since the potentials of the output terminals 3 and 4 are directly applied to the bases of the transistors 4 and 25, the transistor 24 is turned off and the transistor 25 is turned off under the input condition shown in the section (a).
Turns on. Therefore, the current flows from the bias voltage terminal 30 to the resistor 26, and the voltage drop (Δ
V) occurs. The current IB flowing at this time is determined by the circuit constants of the constant current circuit formed by the transistor 28 and the resistor 29 and the voltage values of the current source voltage terminal 31 and the VEE power supply 32. As a result, the collector potential of the transistor 25 is ΔV higher than the potential of the bias voltage terminal 30.
Therefore, the potential level becomes low, and this potential level is applied to the base of the transistor 20.

On the other hand, at this time, since the transistor 24 is off, the voltage drop due to the resistor 27 does not occur. Therefore, the collector potential of the transistor 24 becomes the same level as the potential of the bias voltage terminal 30, and this potential is applied to the base of the transistor 21.

Therefore, the input condition is the section (a) shown in FIG.
In this case, a low potential is applied to the base of the transistor 20 and a high potential is applied to the base of the transistor 21. As a result, as shown in the emitter current waveform (3) of the transistors 20 and 21 in FIG.
There is a difference in the current value flowing between 0 and the transistor 21.
That is, a small current flows through the transistor (transistor 20 in the case of section a in FIG. 2) connected to the low potential level output terminal, and the transistor connected to the high potential level output terminal (see FIG. In the case of the section a of 2, a large current flows through the transistor 21).

Next, the input terminal 10 as shown in the section (b) in the voltage waveform (1) of the input terminal shown in FIG.
The operation when the potential of is changed from the low potential to the high potential will be described.

As the potential of the input terminal 10 changes, the collector potential of the transistor 6 in the block A changes from low potential to high potential. This potential change causes the capacitor 23
2 is transmitted to the base of the transistor 21 via the base voltage waveform of the transistors 20 and 21 in FIG.
As shown in, the base potentials of the transistors 20 and 21 momentarily increase. As a result, a transiently large emitter current flows in the transistor 21 as shown in the emitter current waveform (3) of the transistors 20 and 21 in FIG.
This current is supplied from the load connected to the output terminal 4. That is, the charge of the load is rapidly discharged through the transistor 21, and the potential of the output terminal 4 rapidly changes from the high potential to the low potential as shown in the voltage waveform (4) of the output terminal in FIG. ..

On the other hand, at this time, the collector potential of the transistor 5 changes from a high potential to a low potential as shown in (2) and (3) of FIG. 2, and this potential is transmitted through the capacitor 22. 20 is momentarily turned off. Therefore, all the emitter follower current flowing through the transistor 11 flows into the load, and the load is charged rapidly. Therefore, the change from the low potential to the high potential at the output terminal 3 is rapidly executed as shown by (4) in FIG.

Next, the operation in the section (c) in FIG. 2, that is, the operation when the voltage and current of each part in the logic circuit shown in FIG. 1 shift from the transient state to the stable state will be described. As indicated by (2) in FIG. 2, the base potential of the transistor 21 reaches a peak value by a transient operation via the capacitor 23 and then starts to change toward a low potential level. At the same time, the transistor 24
The base potential of the transistor 25, that is, the potential of the output terminal 3 changes in the high potential direction, and the base potential of the transistor 25, that is, the potential of the output terminal 4 changes in the low potential direction.
The reverse operation of the on / off state at 4, 25 is further accelerated. As a result, the transistor 24 is switched to the on state and the transistor 25 is switched to the off state, and the base potential of the transistor 21 connected to the collector of the transistor 24 is higher than that of the bias voltage terminal 30 by the resistance 27.
It changes toward the lower level by the amount of voltage drop at.

On the other hand, the base potential of the transistor 20 is
Contrary to the operation of the transistor 21 described above, the potential changes from the low potential to the high potential, and finally reaches the potential of the bias voltage terminal 30.

As the base potentials of the transistors 20 and 21 change as described above, the transistors 20 and 21
The emitter current, that is, the emitter follower current, changes as shown by (3) in FIG. Finally, the emitter follower currents of the transistors 20 and 21 are the same as those shown in FIG.
The current values shown by the waveforms mutually inverted with respect to the waveform shown in the section (a) in FIG.

By the above operation, the charge of the load connected to the output terminal 4 is rapidly extracted by the transistor 21, and the potential of the output terminal 4 changes from high potential to low potential at high speed. On the other hand, the load connected to the output terminal 3 is rapidly supplied with electric charges from the transistor 11 and the transistor 20 is temporarily turned off, so that the potential of the output terminal 3 is rapidly changed from a low potential to a high potential. It changes to the electric potential.

FIG. 3 is a circuit diagram showing a logic circuit according to the second embodiment of the present invention. In the logic circuit according to the second embodiment, the components different from those of the logic circuit according to the first embodiment shown in FIG. 1 are connected to the bases of the transistors 24 and 25 forming the bias circuit, respectively. It is the part which is the collector of 6 and 5. The operation of the logic circuit according to the second embodiment is the same as the operation of the logic circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing a logic circuit according to the third embodiment of the present invention. In the logic circuit according to the third embodiment, the components different from those of the logic circuit according to the first embodiment shown in FIG. 1 are such that the capacitors 22 and 23 are connected to the collectors of the transistors 21 and 20, respectively. It is the part that is. The operation of the logic circuit according to the third embodiment is the same as the operation of the logic circuit according to the first embodiment.

FIG. 5 is a circuit diagram showing a logic circuit according to the fourth embodiment of the present invention. Expressed in negative logic, the logic circuit according to the first embodiment is a logic circuit having both AND / NAND outputs, whereas the logic circuit according to the fourth embodiment has only one side output of AND. It is a logic circuit. In the logic circuit according to the fourth embodiment, the constituent parts different from those of the logic circuit according to the first embodiment are the transistors 12 and 21 and the capacitor 2 for producing a NAND output.
There is no 3 and the base input of the transistor 25 is output terminal 3
Is a portion connected to the reference voltage terminal 1 having an intermediate potential between the high potential and the low potential. The operation of the logic circuit according to the fourth embodiment is the same as the operation of the logic circuit according to the first embodiment. Further, in the logic circuit according to the fourth embodiment,
Although the base input of the transistor 24 is connected to the collector of the transistor 20, it is apparent that the same circuit operation is performed even if the connection position is changed to the collector of the transistor 6 as in the second embodiment.

[0030]

As described above, according to the logic circuit of the present invention, when the output logic level of the logic circuit is in the stable state of high potential, the emitter follower current is large and the output logic level of the logic circuit is low potential. In the stable state of, the emitter follower current is reduced. Due to these, the logic circuit according to the present invention rapidly withdraws electric charges from the load when the output logic level changes from the high potential to the low potential according to the potential change of the input terminal of the logic circuit, and the output logic level becomes low. When the potential changes from the high potential to the high potential, the charges are rapidly supplied to the load, so that a logic circuit that can operate at high speed while maintaining low power consumption can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a logic circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing voltage and current waveforms at various parts in the logic circuit according to the first embodiment of the present invention shown in FIG.

FIG. 3 is a circuit diagram showing a logic circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a logic circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a logic circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a conventional logic circuit.

7 is a waveform diagram showing voltage waveforms at input and output terminals in the logic circuit shown in FIG.

[Explanation of symbols]

1; Reference voltage terminal 2; Current source voltage terminal 3, 4; Output terminal 5, 6, 9, 11, 12, 20, 21, 21, 24, 25, 2
8; Transistor 7, 8, 10, 26, 27, 29, 34; Resistor 10; Input terminal 22, 23; Capacitor 30; Bias voltage terminal 31; Current source voltage terminal 31

Claims (1)

[Claims] 1. A logic circuit for outputting a complementary first logic signal and second logic signal whose potential changes in response to a change of an input signal, and a logic circuit based on the first and second logic signals. An emitter follower circuit that outputs a load drive signal that drives a load, and when the load drive signal changes from a high potential to a low potential, the load is rapidly discharged to change the load drive signal from a low potential to a high potential. When changing, the load is rapidly charged through the emitter follower circuit, and when the load drive signal is in a stable state, the first and second
An active pull-down circuit which controls so that an emitter follower current larger than that of the low potential among the logic signals of 1 is supplied to the high potential.