JPH05243922A - Pseudo random number generator and photoelectric switch using the same - Google Patents

Abstract

PURPOSE:To improve the randomization of a pseudo generated random number. CONSTITUTION:A pulse A whose period is unstable is outputted from a pulse generation circuit 1, and for every its period, a counter 2 counts a clock CK from a clock generator circuit 3 for every period corresponding to the length of its period. On the other hand, a pseudo random number generator circuit 5 is constituted so that a series constituted by arraying pseudo random numbers in it can be generated in plural numbers, and the series instructing data corresponding to these series is stored in a series selection circuit 4. The series instructing data SD corresponding to the count value N of every period of the pulse A from the counter 2 is outputted from the series selection circuit 4, and the pseudo random number generator circuit 5 outputs the pseudo random number H of the series corresponding to the series instructing data SD.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo random number generator using a digital circuit and a photoelectric switch using the pseudo random number generator as a clock generating means.

[0002]

2. Description of the Related Art A photoelectric switch is known as a means for detecting the presence or absence of an object moving on a conveyor line or the like. This is to determine the presence / absence of an object by projecting light on the path of the object and detecting the presence / absence of reflected light from the moving object. In such a photoelectric switch, in order to eliminate the influence of ambient light, reduce power consumption, prevent mutual interference, etc., the projection light is pulsed and projected intermittently (hereinafter, this projection light is Sensing light). Usually, a plurality of photoelectric switches are used to detect the presence or absence of an object. For example, in a conveyor line, a photoelectric switch that projects light from the lateral direction, a photoelectric switch that projects light from below, a photoelectric switch that projects from above, etc. 1
Multiple photoelectric switches are installed at each location to enable more accurate object detection. However, when a plurality of photoelectric switches are installed at one location and each photoelectric switch continuously projects light, each photoelectric switch may receive the sensing light projected by the other photoelectric switches. This is called mutual interference as described above.In a photoelectric switch, light is emitted intermittently so that the light emission timing does not overlap with other photoelectric switches, and the reflected light from its own light emission and the light emission of other photoelectric switches cause A method has been taken to allow the received light (interference light) to be distinguished.

As one of the methods, there is known a method of using a pseudo random number generator as a clock generating means for driving the light emitting element to emit light. FIG. 7 is a block diagram showing an example of a conventional pseudo-random number generator, in which 100 is a voltage source and 1 is a voltage source.
Reference numeral 02 is a resistor, 103 is a Zener diode, 104 is a capacitor, 105 is an amplifier, and 106 is an A / D converter. This conventional example takes advantage of the fact that the Zener diode is apt to generate noise when used in a current region smaller than a normal operating current.

In FIG. 1, a voltage source 100 is connected to a resistor 10
A voltage is applied to the Zener diode 103 via 2 and the Zener diode 1 is determined by the applied voltage.
Due to the noise characteristic of 03, white noise whose amplitude changes randomly is generated from the Zener diode 103. This white noise passes through the capacitor 104, is amplified by the amplifier 105, and is then supplied to the A / D converter 106, where a pseudo random number of a digital value is generated.

When such a pseudo-random number generator is used as a clock generating means of a photoelectric switch, the obtained pseudo-random number is converted into an analog value, and a sawtooth-shaped pulse generated from a clock having a constant period is used as an analog value and a comparator. By comparing the levels with, a clock whose position changes randomly according to the analog value with respect to the original clock of the above-mentioned fixed period is obtained, and by using this pulse as the light emission drive pulse of the generating element, The timing can be random. Therefore, even if a plurality of photoelectric switches equipped with such a pseudo-random number generator are installed at the same place and used, the probability of mutual interference is extremely small.

However, although such a pseudo-random number generator has a very simple circuit configuration, it has a problem in terms of influence due to variations in the characteristics of the element itself, noise resistance, and power supply voltage sensitivity, and the obtained pseudo-random number generator has a problem. The random number value may become abnormal, or the same pseudo-random number value may be repeatedly obtained depending on the amplification degree of the amplifier 105 and the operating range of the A / D converter 106. Further, practically, it is necessary to use at least 7 (V) or more as a working voltage, which is sufficiently higher than the standard voltage of 5 (V) used in a digital circuit, and another voltage source is required, which is low. There is also a problem in that it is difficult to use for voltage-powered devices.

FIG. 8 is a block diagram showing another example of a conventional pseudo random number generator, and 201 to 203 are ExOR.
(Exclusive OR) gate, 204 to 208 are D-FF
(D-type flop-rop circuit).

This conventional example is constituted by a digital circuit, and in FIG. 8, for example, five D-
The FFs 204 to 208 are connected in cascade, and between these cascade paths, here, the input side of the D-FF 204, D-FF2.
E between 04 and 205 and between D-FF207 and 208, respectively.
xOR gates 201, 202, 203 are provided, and D at the end
-The Q output of FF208 is changed to D-FF204,205,
I am going to return to 208. ExOR gate 20
A pulse of "1" having a constant cycle is input to 1 in synchronization with the clock φ ₀ , and each of the D-FFs 204 to 208 samples and holds the input data D in synchronization with the clock φ ₀ . Then, the input data D of each D-FF 204 to 208
Are the bits that make up the pseudo-random number. Therefore, a pseudo random number of 5 bits can be obtained from such a pseudo random number generator.

Since the pseudo random number generator basically has the same structure as the CRC coding circuit in which the generator polynomial is set, and is composed of a digital circuit,
The problem of the conventional example shown in FIG. 7 can be solved, and a digital circuit part is included in a part of a signal processing circuit of a device using this, and a custom or semi-custom I
When C is used, the addition of the predetermined function of this IC has the advantage that no external additional components are required.

However, in such a pseudo-random number generator, the pseudo-random number is generated completely in accordance with the sequence determined by the circuit configuration, and this sequence has a finite length and is periodic. Therefore, when a plurality of photoelectric switches equipped with such pseudo-random number generators having the same configuration are used at the same place, this sequence is used unless the frequency of the clock ψ ₀ shown in FIG. There is a case where the phase of the cycle becomes gradually closer to each other, and the pseudo-random number values in the above series are coincident with each other. In such a situation, a state in which the pseudo random number values are almost the same continues for a while, and mutual interference occurs during this period.

FIG. 9 is a block diagram showing a conventional example of a pseudo-random number generator capable of solving such a problem.
301 is an external power supply terminal, 302 is a battery, 303, 3
04 is a diode, 305 is a pseudo random number generation circuit, 306
Is a processing circuit.

In the figure, the external power supply terminal 301 is normally used.
The external power supply voltage is applied to the processing circuit 306 and the like, and is also applied to the pseudo random number generation circuit 305 via the diode 304. The pseudo random number generation circuit 305 has a circuit configuration as shown in FIG. 8, for example, and generates a pseudo random number. Moreover, the cycle of the random number sequence is made longer than at least the average life of the product. This pseudo random number is used by the processing circuit 306.

When the external power supply is turned off and the apparatus is put into a non-use state, the voltage of the battery 302 passes through the capacitor 303,
It is applied to the pseudo random number generation circuit 305 as a power supply voltage.
Therefore, even if the external power supply is turned off, the pseudo random number generation circuit 305
Continues to generate pseudo-random numbers. At this time,
The voltage of the battery 302 is not applied to the processing circuit 306 and the like by the capacitor 304, and the pseudo random number generation circuit 305
Only applied to. The capacitor 303 is for preventing the battery 302 from being charged when an external voltage is applied.

According to such a pseudo random number generator, since the pseudo random number generating circuit 305 continues to operate with the voltage from the battery 302 while the external power source is off, the pseudo random number generating circuit 305 turns on / off the external power source. However, the pseudo-random number is always generated, and thus the initialization is not performed. Therefore, unless the Cook frequencies of the pseudo random number generators match, the phase of the cycle of the sequence of pseudo random numbers generated by these pseudo random number generators has a sufficiently long cycle.
Since it is not repeated, it becomes distant, and thus the generated pseudo random number values do not become the same among a plurality of pseudo random number generating devices, and mutual interference between photoelectric switches can be prevented.

[0015]

However, in the pseudo-random number generator shown in FIG. 9, the pseudo-random number generator circuit 305 is provided even if mutual interference between photoelectric switches using the pseudo-random number generator can be prevented as described above. A battery for backup is required, which makes it difficult to realize downsizing and cost reduction for devices such as a pseudo-random number generator and a photoelectric switch using the same.

An object of the present invention is to provide a small-sized and low-priced pseudo-random number generator that solves the above problem and further enhances the randomness of the generated pseudo-random number value.

Another object of the present invention is to provide a small-sized and low-priced photoelectric switch that further enhances the randomness of light projection timing to prevent mutual interference.

[0018]

In order to achieve the above object, a pseudo-random number generator according to the present invention comprises a pulse generating means for generating a pulse having an unstable cycle, and a pulse generating means for each cycle of the pulse according to the cycle. And counting means for counting the period clock, sequence indicating means for outputting pseudo random number sequence instruction data according to the count value, and pseudo random number generating means for generating pseudo random numbers in the sequence according to the instruction data.

In the photoelectric switch according to the present invention, a means for converting the value of the pseudo random number generated by the pseudo random number generating means according to the present invention into an analog value and a pulse level are compared with the analog value, and at least the front edge is detected. A means for generating a pulse whose phase with respect to the pulse changes according to the analog value, and a means for generating a drive pulse for fixing the time width of the output pulse of the means and determining the light projection timing are provided.

[0020]

In the pseudo-random number generator according to the present invention, one column of pseudo-random numbers is combined into one series, but the pseudo-random number generating means can generate different series (the pseudo-random numbers are arranged differently). There is. The sequence instruction means selects one of these sequences according to this cycle for each cycle of the pulse from the pulse generating means, but since the pulse cycle is randomly different, the selection order of the selected series is completely different. It will be random. Therefore, the arrangement order of the generated pseudo random numbers has no periodicity.

Further, in the photoelectric switch according to the present invention, the timing of the drive pulse of the light projecting portion changes according to the value of the pseudo random number from the pseudo random number generator,
Therefore, the light projecting timing of the light projecting section has no periodicity and is completely random.

[0022]

Embodiments of the present invention and drawings will be described below. FIG. 1 is a block diagram showing an embodiment of a pseudo-random number generator according to the present invention, in which 1 is a pulse generator circuit, 2 is a counter, 3 is a clock generator circuit, 4 is a sequence selection circuit, and 5 is a series selection circuit.
Is a pseudo random number generation circuit.

In the figure, the pulse generation circuit 1 is provided with an oscillator that causes fluctuations in the oscillation frequency of a CR oscillator, an LC oscillator, etc. due to 1 / f noise, temperature changes, etc., and for each cycle of the output pulse of such oscillator, A pulse A having a time width corresponding to this cycle is output. The time width of this pulse A is constantly changing because the oscillation frequency of this oscillator fluctuates constantly. Here, the time width of the pulse A is set to be sufficiently longer than the cycle of the clock CK generated by the clock generation circuit 3, for example, about 10 million times. The counter 2 counts the clock CK from the pulse generation clock generation circuit 3 each time the pulse A is supplied from the pulse generation circuit 1, and selects the count value N in the pulse period at the end of the pulse period. Send to circuit 4.

On the other hand, the pseudo random number generating circuit 5 is constructed so as to be able to generate a plurality of sequences in which pseudo random numbers are arranged in different orders, and the sequence selecting circuit 4 has each of the pseudo random number generating circuits 5 in the sequence selecting circuit 4. The sequence designation data for corresponding to the sequence one-to-one and for instructing the corresponding sequence is stored. Further, these series instruction data correspond to the count value N from the counter 2.

Therefore, when the count value N is output from the counter 2, the sequence instruction data SD corresponding to this is selected and output from the sequence selection circuit 4, and the pseudo random number generation circuit 5 instructs with this sequence instruction data SD. Is set to the occurrence state of the series. Then, the pseudo random number of the instructed sequence is used as the clock CK output from the clock generation circuit 3.
The pseudo random number generation circuit 5 outputs the data one by one.

Here, the output pulse A of the pulse generation circuit 1
When the pulse width of the clock CK is sufficiently long as described above with respect to the cycle of the clock CK, if all the clocks CK within this pulse width are counted, a count value of an enormous number of bits is obtained, and the number of bits corresponding to the count value is It is practically impossible to store the sequence instruction data in the sequence selection circuit 4, and it is impossible for the pseudo random number generation circuit 5 to be able to generate the number of sequences corresponding to the count value. Is. Therefore, in practice, the count value N of the counter 2 is the lower predetermined number of bits of the count value when the number of clocks CK during the pulse time of the pulse A is counted. The predetermined number of bits may be set as follows.

That is, the pulse width of the output pulse A of the pulse generation circuit 1 does not change from zero to a certain maximum width even if the oscillation frequency of the oscillator used for the fluctuation fluctuates, and the width of a certain value. Change around. Therefore, the number of bits of the count value N may be determined so that the count value N of the counter 2 includes the narrowest possible range including at least the change range of the pulse width. For example, when the number of clocks CK included in the pulse width changes between 8000 and 9000 due to fluctuations in the pulse width of the pulse A, the change amount is 1000 and the counter value N may be 10 bits. Good.

The pulse width of the pulse A is set to the clock CK.
The reason for increasing the period to about 10 million times is to detect a slight fluctuation of the oscillation frequency of the oscillator in the pulse generation circuit 1.

As described above, in this embodiment, the pulse A
Since pseudo random numbers of different series are output from the pseudo random number generating circuit 5 along with the random fluctuation of the pulse width of, the obtained pseudo random number has no periodicity. Moreover, when the power is turned on to start up, the pseudo random number generation circuit 5
The sequence output from is not limited to a specific sequence, and thus a battery for backup such as the pseudo random number generator described in FIG. 9 is unnecessary,
Stable operation is performed without malfunction due to sudden noise. Furthermore, except for the resistor R, the capacitor C, and the coil L of the oscillator in the pulse generation circuit 1, a digital circuit can be used. If a custom or semi-custom digital IC is used in the equipment using this embodiment,
By incorporating this embodiment into this digital IC, it is possible to use the above-mentioned resistors, capacitors, coils, and the like with low precision as external parts, reduce the number of parts and the labor of assembly, and increase cost and size. It is possible to eliminate the inconvenience. Furthermore, since the pseudo random number generation circuit 5 outputs the pseudo random number in synchronization with the clock CK,
The operation speed is also very fast.

Next, a concrete example of each part in FIG. 1 will be described. FIG. 2 shows the pulse generating circuit 1 and the counter 2 in FIG.
1a is a CR oscillator, 1b is a frequency divider, 6 is an AND gate, 7 and 8 are delay circuits, and 9a to 9e are T-FFs (T-type flip-flop circuits). Reference numeral 10 is a latch circuit, and the portions and signals corresponding to those in FIG.

In the figure, the pulse generation circuit 1 comprises a CR oscillator 1a and a frequency divider 1b, and the frequency divider 1b has n stages (where n is an integer of 2 or more) cascade-connected T-FF.
And an OR circuit that receives the Q output of these T-FFs as an input. The output pulse of the CR oscillator 1a is divided by the frequency divider 1b, and the period t of the output pulse of the CR oscillator 1a is t.
2 (n-1) times the period T and the pulse width is (T-
A pulse A of t / 2) is obtained. The high level period of the pulse A shown in FIG. 4 is the period of the pulse width (T−t / 2).

In the counter 2, the clock CK shown in FIG. 4 passes through the AND gate 6 during the pulse period of the pulse A. Clock CK that passed AND gate 6
Is counted by five T-FFs 9a to 9e connected in cascade. Here, since the clock CK is counted using five T-FFs 9a to 9e, these T-FFs 9a to 9e are used.
The count value B having the Q output of the FFs 9a to 9e as a constituent bit repeats 0 to 31 while the clock CK is supplied through the AND gate 6, as shown in FIG.

On the other hand, the pulse A is supplied to the delay circuit 7,
A latch pulse RC is generated with a delay of time Δt from the falling edge thereof, the latch pulse RC is supplied to the delay circuit 8, and a reset pulse RS is generated with a delay of time Δt ′ from the falling edge thereof. However, as shown in FIG. 4, both the latch pulse RC and the reset pulse RS are delayed by the delay circuits 7 and 8 so that the latch pulse RC and the reset pulse RS fall between the trailing edge of the pulse A and the trailing edge of the next pulse A. Times Δt and Δt ′ are set.

The count value B obtained by the T-FFs 9a to 9e is latched in the latch circuit 10 by the latch pulse RC, and then by the reset pulse RS, the T-FF 9a.
9e are reset, and the count value B becomes zero. When the pulse generating circuit 1 outputs the pulse A again, the T-FFs 9a to 9e count the clocks CK as described above.

The count value latched by the latch circuit 10 is the count value N of the counter 2. Now, the value N latched in the latch circuit 10 is set to Ca as shown in FIG. 4, and the count value B of the T-FFs 9a to 9e at the timing of the next latch pulse RC is set as shown in FIG. , Cb, the latch pulse RC causes the output value N of the latch circuit 10 to change from Ca to Cb as shown in FIG.
Change to

The count value N latched in the latch circuit 10 is composed of the lower 5 bits of the count value when the total number of clocks CK that have passed through the AND gate 6 is counted during the pulse period of the pulse A. It means that the range of 0 to 31 times the cycle of the clock CK is detected in the fluctuation range of the cycle of the pulse A due to the fluctuation of the oscillation frequency of the oscillator 1a. For example, clock CK
When the period of pulse A is 1 μsec, it is effective, for example, when the period of pulse A varies from 10 sec to 0 to 31 μsec. Of course, the cycle of the pulse A may fluctuate further, but if the fluctuation amount of the pulse width of the pulse A is ΔT μsec, the count value N is always 0 ≦ (ΔT−32k) ≦ 3.
A value of 1 (however, k = 0, 1, 2, ...) (ΔT-32
k).

FIG. 3 is a block diagram showing a specific example of the sequence selection circuit 4 and the pseudo random number generation circuit 5 in FIG.
11 is a ROM (Read Only Memory), 121 to 1
2 m is an AND gate, 131 to 13 m is a D-FF, 14
1 to 14 m are ExOR circuits.

In the figure, the sequence selection circuit 4 is a ROM 1
It consists of 1. The ROM 11 stores m-bit different series designation data SD at ^{25 5} individual addresses, and the count value N from the counter 2 (FIG. 2) is used as an address signal to be designated by the count value N. Address series designation data SD is read. Here, as described in FIG. 2, the count value N of the counter 2 is
Is 5 bits, it is assumed that the ROM 11 stores 2 ⁵ pieces of sequence designation data SD.

The pseudo random number generating circuit 5 basically has the same circuit configuration as that of FIG. 8, but corresponds to changing the generator polynomial according to the sequence designation data SD from the sequence selecting circuit 4. This generates pseudo-random numbers of different series.

That is, m D-FFs 131 to 13m are connected in cascade, and the ExoR circuit 141 is connected to each data input side.
14m are provided, and the Q output of the final stage D-FF 13m is configured to be transferred to these ExoR circuits 141, 142, ..., 14m via AND gates 121, 122 ,. These and gates 1
, 122, 123, ..., 12m are controlled to be turned on / off by different bits of the m-bit sequence instruction data, and when the AND gate 12i (i = 1, 2, ..., M) is turned on, D- via the ExOR circuit 14i
The Q output of the D-FF 13m at the last stage is fed back to the FF 13i. Therefore, as shown in FIG. 4, when the count value N changes from Ca to Cb and the value of the series instruction data SD changes from Sa to Sb, the AND gate to be turned on among the AND gates 121 to 12m changes. This is equivalent to setting different generator polynomials, and the pseudo random number H that is eventually output
However, as shown in FIG. 4, the sequence of a ₁ , a ₂ , ... Is changed from the sequence of b ₁ , b ₂ , ... Is repeated, and the obtained sequence of pseudorandom numbers H is completely different.

FIG. 5 is a block diagram showing an embodiment of the photoelectric switch according to the present invention which uses the pseudo random number generator described above, wherein 15 is a pseudo random number generator and 16 is an R-P.
PM (random pulse position modulation) circuit, 17 sawtooth wave generation circuit, 18 D / A converter, 19 comparator, 20 one-shot circuit, 21 light projecting unit, 22 light receiving unit, 23 gate circuit, Reference numeral 24 is an integrator circuit, 25 is a determination circuit, and 26 is an object. The parts corresponding to those in FIG.

FIG. 6 is a timing chart showing the signals of the respective parts in FIG. 5, and the signals corresponding to those in FIG. 5 are designated by the same reference numerals.

In FIGS. 5 and 6, the clock CK from the clock generation circuit 9 of the pseudo random number generator 15 is RP.
The sawtooth wave generation circuit 17 of the PM circuit 16 supplies the sawtooth wave signal C to form the sawtooth wave signal C, which is supplied to the comparator 19. In addition, the digital-valued pseudo-random number H output from the pseudo-random number generator 15 is generated by the R-PPM circuit 16.
After being converted to an analog value D by the D / A converter 18,
The comparator 19 compares the level with the sawtooth wave signal C from the sawtooth wave generation circuit 17, and forms a pulse E that becomes "H" (high level) at the level of the analog value D≥the sawtooth wave signal C. Since the analog value D changes randomly, the pulse E is pulse width-modulated so that the pulse width changes randomly. The one-shot circuit 20 is triggered by the falling edge of the pulse E, and a pulse F of "H" having a narrow constant pulse width determined by the time constant of the one-shot circuit 20 is generated in synchronization with the falling edge. .. The pulse F is a pulse in which the position of the clock signal CK is randomly modulated.

The light projecting section 21 is driven by this pulse F, and projects the sensing light in a pulse shape at the same timing and duty ratio as this driving pulse F. This sensing light is the object 26
When reflected by, the reflected light is received by the light receiving section 22,
The pulse G is output. The pulse G has the same timing as the drive pulse F if it is obtained by the reflected light from the light projecting section 21 of itself, but it is obtained by receiving the sensing light from another photoelectric switch. If so, the timing does not match the drive pulse F.
Therefore, the output pulse G of the light receiving unit 22 is supplied to the gate circuit 23 that uses the drive pulse F as a gate pulse, and the pulse G
Only the pulse generated by the self-projection is extracted. The output pulse I of the gate circuit 23 is driven by the integration circuit 24 to generate a drive pulse F.
When the integrated value is taken in and integrated at a timing of, and the integrated value is equal to or more than a preset threshold value, the determination circuit 25 outputs a determination signal J indicating that an object exists.

As described above, in this embodiment, the light projecting section 2
Since the drive pulse F of 1 is random-position-modulated by the pseudo-random number H output from the pseudo-random number generator 15 that operates as described above, the sensing light is generated at random, and thus the sensing light is generated. The probability that mutual interference will occur is extremely small between the photoelectric switches that generate.

The pseudo random number generator according to the present invention is
It goes without saying that the present invention can be applied not only to the photoelectric switch but also to other devices using pseudo random numbers.

[0047]

As described above, according to the pseudo-random number generator according to the present invention, it is possible to generate a plurality of sequences of pseudo-random numbers that can be generated and randomly select and output them. The randomness of the arrangement order of the generated pseudo-random numbers is significantly improved.

Further, according to the photoelectric switch of the present invention, the randomness of the light projecting timing of the light projecting section is significantly improved, and the probability of mutual interference can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo random number generator according to the present invention.

FIG. 2 is a configuration diagram showing a specific example of a pack generation circuit and a counter in FIG.

3 is a configuration diagram showing a specific example of a sequence selection circuit and a pseudo random number generation circuit in FIG.

FIG. 4 is a timing diagram showing signals of respective parts of FIGS. 2 and 3.

FIG. 5 is a block diagram showing an embodiment of a photoelectric switch according to the present invention.

FIG. 6 is a timing chart showing signals of various parts in FIG.

FIG. 7 is a block diagram showing an example of a conventional pseudo-random number generator.

FIG. 8 is a block diagram showing another example of a conventional pseudo random number generation device.

FIG. 9 is a block diagram showing still another example of a conventional pseudo random number generation device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse generation circuit 2 counter 3 clock generation circuit 4 sequence selection circuit 5 pseudo random number generation circuit 15 pseudo random number generation device 16 random pulse position modulation circuit 17 sawtooth wave generation circuit 18 A / D converter 19 comparator 20 one shot circuit 21 light projection Part 22 Light receiving part 23 Gate circuit 24 Integration circuit 25 Judgment circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Ikuro Ouchi 1-13-10 Nishi-Odori, Hanamaki-shi, Iwate Shan Paul 203

Claims (2)

[Claims] 1. A pulse generating means for generating a pulse having an unstable cycle, a counting means for counting a period clock corresponding to the cycle for each cycle of the pulse, and a pseudo-random number according to a count value of the counting means. Sequence instructing means for outputting sequence instructing data, and pseudo random number generating means for generating pseudo random numbers in different sequences and for generating pseudo random numbers in a sequence according to the pseudo random number sequence instructing data from the sequence instructing means And a pseudo random number sequence that can be generated by the pseudo random number generating means in a random order for each period of the pulse generated by the pulse generating means. Random number generator. 2. A photoelectric switch that projects light from a light projecting portion and receives reflected light from an object to determine the presence or absence of the object, wherein the pseudo random number generated by the pseudo random number generator according to claim 1. First means for converting a numerical value into an analog value; second means for generating a sawtooth wave or triangular wave signal from the clock of the pseudo-random number generator; and comparing the level of the signal with the analog value. Third means for generating a pulse in which the phase of a rising edge or a falling edge with respect to the signal changes according to the analog value, and fourth means for making the time width of the output pulse of the third means constant And a light output timing of the light projecting section is set by the output pulse of the fourth means.