JPH05241864A - Method for controlling computer - Google Patents

Abstract

PURPOSE: To execute plural instructions in parallel without deceleration by means of an error in the result of the instruction which is not finally used by permitting the succeeding instruction to utilize the preceding instruction and adding a stage for executing an exception command when the result contains an error command. CONSTITUTION: In step 1, one or plural instructions within the plural instructions are designated as the preceding instruction. One preceding instruction is executed in the step 2 and an exception code is stored in the result of the instruction so as to set an error tag bit in the step 4 when the error is detected. The execution of the instruction is continued in the step 5. When the result of the preceding instruction is used, a check operation for recognizing whether or not the error tag bit is set is executed in the step 7. Then, at the time of setting, the execution of a program is stopped in the step 8 and a user is reported concerning the instruction being the cause of the error.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates generally to computers, and more particularly to a method for controlling the operation of a high speed computer, said high speed computer comprising a plurality of Instructions are executed in parallel and any erroneous results
It is particularly relevant to parallel processor computers in which the erroneous result is ignored until later use.

[0002]

BACKGROUND OF THE INVENTION The present invention is useful in connection with computer systems that allow multiple operations to execute concurrently. The concurrency is achieved either by initiating multiple operations at the same time, or by initiating a new operation prior to the completion of one or more previously initiated operations. In such systems, it is often advantageous to move operations through program branch or jump instructions. Movement of the code through the program's planch enhances parallelization.

Consider the following program. IF (A.LT.TAN (Y (I))) GO TO
100 Z = TAN (X (I)) 100 CONTINUE

In conventional computer systems, the conditional (A.LT.TAN (Y (I))) evaluation is completed before the branch of the program for statement 100 is executed or continues. A decision is made whether to continue the flow through the statement. After the branch condition is evaluated, the computer loads the value of X (I) from computer memory and evaluates the result with the TAN function. The result is stored in a memory or register location and used to represent the variable Z.

Now consider the modified program. TEMP Z = TAN (X (I)) IF (A.LT.TAN (Y (I))) GO TO
100 Z = TEMP Z 100 CONTINUE

This modified program can have the same performance but better performance than the original program for parallel computers. In this modified program, TAN (X
(I)) and TAN (Y (I)) can be evaluated in parallel. ． LT. If the program fails through the branch due to a failure in the comparison of
Only a simple designation of MPZ to Z is required. Thus, for programs that often lead to failures through statements in branches, the modified program allows for significant parallelization of TAN (X (I)) and TAN (Y (I)). Can be used fast.

Although this modified program is more parallel, it does not behave exactly the same in terms of error. 10 depending on the original program
It may execute branches up to 0 and terminate without error, whereas the modified program may stop with an error. This can occur because the index I for array X (I) is outside the array boundaries, or TAN (X
This is because either (I)) causes an arithmetic error. Since the original program never evaluated these statements, it would not cause such an error. This modification is often said to be "uneasy" because the modified program causes the error when it was not the original program and is not allowed by conventional compilation techniques. An operation that is moved through a branch of a program is called a "predecessor" operation when there is potential for that execution operation, even though it was not executed in the original program.

It is an object of the present invention to allow the optimization of an anxious program while retaining the exact behavior of the program with respect to errors. The optimizations allowed by this introduce additional parallelism within the program.

[0009]

[Means for solving the problem]

b. Prior Solution The most major prior solution is to not tolerate insecure optimization. Insecure optimizations are selectively allowed when an operation is moved through a branch, or when the operation does not cause an error (eg, address addition is specified to not cause an error). It was Because of this, the only predecessor operations that are allowed are those that do not cause an error.

Mutiflow Inc. in the Trace family of computer products. The solution sought by is to maintain an awkward optimization by ignoring the error. By disabling arithmetic violations and memory reference violations, the behavior of the original and modified programs shown above is equivalent, and neither program is stopped by an error. However, certain difficulties with this are presented to the user so that error checking operations must be ignored in order to achieve the highest level of performance.

C. DESCRIPTION OF THE INVENTION In prior implementations, in addition to the additional data values as contrasted with conventional computer systems, both additional operation codes (OP codes).
Is used. This additional opcode determines whether a given op is a normal op, or its predecessor. An additional data value is one data item is a good data item (valid)
Or is the result of an error that occurred during a previous execution (invalid).

In one implementation, prior execution is enabled by an error tag bit in all registers of the processor that distinguishes normal from erroneous values, and also on all opcodes. The predecessor execute bit distinguishes the predecessor operation from the normal operation.

Execution of operations is done in either normal mode or predecessor mode. This mode decision is made by their opcodes that distinguish normal instructions from preceding instructions.

Normal Mode Execution When all input operands are valid and the operation is not the cause of the error, the normal valid result is stored in the result register. When an operation is the cause of an unmasked exception, the exception is asked to be handled and the program is stopped. If any of the input operands are marked invalid by the current error tag bit, then the program is halted by signaling that it is an exception to the preceding execution.

Execution in Speculative Mode In all cases, execution continues after execution of the preceding instruction. If the input operand does not have the error tag bit set, then the appropriate operation is performed. A valid result is stored when no error occurred during the execution of the operation. When an exception occurs during the execution of an operation, the error tag bit for the result is set and the exception code is written to the remaining bits of the result register (the normal data bits). If the error tag bit of any of the input operands is set, the error tag bit of the appropriate result operand is set. The exception code from one of the tagged input operands is copied to the result register. This action propagates the error forward.

[0016]

【Example】

Example of use of preceding execution The hardware for preceding execution can be as follows.

Consider the process of optimizing a computer program for effective execution on parallel processors. In the original program, all operations would be performed under conditions equivalent to the user's point of view of the unchanged source program. Under this non-optimized program, all operations are in their "home base block". That is, no operation is moved to a new base block via a branch,
The condition is changed, and the operation is executed under the changed condition. Under a non-optimized program, all operations are performed with the non-leading form of OP code. When an error occurs, all operations are suspended from execution because this is a true error in the source program and the user should be informed of its occurrence.

The optimizer initiates the task of parallelizing the program. One operation (in the previous base block)
A determination is made as to whether it is being issued at an earlier point in time, allowing the program's ability to execute to be enhanced. It is ensured that the operation will always be executed before it is moved towards the previous set of base blocks and any use of its result will occur. What can be included in this is to move the operation to multiple preceding base blocks. All operations that are moved towards the base block prior to going to the home block have their opcodes for the preceding form. This optimizing means also ensures that the result of the preceding operation is actually used in the home base block. Non-leading use can be inserted in the home block just to test for the presence of an undetected error.

When the original program runs to completion without error, the optimized predecessor program will run to completion. When the original program stops with an error, the optimized predecessor program also stops with an error. As is apparent, when multiple errors occur, the order of reporting the errors is different than the order of the errors within the source. However, this is generally a problem typical of compiler optimizations and not specific to prior executions.

The result of one preceding operation can be used as input to another preceding operation. In this case, the result of the final preceding operation in any concatenated use will have an error tag at the exact time at which at least one of the preceding operations caused an error. When the final operand is used in the home base block, the program will stop in error if any of the predecessors used in the calculation of the input operands caused the error. ..

Error Tag Organization Exception codes are typically encoded in the usual data fields of processor registers. What is determined by the error tag bit here is whether to interpret the data field as correct data or as an exception. Many valuable pieces of information can be placed in the exception code.

Character of error Violation of address Arithmetic overflow, arithmetic underflow, etc.

A tag that uniquely determines the value of the program counter when an erroneous operation is issued.

Set status bits that support re-execution of the operation. For example, with IEEE floating point operations, it is possible to perform all operations in hardware except for operations that result in unnormalized results. The calculation of the preceding denormalized result may be postponed until the preceding exception indicating that the result has been used in a non-predecessor part of the program has been executed.

D. Advantages of the Present Invention Over What It Was Previously The advantage of the present invention is that it preserves the behavior of the program in the presence of program errors while preserving the behavior of unsettled code (code to the base block preceding the home block). Movement). This allows the compiler parallelization to allow changes to the program to enhance parallelization without requiring the disabling of error checking operations. Both for the highest level of parallelism and the rigorous error checking operations typical of non-parallel processors,
The user is made to enjoy sufficient profit.

Computer hardware registers have one additional bit called the error tag bit. By setting the error tag bit to the first value, the data contained in the register is generated when the instruction that generated the corresponding data is executed in the normal mode instead of the preceding mode. Indicates that is generating an exception code.

The preceding tag word is placed in the destination register. The value of the counter contained in the tag word is at the time the previous instruction was executed. The value of this counter can be related to the history of the program counter and is made to indicate which previous instruction caused the error.

As shown in the exemplary drawings, the preferred inclusion in the method according to the invention designates one or more of the plurality of instructions as the preceding instruction (1 ), Executing one preceding instruction (2), when an error is detected (3), storing the exception code in the result of the instruction and setting the error tag bit (4), Continue execution of the instruction (5), when the result of the preceding instruction is used (6), perform a check operation to see if the error tag bit is set (7), and If so, it is to stop the execution of the program and inform the user about the instruction that caused the error.

[0029]

As described above, by using the present invention, a plurality of instructions can be executed in parallel without being slowed down by an error in the result of an instruction that is not finally used.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention.

Claims (1)

[Claims] 1. An instruction is designated as a preceding instruction, the instruction is executed, an exception code is stored as a result when an error is detected during the execution, and the next instruction is executed. And a step of executing an exception command if the next instruction utilizes a result of the preceding instruction and the result includes an error code.