JPH05241825A - Microprocessor - Google Patents

Abstract

PURPOSE:To decrease the using frequency of a branch instruction with a condition, and to shorten a processing time. CONSTITUTION:This device is equipped with an instruction memory 2 which stores an instruction for controlling a system, program counter l which designates the reading address, command decoder 3 which controls the operation of a processor by decoding the content of the instruction memory 2, P and Q registers 4 and 5 for an arithmetic input which store data to be computed, arithmetic circuit (EXU) 7 which inputs the data of the P and Q registers 4 and 5, R register 10 for an arithmetic output which stores the output data X, arithmetic flag register 11 which inputs and stores the flag of an arithmetic result from the arithmetic circuit 7 through a multiplexer (MUX) 12, and arithmetic control circuit 9 which controls the execution of a conditional arithmetic operation by using the value as a condition. The arithmetic flag register 11 independently stores the flag of the unconditional arithmetic result and the flag of the conditional arithmetic result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a structure of a computation flag register of a microprocessor capable of controlling execution of conditional computation on the condition of a value of a computation flag register.

[0002]

2. Description of the Related Art Conventionally, there have been microprocessors having one to two sets of operation flag registers and microprocessors having conditional operation instructions. The operation will be described below with an example. First, a microprocessor having a set of operation flag registers, for example, μPD701
There are 16 (trade names). When the operation circuit performs an operation, a plurality of bits of the operation flag register are affected by the operation result. Therefore, the conditional branch instruction is the only instruction that can be executed using the value of the operation flag register as a condition. Selection of execution / ignore of an operation based on the value of the operation flag register is performed by branching with a conditional branch instruction.

As a microprocessor having two sets of operation flag registers, a microprocessor having an operation flag register used in a native mode and an operation flag register used in an emulation mode, and two sets of operation flag registers There are some that can be switched with an exchange command. In both sets of operation flag registers, the conditional branch instruction is the only instruction that can be executed with the value of the operation flag register as a condition.

For a microprocessor having a conditional operation instruction, in addition to a conditional branch instruction, it is possible to select whether to execute or ignore the operation on the condition of the value of the operation flag register. When the condition is false, the operation is ignored and the value of the operation flag register is held, and when the condition is true, the operation is executed and the value of the operation flag register is updated. A conditional operation instruction can be used when the content of processing that is conditional on the value of the operation flag register is one instruction. However, when a plurality of operations are included, a conditional branch instruction is used for branching.

Having the conditional operation instruction in the microprocessor can reduce the execution of conditional branch instruction for selecting execution / ignore of the operation, which is effective in reducing the instruction memory and the processing time. Instruction fetch, decode,
It is especially effective in high-speed microprocessors that pipeline operand fetch, operation, and write back. Note that FIG. 4 is a flow chart showing a procedure of a division process using an example of a conventional microprocessor.

[0006]

The conventional microprocessor described above, even if it has a conditional operation instruction, is conditional if the processing contents conditional on the value of the operation flag register include a plurality of operations. It was necessary to branch and process with a branch instruction, and the effect of the conditional operation instruction could not be fully utilized.

An object of the present invention is to provide a microprocessor capable of processing only a conditional operation instruction without branching by a conditional branch instruction even in a processing including a plurality of conditional operation instructions whose condition is the value of an unconditional operation flag register. To provide.

[0008]

SUMMARY OF THE INVENTION A microprocessor of the present invention stores an instruction memory for storing instructions for controlling a system, a program counter for designating a read address of the instruction memory, and contents of the instruction memory. An instruction decoder that decodes and controls the operation of the processor, an operation input register that stores the operation target data, an operation circuit that receives the data of the operation input register as an input, and an operation output register that stores the output data of the operation circuit. In a microprocessor having an operation flag register for storing a flag of an operation result in the operation circuit and an operation control circuit for controlling execution of conditional operation on the condition of the value of the operation flag register, the operation flag register is: Consists of a register that stores the unconditional operation result flag and the conditional operation result flag independently It is.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of the first embodiment of the present invention.
The microprocessor of this embodiment includes an instruction memory 2 for storing instructions for controlling the system, a program counter 1 for designating a read address of the instruction memory 2, and an instruction memory 2.
An instruction decoder 3 for decoding the contents of the above and controlling the operation of the processor, P and Q registers 4 and 5 for operation input for storing data to be operated, and an operation circuit for receiving the data of P and Q registers 4 and 5 (EXU) 7, an R register 10 for operation output that stores the output data X thereof, and a flag of the operation result Y in the operation circuit 7 to a multiplexer (MUX) 12
An operation flag register 11 which is input and stored through
The operation flag register 11 has an operation control circuit 9 for controlling the execution of conditional operation using the value as a condition. The operation flag register 11 internally stores two flags, an unconditional operation result flag and a conditional operation result flag. It is configured.

The register program counter 1 is a register indicating the address of the instruction memory 2, and can be incremented and rewritten by an instruction. The instruction memory 2 is a memory for storing instructions for controlling the system, and the content S of the address S1 designated by the program counter 1
2 is output to the instruction decoder 3. Instruction decoder 3
Outputs the control signal S3 for each unit in the microprocessor which decodes the instruction S2 selectively output from the instruction memory 2 and controls the operation of the processor. The P register 4 and the Q register 5 are operation input registers that store data to be operated, and can input data from the main bus 6. The arithmetic circuit 7 is an arithmetic circuit to which the data of the P register 4 and the Q register 5 are input.

The multiplexer 8 is a P register or an arithmetic circuit 7 according to a control signal S9 output from the arithmetic control circuit 9.
The output signal Y or X is selected and the signal S8 is output to the R register 10. Data S1 of R register 10
0 is output to the main bus 6. Arithmetic control circuit 9
Outputs a control signal S9 to the multiplexers 8, 12, and 13 in accordance with the type of operation decoded by the instruction decoder 3.

Table 1 shows the relationship between the type of operation and the selection signal of each multiplexer. The operation flag register 11 is a register that stores data in which a flag of an unconditional operation result is in the upper part and a flag of the condition operation result is in a lower part.

[0013]

[Table 1]

FIG. 2 is a flow chart showing a procedure for a division process using the microprocessor of this embodiment. The effects of this embodiment are shown in the conditional operation S4 and the conditional operation S5 in the process B. For example, if the unconditional operation and the conditional operation are 1 cycle instruction and the conditional branch instruction is 2 cycle instruction, and the number of loops N is 16, the microprocessor of this embodiment can process in 113 cycles,
A conventional microprocessor requires up to 145 cycles. According to this embodiment, the number of instructions can be reduced and the processing time can be shortened by 20% or more.

FIG. 3 is a block diagram of the second embodiment of the present invention. The operation flag encoder 14 is a logic circuit that converts the flag of the operation result of the operation circuit 7 into a condition flag. As an example, Table 2 shows output data when the zero flag and the sine flag are input to the operation flag encoder.

[0016]

[Table 2]

The unconditional operation flag register 11a is a register for storing the condition flag of the unconditional operation result, and the conditional operation flag register 11b is a register for storing the condition flag of the condition operation result. The data of the unconditional operation flag register 11a and the conditional operation flag register 11b can be output to the main bus 6. The effect of this embodiment is similar to that of the first embodiment.

[0018]

As described above, the microprocessor of the present invention executes an operation flag register that stores a flag of an unconditional operation result and a flag of a condition operation result, and executes a conditional operation on the condition of the value of the operation flag register. Since it has an operation control circuit for controlling, the value of the unconditional operation flag register and the value of the conditional operation flag register can be evaluated independently, and a plurality of conditional operation instructions can be controlled by the result of one unconditional operation. Therefore, it is possible to reduce the execution of conditional branch instructions for selecting whether to execute or ignore the operation, and it is possible to reduce the instruction memory and the processing time.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flow chart showing a procedure when a division process is performed using the microprocessor of FIG.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure when a division process is performed using an example of a conventional microprocessor.

[Explanation of Codes] 1 Program Counter 2 Instruction Memory 3 Instruction Decoder 4 P Register 5 Q Register 6 Main Bus 7 Operation Circuit 8, 12, 13 Multiplexer 9 Operation Control Circuit 10 R Register 11 Operation Flag Register 11a Unconditional Operation Flag Register 11b Conditional operation flag register 14 Operation flag encoder

Claims (1)

[Claims] 1. An instruction memory for storing an instruction for controlling a system, a program counter for designating a read address of the instruction memory, and an instruction decoder for decoding the content of the instruction memory and controlling the operation of a processor. , An operation input register for storing data to be operated, an operation circuit for receiving data of the operation input register, an operation output register for storing output data of the operation circuit, and a flag of an operation result in the operation circuit. In a microprocessor having an operation flag register to be stored and an operation control circuit for controlling execution of conditional operation on the condition of the value of the operation flag register, the operation flag register includes a flag of an unconditional operation result and a condition operation result. A microprocessor having a register that stores a flag independently.