JPH05241535A - Shift register - Google Patents

Abstract

PURPOSE:To prevent a malfunction caused by leakage due to a defect in breakdown strength between the source/drain of a transistor in a shift register using a clocked inverter. CONSTITUTION:The shift register 1 is constituted of D type flip-flop 2 multistage-connected. The D type flip-flop 2 of each stage is provided with a pair of clocked inverters 3, 4 and generates an output pulse signal successively in a shift clock. An N channel driving transistor S1 is connected to the power source side of the clocked inverters 3, 4 and a P channel driving transistor S2 is connected to the ground side. Since voltage drop corresponding to the threshold voltage of these driving transistors is caused, the hold potential of the clocked inverters 3, 4 are limited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register composed of clocked inverters, and more particularly to a circuit structure for preventing malfunction due to a leak current of a driving transistor.

[0002]

2. Description of the Related Art A shift register using a clocked inverter is used, for example, as a vertical scanning circuit or a horizontal scanning circuit of an active matrix type liquid crystal display device. To clarify the background of the present invention, a general configuration of an active matrix type liquid crystal display device will be briefly described with reference to FIG. This type of display device includes a plurality of gate lines X1, X2, ... Arranged in the X direction and a plurality of data lines Y1, Y2 ,. Thin film transistors (TFTs) T11, T12, T21, T22, ... Are formed at the intersections of the gate lines and the data lines. Also, the corresponding liquid crystal cells L11, L12, L
21, L22, ... Are also provided. The liquid crystal cell is composed of a liquid crystal layer sandwiched between each pixel electrode and a common electrode COM which is arranged to face each other. The gate electrode of the thin film transistor is connected to the corresponding gate line, the source electrode is connected to the corresponding data line, and the drain electrode is connected to the pixel electrode of the corresponding liquid crystal cell.

The plurality of gate lines X1, X2, ... Are connected to the vertical scanning circuit 101 and are supplied with gate signals line-sequentially.

On the other hand, the data lines Y1, Y2, ... Are connected to a common signal line SIG via the corresponding switching transistors P1, P2 ,. The gate electrodes of these switching transistors P1, P2, ... Are connected to the horizontal scanning circuit 102. Horizontal scanning circuit 102
In response to the pulse sequentially output from, each switching transistor becomes conductive and samples the video signal from the signal line SIG and sequentially distributes it to the corresponding data line.

The TFTs are selected row by row in response to a gate signal supplied from the gate line. Selected TFT
Writes the video signal supplied from the data line to the corresponding liquid crystal cell. After the application of the gate signal is released, the TFT becomes non-conductive and holds the video signal written in the liquid crystal cell. An image is displayed by such a sampling hold.

The configuration of the shift register included in the vertical scanning circuit shown in FIG. 5 will be briefly described with reference to FIG.
This shift register 103 is a D-type flip-flop 10.
4 has a multi-stage connection structure. Each D-type flip-flop 104 is composed of a pair of inverters 105 and 106 whose output terminals are commonly connected. Each inverter is P
It is connected to the power supply side via a channel type drive transistor 107 and is connected to the ground side via an N channel type drive transistor 108. The pair of drive transistors 107 and 108 are turned on in response to the shift clock pulses φ1 and φ2 and drive the inverter. Inverters 105, 10 driven in this way
Reference numeral 6 is a so-called clocked inverter. The input terminal of the third inverter 109 is connected to the commonly connected output terminals of the pair of inverters 105 and 106. The output pulse of the D-type flip-flop of each stage appears at the output terminal of the third inverter 109. This output pulse is also used as the input of the D-type flip-flop of the next stage.

It should be noted that in FIG.
Only the flip-flops in the second and second stages are shown.
The start pulse input to the first-stage flip-flop 104 is represented by B0, and a pair of inverters 105, 10
The hold potential held by 6 is represented by A1, and the output pulse is represented by B1. Similarly, the output pulse of the second-stage flip-flop is represented by B2. The output pulses B1, B2, ... Generated sequentially are supplied to the gate line shown in FIG. 5 as a gate signal after being subjected to a predetermined logic process.

[0008]

Problems of the shift register shown in FIG. 6 will be briefly described with reference to FIGS. 7 and 8. FIG. 7 is an operation waveform diagram of the shift register. The start pulse B0 is supplied to the D-type flip-flop in the first stage. When the N-channel drive transistor 108 connected to the ground side and the P-channel drive transistor 107 connected to the power supply side become conductive in response to the clock pulse φ1 and its inverted clock pulse, the clocked inverter 105 is driven to start pulse. B0 is inverted and held. The hold potential A1 at this time is the ground level or the ground level VSS. The clocked inverter 105 is driven again by the input of the next clock pulse φ1 and its inverted clock pulse, and the start pulse B0 is inverted and latched. Since the start pulse B0 is falling at this time, it is at a low level and the hold potential A
1 becomes equal to the power supply level VDD. The potential A1 held in this way is inverted and output via the third inverter 109, and the output pulse B1 of the head stage is generated. As is clear from the timing chart, the first output pulse B1 is shifted from the start pulse B0 by the half cycle portion of the clock pulse train. By the similar operation, the D-type flip-flop of the second stage receives the input of the output pulse B1 and generates the output pulse B2 of the stage. In this way
Output pulses B1, B2 sequentially shifted by half a cycle
... is generated. The pair of drive transistors for driving the second-stage clocked inverter are clock pulse φ.
It operates in response to the clock pulse φ2 and its inversion pulse whose period is deviated from 1 by a half period.

Generally, in an active matrix type liquid crystal display device or the like, the vertical scanning circuit has a lower operating frequency than the horizontal scanning circuit. Therefore, clock pulses φ1 and φ2
A predetermined space interval F is created between and. During this period,
Since the four drive transistors incorporated in the D-type flip-flop are all non-conductive, the pair of inverters are in a floating state. At this time, a high drain voltage is applied to the N-channel transistor when the hold potential is held at the power supply level VDD, for example. This high drain voltage causes a problem that a leak current occurs in the transistor and the hold potential fluctuates.
If this variation exceeds the threshold voltage of the output inverter, it will be inverted and malfunction will occur. Also, when the hold potential is held at the ground level VSS, a similar leak current occurs on the P-channel transistor side.

[0010] Figure 8 is a gate voltage V _G of the individual transistors constituting the shift register shown in FIG. 6 - shows the drain current I _D characteristics. The drain current is represented by a logarithmic memory for easy understanding. In the monolithic type in which the peripheral circuit and the display circuit are formed on the same substrate, the transistors constituting the shift register generally have a thin film transistor (TFT) structure made of polycrystalline silicon or the like. As shown in FIG. 8, when a high drain voltage is applied to the TFT, there is a defect that a high off current or a leak current flows even in a non-conducting state. Therefore, when a shift register is constructed using such TFTs, there is a problem that the hold potential fluctuates and a malfunction occurs in the floating state of the clocked inverter as described above.

[0011]

SUMMARY OF THE INVENTION In view of the above-mentioned problems or problems of the conventional technique, an object of the present invention is to prevent malfunction of a shift register due to a leak current of a transistor. The following measures have been taken in order to achieve this purpose. That is, in a shift register that sequentially generates output pulse signals in shift clock units using a clocked inverter, a means of connecting an N-channel drive transistor to the power supply side and a P-channel drive transistor to the ground side has been taken. That is, the drive transistor on the power supply side and the drive transistor on the ground side are replaced with each other in the conventional circuit configuration.

[0012]

When the N-channel drive transistor is connected to the power supply side, the hold potential can be suppressed because the voltage drop occurs by the threshold voltage. Further, since the P-channel drive transistor is connected to the ground side, a voltage drop similarly occurs for the threshold voltage, and the hold potential can be suppressed. Therefore, since the source / drain voltage of each transistor is suppressed in the floating state, the leak current is reduced,
It is possible to suppress fluctuations in the hold potential. Even if the hold potential is limited by the threshold voltage of the drive transistor, there is no problem in operation as long as it is within the range that crosses the threshold voltage of the output inverter.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a shift register according to the present invention. This shift register is used, for example, in a vertical scanning circuit integrally incorporated in a liquid crystal display device of a monolithic active matrix type. The shift register 1 is composed of D-type flip-flops 2 connected in multiple stages. 1 to simplify the illustration
Only the columns are shown. The D-type flip-flop 2 includes a pair of inverters 3 and 4 whose output terminals are commonly connected. Each inverter has a CMOS structure and includes a P-channel transistor M1 and an N-channel transistor M2.
Drain electrodes are connected to each other. An N-channel drive transistor S1 is connected to the power supply side of each inverter, and a P-channel drive transistor S2 is connected to the ground side. The arrangement of the pair of drive transistors S1 and S2 is opposite to that of the conventional example. Furthermore, the third inverter 5 is connected to the output terminals of the pair of inverters 3 and 4 that are commonly connected. The inverter 5 is for inverting the hold potential A and generating an output pulse B. Since the shift register 1 in which the D-type flip-flops 2 having such a configuration are connected in multiple stages basically has the same configuration as the conventional example shown in FIG. 6, its transfer operation will be easily understood. However, the polarities of the clock pulses φ1 and φ2 applied to the respective drive transistors are inverted because the drive transistors are replaced.

Next, the operation of the D-type flip-flop 2 shown in FIG. 1 will be described in detail with reference to FIG. Inverter 3
Is a so-called clocked inverter because it is driven only when the pair of drive transistors S1 and S2 become conductive in response to the clock pulse φ1 and its inverted pulse. However, since the N-channel drive transistor S1 is connected to the power source side of the inverter 3, a voltage drop occurs by the threshold voltage Vthn, and C shown in FIG.
The potential at the point rises only to VDD− | Vthn |.
Further, since the P-channel drive transistor S2 is connected to the ground side of the inverter 3, its threshold voltage Vth
A voltage drop corresponding to p occurs, and the potential at the point D shown in FIG. 1 drops only to VSS + | Vthp |. Therefore,
The hold potential A is limited according to these voltage drops. Therefore, the transistor M forming the inverter 3
The voltage applied between the source and drain of M1 and VDD is VDD-
VSS- | Vthn |-| Vthp | becomes conventional VD
It is smaller than D-VSS. Therefore, the transistor M
1, M2 is the gate voltage V at the low drain voltage shown in FIG.
_The leakage current is suppressed because it follows the _G -drain current _ID characteristic.

Although the hold potential A is limited as described above, no trouble occurs in the transfer operation as long as it is within the range that crosses the threshold voltage Vthi of the output inverter 5 shown in FIG.
That is, the output pulse B of the shift register 1 is inverted between the power supply potential VDD and the ground potential VSS according to the normal operation.
As an example, to enumerate the characteristics of a thin film transistor incorporated in a peripheral circuit of an active matrix liquid crystal display device, VDD = 14V, VSS = 0V, Vthn = 3.
V, Vthp = −3V, threshold voltage Vt of output inverter
Since hi = 7V, no problem occurs in operation.
The source-drain voltage is 8 compared to the conventional 14V.
V can be suppressed.

Next, another embodiment of the shift register according to the present invention will be described with reference to FIG. FIG. 3 shows only one D-type flip-flop included in the shift register, and the same components as those of the embodiment shown in FIG. 1 are designated by the same reference numerals to facilitate understanding. The difference from the embodiment shown in FIG. 1 is that n diode-connected N-channel transistors R1 are inserted between the N-channel drive transistor S1 and the transistor M1 forming an inverter on the power supply side. Further, on the ground side, m diode-connected P-channel transistors R2 are inserted between the P-channel drive transistor S2 and the transistor M2 forming the inverter. Even when the structure of the embodiment shown in FIG. 1 is adopted, these diode-connected transistors are inserted when the leakage due to the source / drain voltage poses a problem. Leakage can be effectively suppressed by appropriately setting the number of insertions. In this case, the source-drain voltage is VDD-VS
It is given by S−n × | Vthn | −m × | Vthp |.

FIG. 4 shows still another embodiment. For the sake of easy understanding, only one D-type flip-flop is shown, and the same components as those of the embodiment of FIG. 1 are designated by the same reference numerals. A resistor R is inserted between the N-channel drive transistor S1 and a transistor M1 forming an inverter in order to adjust the source / drain voltage more delicately than that of the embodiment shown in FIG. A resistor R is also provided between the transistor M2 and the P-channel drive transistor S2 that constitute the above. The source / drain voltage can be set to a desired value by adjusting these resistances. These resistors R are
For example, the thin film transistor can be introduced by forming a so-called LDD structure.

[0018]

As described above, according to the present invention, in the shift register using the clocked inverter,
By connecting the N-channel drive transistor to the power supply side and the P-channel drive transistor to the ground side,
The hold potential of the clocked inverter can be limited by the threshold voltage of these drive transistors. Therefore, since the source / drain voltage is suppressed, the fluctuation of the hold potential due to the leakage current can be suppressed, and the malfunction caused by the leakage due to the insufficient withstand voltage of the transistor can be effectively prevented. In particular, since the present invention can be achieved by replacing the N-channel drive transistor and the P-channel drive transistor with respect to the conventional structure, there is an effect that there is no need to increase the number of elements and the circuit configuration is efficient. Further, since the source-drain voltage can be suppressed without performing any timing control, there is an effect that the transfer operation of the shift register is not adversely affected.

[Brief description of drawings]

FIG. 1 is a schematic partial circuit diagram showing an embodiment of a shift register according to the present invention.

FIG. 2 is an operation explanatory diagram of a D-type flip-flop included in the shift register shown in FIG.

FIG. 3 is a circuit diagram showing another embodiment of the shift register according to the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the shift register according to the present invention.

FIG. 5 is a circuit diagram showing a general configuration of an active matrix type liquid crystal display device incorporating a vertical scanning circuit including a shift register.

FIG. 6 is a circuit diagram showing a conventional shift register.

FIG. 7 is an operation timing chart of a conventional shift register.

FIG. 8 is a graph showing gate voltage-drain current characteristics of a thin film transistor which constitutes a shift register.

[Explanation of symbols]

 1 shift register 2 D-type flip-flop 3 clocked inverter 4 clocked inverter 5 output inverter S1 N-channel drive transistor S2 P-channel drive transistor R1 diode-connected N-channel transistor R2 diode-connected P-channel transistor

Claims (2)

[Claims] 1. A shift register, which uses a clocked inverter to sequentially generate an output signal in shift clock units, wherein an N-channel drive transistor is connected to a power supply side and a P-channel drive transistor is connected to a ground side, respectively. register. 2. The shift register according to claim 1, wherein a plurality of diode-connected transistors are inserted between the power supply and the ground.