JPH0523628U - Clock signal switching circuit - Google Patents

Abstract

(57) [Summary] [Embodiment] Each of the emitter follower circuits 11 to 1n inputs a different one of the n (n is a plurality) clock signals IN1 to INn and outputs it at the ECL level.
One of the emitter follower circuits 21 to 2n is connected in cascade to each of the emitter follower circuits 11 to 1n. The outputs of the emitter follower circuits 21 to 2n are input to the n input terminals of the selection circuit 3, respectively. The selection circuit 3 selects and outputs one of the input terminals under the control of the switching control signal CONT. At this time, the bias circuit 4 receives the selection control signal CONT according to the switching control signal CONT.
Turns off the emitter follower circuit connected to an input terminal other than the one selected by. [Effect] The increase in jitter of the output clock signal is suppressed by eliminating crosstalk in the selection circuit.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a clock signal switching circuit, and more particularly to a clock signal switching circuit for selecting and outputting one signal from a large number of high speed clock signals in a high speed communication device.

[0002]

[Prior Art]

 A conventional clock signal switching circuit will be described with reference to the circuit diagram of FIG.

To the clock signal switching circuit, n (n is a plurality) clock signals IN1 to INn are input. The clock signals IN1 to INn are respectively input to the emitter follower circuits 51 to 5n of AC coupling inputs, converted to ECL levels, and input to the input terminals 31 to 3n of the selection circuit (SEL) 3 composed of an IC circuit or the like, respectively. Is input. The SEL3 selects one of the input terminals 31 to 3n according to the control signal CONT and outputs one of the clock signals IN1 to INn converted to the ECL level corresponding to the selected input terminal. Output to terminal 301.

The emitter follower circuits 51 to 5n have the same circuit configuration. For example, explaining the operation of the emitter follower circuit 51, the input clock signal IN 1 is AC-coupled by the capacitor C51, is input to the base of the transistor TR51 via the protection resistor R53, and is connected to one end of the emitter follower resistor R54. It is converted into an ECL level and output to the emitter of the connected transistor TR51, and this is further input to the input terminal 31 of SEL3. As a bias of the transistor TR51, a voltage of, for example, −2V is applied from the bias terminal 501. The other end of the resistor R51 whose one end is grounded, and the other end of the resistor R52 whose one end is connected to the bias terminal 501 are connected to the input side of the clock signal IN1 of the protection resistor R53 and connected to the transistor TR51. Apply a bias voltage to the base. The other end of the emitter follower resistor R54 is also connected to the bias terminal 501 to apply a bias voltage to the emitter of the transistor TR51. The collector of the transistor TR 51 is grounded.

[0005]

[Problems to be solved by the device]

 This conventional clock signal switching circuit has a drawback that the output clock signal jitter increases due to crosstalk inside the selection circuit. This jitter tends to increase particularly in a selection circuit using an IC circuit.

[0006]

[Means for Solving the Problems]

 The clock signal switching circuit of the present invention comprises n multi-stage emitter-follower circuits for outputting different ones out of n (n is a plurality) clock signals input at an ECL level. A selection circuit in which each of the n input terminals is connected to each of the n emitter follower circuits to select one of the input terminals by a switching control signal; and an input terminal other than the selected input terminals. And a bias circuit for turning off the connected emitter follower circuit in response to the switching control signal.

[0007]

【Example】

 Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention.

To the clock signal switching circuit, n (n is a plurality) clock signals IN1 to INn are input as in the conventional example. The clock signals IN1 to INn are input to the emitter follower circuits 11 to 1n having AC coupling inputs, respectively, and converted into ECL levels. The clock signals IN1 to INn converted to the ECL level further pass through the emitter follower circuits 21 to 2n which are connected in series to the emitter follower circuits 11 to 1n, respectively, and the selection circuit (SEL) formed by an IC circuit or the like. ) 3 input terminals 31 to 3n, respectively. The SEL3 selects one of the input terminals 31 to 3n according to the control signal CONT and outputs one of the clock signals IN1 to INn converted to the ECL level corresponding to the selected input terminal as an output terminal. Output to 301.

When the selection circuit 3 selects one input terminal, the bias circuit (BIAS) 4 controlled by the control signal CONT is connected to the selected input terminal (for example, the input terminal 31). Only the two-stage configured emitter follower circuit (emitter follower circuits 11 and 21 in the above example) is turned on (by controlling the bias terminals 101 and 201 in the above example), and the other emitter follower circuits are turned off. To do. Therefore, a low-level clock signal is output from the emitter follower circuits connected in series to the unselected input terminals. Since the low level signal does not cause crosstalk in SEL3, the jitter of the clock signal output from SEL3 does not increase.

The emitter follower circuits are connected in cascade (for example, the emitter follower circuits 11 and 21) in order to complete the lot-off of the clock signal. The lot-off effect increases as the number of emitter follower circuits connected increases, but this increases power consumption, so the number of cascaded emitter follower circuits must be determined by the allowable crosstalk amount.

The emitter follower circuits 11 to 1n have the same circuit configuration. For example, to explain the operation of the emitter follower circuit 11, the input clock signal IN1 is AC-coupled by the capacitor C11, is input to the base of the transistor TR11 via the protection resistor R11, and is connected to one end of the emitter follower resistor R13. It is converted to the ECL level and output to the emitter of the connected transistor TR11. A bias voltage is applied to the base of the transistor TR11 from the bias terminal 101 via the resistor R12 and the protection resistor R11, and a bias voltage is applied to the emitter from the bias terminal 102 via the emitter follower resistor R54. .. The collector of the transistor TR11 is grounded.

The emitter follower circuits 21 to 2n have the same configuration as the emitter follower circuits 11 to 1n, although they are given different circuit codes. A bias voltage is supplied from the bias terminal 201 to the base of the transistor TR21 and from the bias terminal 202 to the emitter. Either the clock signal IN1 or INn converted to the ECL level is input to the capacitor C21 and is also output from the emitter of the transistor TR21.

The operations of the emitter follower circuits 11 to 1n and 21 to 2n described above will be described by taking the emitter follower circuit 11 as an example. Bias terminal 102 is always supplied with -2V. When turning on the emitter follower circuit 11, -0.5 V is supplied from BIAS4 to the bias terminal 101. Then, a signal in which the clock signal IN1 is at the ECL high level is output to the emitter of the transistor TR13. Further, when the emitter follower circuit 11 is turned off, −2V is supplied from the BIAS4 to the bias terminal 101. Then, the ECL low-level signal is output to the emitter of the transistor TR13.

[0014]

[Effect of the device]

 As described above, the present invention not only selects one of the input clock signals by the selection circuit, but also suppresses the unselected clock signal by the emitter follower circuits connected in cascade. The effect of crosstalk in the circuit can be eliminated, and the increase in jitter of the output clock signal can be eliminated.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional example.

[Description of Reference Signs] 3 selection circuit (SEL) 4 bias circuit (BIAS) 11 to 1n, 21 to 2n, 51 to 5n emitter follower circuit 31 to 3n input terminal 101, 102, 201, 202, 501 bias terminal 301 output terminal C11, C21, C51 capacitors R11 to R13, R21 to R23, R51 to R54
Resistor TR11, TR21, TR51 Transistor CONT Switching control signal IN1 to INn Clock signal

Claims (1)

[Scope of utility model registration request] 1. An n-stage multi-stage emitter follower circuit that outputs different ones of n (n is a plurality) clock signals that are input at an ECL level, and n input terminals, respectively. A selection circuit connected to each of the n emitter follower circuits to select one of the input terminals by a switching control signal, and an emitter follower circuit connected to an input terminal other than the selected input terminal. A clock signal switching circuit including a bias circuit that is turned off by a switching control signal.