JPH05236069A - Data transmission system - Google Patents

Abstract

PURPOSE:To remarkably save a cause discriminating time on the occurrence of a fault by allowing a subordinate equipment to use a check bit detector to detect a check bit of reception data, using a check bit inverter to invert the detected check bit and using a check bit addition device to add the inverted check bit to the transmission data. CONSTITUTION:When a transmission request comes, a host device 10 uses a check bit addition device 1 to add check bits A='0', B='1' to transmission data and sends the result to a transmission line 30. Upon the receipt of a signal from the transmission line 30, a subordinate device 20 uses a check bit detector 3 to detect the check bits and sends the detected bits '0', '1' to a check bit inverter 4, in which the check bit is inverted. The inverted check bit is fed to a check bit adder device 5, in which the check bit is added to the transmission data and the resulting data are sent to an incoming transmission line 40. Thus, a cause discrimination on the occurrence of a fault is remarkably decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system, and more particularly to a data transmission system between communication line monitoring devices.

[0002]

2. Description of the Related Art In a conventional data transmission system between communication line monitoring devices, a lower device detects the state of a transmission line based on a redundant code added by a higher device and notifies the upper device of the information. Or the upper device determines whether or not the line is disconnected depending on the presence or absence of a response from the receiving side.

[0003]

However, in the above-mentioned conventional example, since the state of each transmission line is not detected, when the transmission line is disconnected, the transmission line from the upper device to the lower device is changed in the upper device. It is difficult to identify whether the line is disconnected or the line from the lower device to the upper device is disconnected, and there is a disadvantage that extra time is spent in isolating the failure.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a data transmission system which can remedy the disadvantages of the prior art and can greatly reduce the cause isolation time especially when a failure occurs.

[0005]

Therefore, in the present invention, in a data transmission system comprising a higher-order device and a lower-order device for mutually transmitting and receiving data using a plurality of transmission paths,
The first is that the host device adds a check bit to the transmission data.
And a first check bit detecting means for detecting the check bit of the received data and checking the state of the transmission line, and the second check bit for detecting the check bit of the received data by the lower device. Detection means, check bit inverting means for inverting the check bit detected by the second check bit detecting means, and second check bit adding means for adding the check bit inverted by the check bit inverting means to the transmission data. Is adopted as a side-by-side configuration. This aims to achieve the above-mentioned object.

[0006]

In the host device, when a transmission request is generated, the first check bit adding means adds a check bit to the transmission data and sends it to the downlink transmission path. When receiving the signal from the downlink transmission line, the lower device detects the check bit by the second check bit detecting means. The second check bit detecting means sends the detected check bit to the check bit inverting means. The check bit inverting means inverts the check bit from the second check bit detecting means. The check bit inverting means sends the inverted check bit to the second check bit adding means. The second check bit adding means adds the check bit inverted by the check bit inverting means to the transmission data and sends it to the upstream transmission path. When the host device receives a signal from the upstream transmission line, the first check bit detecting means detects the check bit and compares the transmitted check bit with the received check bit to determine the state of each transmission line.

[0007]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

The embodiment shown in FIG. 1 has two transmission lines 30 and 40.
First check bit adding means 1 configured to add a check bit to the transmission data by the high-level device 10 and the low-level device 20 that mutually transmit and receive data using First check bit detecting means 2 for detecting and checking the state of the transmission path
And a second check bit detecting means 3 for detecting the check bit of the received data by the lower device 20, and
Check bit inverting means 4 for inverting the check bit detected by the check bit detecting means 3 and second check bit adding means 5 for adding the check bit inverted by the check bit inverting means 4 to the transmission data. To be done.

Next, the operation of this embodiment will be described.
Here, as shown in FIG. 2 as an example of the data format transmitted from the host device 10, one frame is synchronized with a sync (SYNC) signal and a clock (CLK) signal, and 13 bits of data bits and 2 bits are checked. It is assumed that it is composed of bits A and B and one parity bit P. When the check bits A and B are transmitted from the higher-level device 10, the check bits A and B are “0”,
It is assumed that B = “1” is fixed. In addition, the transmission path from the higher-level device 10 to the lower-level device 20 is a downstream transmission path 30,
A transmission line from the lower device 20 to the upper device 10 is referred to as an upstream transmission line 40.

(1). When both transmission lines 30 and 40 are normal:

[0011]. In the upper level device 10, when a transmission request is generated, the first check bit adding means 1 adds a check bit A = “0” and a check bit B = to the transmission data.
“1” is added and the result is transmitted to the downlink transmission line 30.

[0012]. When the lower device 20 receives the signal from the downlink transmission path 30, the second check bit detecting means 3 detects the check bit.

.. The second check bit detecting means 3 is
The detected check bit “0, 1” is sent to the check bit inverting means 4.

.. In the check bit inverting means 4, the second
The check bit from the check bit detecting means 3 is inverted. That is, "0,1" is changed to "1,0".

.. The check bit inverting means 4 sends the inverted check bits “1,0” to the second check bit adding means 5.

.. The second check bit adding means 5 is
The check bit inverted by the check bit inversion means 4 is added to the transmission data and sent to the upstream transmission line 40.

.. When the host device 10 receives the signal from the upstream transmission path 40, the first check bit detection means 2 detects the check bit, and since it is “1,0”, both the transmission paths 30 and 40 are normal. to decide.

(2). When the line disconnection occurs on the downlink transmission line 30:

.. In the upper level device 10, when a transmission request is generated, the first check bit adding means 1 adds a check bit A = “0” and a check bit B = to the transmission data.
“1” is added and the result is transmitted to the downlink transmission line 30.

[0020]. When the lower device 20 receives the signal from the downlink transmission path 30, the second check bit detecting means 3 detects the check bit. However, the downlink transmission line 30
The check bit detected due to the disconnection of the line is "0,0".

[0021]. The second check bit detecting means 3 is
The detected check bit “0,0” is sent to the check bit inverting means 4.

.. In the check bit inverting means 4, the second
The check bit from the check bit detecting means 3 is inverted. That is, "0,0" is changed to "1,1".

.. The check bit inverting means 4 sends the inverted check bits “1,1” to the second check bit adding means 5.

[0024]. The second check bit adding means 5 is
The check bit inverted by the check bit inversion means 4 is added to the transmission data and sent to the upstream transmission line 40.

[0025]. When the host device 10 receives the signal from the upstream transmission line 40, the first check bit detecting means 2 detects the check bit, and since it is “1,1”, it is determined that the downstream transmission line 30 is disconnected. To do.

(3). When the line is disconnected on the upstream transmission line 40:

[0027]. In the upper level device 10, when a transmission request is generated, the first check bit adding means 1 adds a check bit A = “0” and a check bit B = to the transmission data.
“1” is added and the result is transmitted to the downlink transmission line 30.

.. When the lower device 20 receives the signal from the downlink transmission path 30, the second check bit detecting means 3 detects the check bit.

.. The second check bit detecting means 3 is
The detected check bit “0, 1” is sent to the check bit inverting means 4.

.. In the check bit inverting means 4, the second
The check bit from the check bit detecting means 3 is inverted. That is, "0,1" is changed to "1,0".

.. The check bit inverting means 4 sends the inverted check bits “1,0” to the second check bit adding means 5.

.. The second check bit adding means 5 is
The check bit inverted by the check bit inversion means 4 is added to the transmission data and sent to the upstream transmission line 40.

.. When the host device 10 receives the signal from the upstream transmission path 40, the first check bit detecting means 2 detects the check bit. However, the upstream transmission line 40
The check bit detected due to the disconnection of the line is "0, 0". Therefore, in the first check bit detecting means 2, since the check bit is "0,0", it is judged that the upstream transmission line 40 is disconnected.

As described above, the first check bit detecting means 5 detects the three states of the line "normal", "downline transmission line disconnection", and "uplink transmission line line disconnection" in the host device. Check bit three states (“0, 1”,
It is possible to identify by "1,1", "0,0").

[0035]

Since the present invention is constructed and functions as described above, according to the present invention, it is possible to identify a line disconnection in a vertical transmission line without lowering the data transmission efficiency, which results in a failure. It is possible to provide an unprecedented excellent data transmission system that can significantly reduce the cause isolation time at the time of occurrence.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining a signal frame configuration of the present invention.

[Explanation of symbols]

 1: first check bit adding means 2: first check bit detecting means 3: second check bit detecting means 4: check bit inverting means 5: second check bit adding means 10: upper device 20: lower device 30: Downlink transmission line 40: Uplink transmission line

Claims (1)

[Claims] 1. A data transmission system comprising a higher-order device and a lower-order device for mutually transmitting and receiving data using a plurality of transmission paths, wherein the higher-order device adds a check bit to the transmission data. Means and a first check bit detection means for detecting the check bit of the received data and checking the state of each transmission line are provided together,
The lower device includes a second check bit detecting means for detecting a check bit of received data, a check bit inverting means for inverting the check bit detected by the second check bit detecting means, and a check bit inverting means. And a second check bit adding means for adding the check bit inverted to the transmission data.