JPH05235784A - Error correction coding circuit - Google Patents

Abstract

PURPOSE:To improve the error correction capability of a convolution code system comprising a block code and a convolution code. CONSTITUTION:This circuit is provided with a convolution coding decoding device 5 applying convolution decoding to output data from a convolution coder 3 and outputting also data reliability information representing how the output data are reliable, a comparator 7 comparing the data reliability information with an optional reference, a 3rd rearrangement device 8 rearranging again its output signal in the reverse rearrangement procedure to that of a 1st rearrangement device 2, and a reed Solomon decoder 9 applying reed Solomon decoding to data resulting from rearranging an output of the code decoder 5 with a 2nd rearrangement device 6 while using its output signal as error occurrence position information and the reliability information of the output data is outputted in the decoding of the convolution code and the information is used for erasure information for the reed Solomon decoding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction code circuit in a multiple code system in which a convolutional code and a Reed-Solomon code are combined.

[0002]

2. Description of the Related Art A conventional convolutional / Reed-Solomon double code system is shown in FIG. The conventional error correction coding circuit includes a Reed-Solomon encoder 1 that performs Reed-Solomon coding on a digital signal of input input data 21,
A first rearranger 2 that rearranges the output data of the Reed-Solomon encoder 1, a convolutional encoder 3 that further convolutionally encodes the output data of the first rearranger 2, and a convolutional encoding The output data of the convolutional code decoder 5 for inputting the output data of the convolutional coder 3 via an arbitrary transmission path 4 and the convolutional decoding for the convolutional decoding of the convolutional code decoder 5 and the output data of the convolutional code decoder 5 The second rearranger 6 and the second rearranger 6 which rearrange the rearrangement again according to the rearrangement procedure
Output data 2 after Reed-Solomon decoding of the output data of
2 and a Reed-Solomon decoder 9. In this example, since the convolutional decoder 5 does not output the erasure information (error position information), the Reed-Solomon decoder 9 performs a normal error correction operation.

[0003]

In the conventional error correction code circuit described above, since the position of the error bit is unknown in Reed-Solomon decoding, it is compared with the case where the position is known. Then, there was a problem that the error correction capability was halved.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an error correction code circuit having an improved error correction capability.

[0005]

In order to achieve the above object, an error correction circuit of the present invention comprises a Reed-Solomon encoder for encoding an input digital signal and a Reed-Solomon encoder. A first rearranger that rearranges output data, a convolutional encoder that further convolutionally encodes output data of the first rearranger, and output data of the convolutional encoder is transmitted arbitrarily. A convolutional code decoder that inputs via a path, convolutionally decodes it, and at the same time outputs data reliability information that indicates how likely the output data is.
A comparator that compares the data reliability information output from the convolutional code decoder with an arbitrary reference value, and a rearrangement procedure that reverses the output data output from the convolutional code decoder from the first rearranger. A second rearranger that rearranges the output signals of the comparator, a third rearranger that rearranges the output signals of the comparator in a rearrangement procedure reverse to that of the first rearranger, and the third rearranger. And a Reed-Solomon decoder for decoding the output data of the second rearranger using the output signal of the rearranger as error occurrence position information.

[0006]

According to the error correction code circuit having the above structure,
Since the Reed-Solomon code is used as the outer code and the convolutional code is used as the inner code, the reliability information of the output data is output when the convolutional code is decoded, and this can be used as the erasure information in the Reed-Solomon decoding.
This improves the error correction capability.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an error correction code circuit in a convolution / Reed-Solomon double code circuit of the present invention.

In the figure, 1 is input data 21 to be input.
Reed-Solomon encoder for reed-Solomon encoding the digital signal of 2 is a Reed-Solomon encoder 1
First rearranger for rearranging the output data of
Is a convolutional encoder for further convolutionally encoding the output data of the first rearranger 2, and 4 is the input data of the convolutional encoder 3 via an arbitrary transmission path 4, and at the same time convolutionally decodes it. , A convolutional code decoder that also outputs data reliability information indicating how likely the output data is.

Further, 7 is a comparator for comparing the data reliability information output from the convolutional code decoder 5 with an arbitrary reference value,
6 is a second rearranger for rearranging the output data output from the convolutional code decoder 5 by a rearrangement procedure reverse to that of the first rearranger 2, and 8 is an output signal of the comparator 7. , A third rearranger for rearranging again in the reverse rearrangement procedure of the first rearranger 2, and 9 for outputting the output signal of the third rearranger 8 as error occurrence position information. This is a Reed-Solomon decoder which outputs the output data 22 of the rearranger 6 by performing Reed-Solomon decoding.

Further, this embodiment will be described in detail together with its operation. It is now assumed that the convolutional code decoder 6 in the receiving system is a Viterbi decoder with a constraint length K = 7 and a coding rate of 1/2. The data input to the Viterbi decoder is converted into a metric (metric) for each state, and calculation with each path metric (cumulative metric) is performed. After this operation is performed on a plurality of input data, final output data is determined.

The value of the path metric associated with the final output data at this time is a large value when the transmission line quality is good, but becomes smaller as the line quality deteriorates. When an error due to line deterioration is output, this value becomes an extremely small value, which is the same level as when random data is input. Therefore, this value can be regarded as representing the reliability of the output data.

In this embodiment, this final path metric value is treated as the reliability information 51. Then, when this falls below a certain threshold value, the corresponding output data is regarded as “erased data”. This data loss information is given to the Reed-Solomon code decoder 8 as erasure information 52, and the data is decoded in the erasure correction mode.

On the other hand, one of the characteristics of the Viterbi decoder is the burstiness of output errors. In other words, when the error in the input data exceeds the correctable limit value,
The Viterbi decoder outputs burst-like errors. The burst length of the Viterbi decoder according to the present embodiment ranges from several tens to several hundreds of bits. Therefore, in order to correct this with a Reed-Solomon code which is an outer code, a measure for dispersing this burst error is necessary. Therefore, in the embodiment, the rearrangement circuit 2 is provided on the transmission side, and the rearrangement circuits 6 and 8 are provided on the reception side.

A characteristic of the Reed-Solomon code is that the error correction capability greatly differs when the position of error data is known and when it is unknown. As an example, if the block length is 255 symbols, of which 223 symbols are information symbols and 32 symbols are redundant symbols, there is a correction capability of 16 symbols when the error symbol position is unknown, but 32 symbols when known. Can be corrected. However, in the conventional example, since the information regarding the reliability of the output data cannot be obtained from the convolutional decoder, the error position cannot be specified. Therefore, the erasure correction as in the above example cannot be used.

In the embodiment, in order to eliminate such a defect of the conventional error correction code circuit, a read / write as an outer code is performed.
As a result of the system that can perform the erasure correction when decoding the Solomon code, the error correction capability can be improved.

[0016]

As described above, according to the error correction code circuit of the present invention, the function of outputting the data reliability information is added to the decoder side of the convolutional encoder which is the inner code, and the data error position is added. Is detected and used as erasure information in a Reed-Solomon decoder which is an outer code, there is an effect of further improving the error correction capability as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is a block diagram showing an error correction coding circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional error correction code circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Reed-Solomon encoder 2 1st rearranger 3 Convolutional encoder 4 Transmission path 5 Convolutional code decoder 6 2nd rearranger 7 Comparator 8 3rd rearranger 9 Reed-Solomon code decoder 21 Input data on sending side 22 Output data on receiving side 51 Data reliability information 52 Erasure information

Claims (1)

[Claims] 1. A Reed-Solomon encoder for Reed-Solomon encoding an input digital signal, a first rearranger for rearranging output data of the Reed-Solomon encoder, and the first rearranger. A convolutional encoder that further convolutionally encodes the output data of the rearranger of 1;
A convolutional code decoder for inputting output data of the convolutional encoder through an arbitrary transmission path, convolutionally decoding it, and also outputting data reliability information indicating how likely the output data is. , A comparator for comparing the data reliability information output from the convolutional code decoder with an arbitrary reference value, and an output data output from the convolutional code decoder in the reverse order of the first rearrangement circuit. A second rearranger that rearranges in a procedure, a third rearranger that rearranges the output signals of the comparator in a reverse rearrangement procedure to the first rearranger, and the third rearranger. And a Reed-Solomon decoder for performing Reed-Solomon decoding of the output data of the second rearranger using the output signal of the rearranger No. 3 as error occurrence position information. No. circuit.