JPH05235783A - Sequential decoder - Google Patents

Abstract

PURPOSE:To set a decoding delay suitable for the system design by making the capacity of a reception buffer and a decoding buffer variable. CONSTITUTION:A reception symbol string is stored in a reception buffer 11 of ring structure whose memory capacity is made variable. Then the string is fed to a state latch circuit 12 which extracts the symbol from the reception buffer 11 for each symbol and latches the symbol for a prescribed period. Furthermore, a function generator 14 generates an estimate code symbol based on the symbol string latched by the state latch circuit 12. A sequential decoding control circuit 15 implements input output control of the reception buffer 11 and a decoding buffer 13. Then an address control circuit 16 revises an apparent capacity of the reception buffer 11 and the decoding buffer 13. Thus, the decoding speed is revised to adjust an error rate by setting an address counter with a selector signal before decoding.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction decoding apparatus for automatically correcting an error generated in data due to transmission or storage of convolutionally encoded data, and more particularly to a received symbol string in symbol units. The present invention relates to a sequential decoder that restores an original information symbol sequence.

[0002]

2. Description of the Related Art Conventionally, the following has been performed to detect and correct a data transmission error.

Data to be transmitted is divided into a number of information symbols, convolutionally coded by an error correction encoder (hereinafter referred to as an encoder), and a code symbol in which redundant bits are added to the information symbol is transmitted. The transmitted code symbol is used as a received symbol and sequentially decoded by an error correction decoder (hereinafter referred to as a decoder) using the Fano algorithm.

The Fano algorithm was devised by American Fano (RMFano).
ction on Infomation Theory, IT-9 (1963) PP64−PP
74. Encoders and decoders are described, for example, in the article IEEE Tran by George David Forney, Jr. (American).
saction on Communications Technology, COM-19 (197
1) It can be realized by the circuit described in PP821-PP835.

FIG. 3 shows a basic configuration of a decoder adopting such a Fano algorithm. The decoder shown in FIG. 3 has a reception buffer 31, a state holding circuit 32, a decoding buffer 33, a function generator 34, a sequential decoding control circuit 35, and an address control circuit 36. In this decoder, the systematic code is used in order to easily obtain the estimated code symbol.

The received symbol string is input for each symbol from the input terminal 37 of the receive buffer 31 and is temporarily stored in the receive buffer 31. The successive decoding control circuit 35 gives a read signal to the reception buffer 31 as necessary, and the reception buffer 31 controls the reception symbol stored at the address designated by the address control circuit 36 in the state holding circuit 32 and the successive decoding control. Output to the circuit 35. The state holding circuit 32 holds a predetermined number of received symbols, and when a new received symbol is input from the receive buffer 31,
The new received symbol is held and the oldest received symbol is output to the decoding buffer 33. Function generator 34
Generates an estimated code symbol from the content of the received symbol sequence held in the state holding circuit 32 and outputs it to the successive decoding control circuit 35.

The successive decoding control circuit 35 calculates the likelihood between the input received symbol and the estimated code symbol, and adds the likelihood to the past cumulative likelihood, and the threshold that varies depending on the decoding state. Compare with the value. Sequential decoding control circuit 35
Determines that the past estimation is correct if the cumulative likelihood exceeds the threshold, and determines that the past estimation is incorrect if the threshold is divided.

When the past estimation is judged to be correct, the successive decoding control circuit 35 again reads the designated symbol from the reception buffer 31 and inputs it to the left end of the state holding circuit 32. At the same time, the state holding circuit 32 shifts the held symbol to the right and stores the protruding symbol in the location designated by the address control circuit 38 of the decoding buffer 33. Hereinafter, the same operation is repeated until the cumulative likelihood falls below the threshold value.

When it is determined that the past estimation is incorrect, the successive decoding control circuit 37 changes the symbol at the left end of the state holding circuit 32, that is, the received symbol read previously, as much as possible to obtain the cumulative likelihood. Exceeds the threshold. If the cumulative likelihood does not exceed the threshold even after performing such an operation, it is determined that the previous estimation is incorrect, and the symbol held in the state holding circuit 32 is shifted to the left. , The symbol stored in the location designated by the address control circuit 36 of the decoding buffer 33 is read and input to the right end of the state holding circuit 32 to reproduce the state one symbol before, and the leftmost symbol is changed as much as possible. , So that the cumulative likelihood exceeds the threshold. In this manner, a series of processes for obtaining the likelihood of the received symbol (symbol held at the left end of the state holding circuit) corresponding to the estimated code symbol from the function generator 34 is performed.

As described above, the conventional sequential decoder estimates the information symbol sequence which gives the code symbol closest to the received symbol sequence while performing the trial and error operation.

Finally, the received symbol is the received buffer 3
Every time the information symbol is stored in the location designated by the address control circuit 36, the estimated information symbol is read from the location designated by the address control circuit 36 of the decoding buffer 33 and output from the output terminal 38.

[0012]

Generally, since the fluctuation of the delay caused by the decoding is absorbed by the receiving buffer, the decoding delay always occurs for the symbols accumulated in the receiving buffer. In the conventional sequential decoder, the capacity of the receiving buffer is fixed, so that there are the following problems in designing the system.

That is, when it is desired to suppress the decoding delay even if the decoding error rate is a little worse, or when the circuit design has a large margin and can be used at a good C / N, the reception buffer has a small capacity. However, there is a problem that the delay becomes large because the receiving buffer is larger than necessary although it is sufficient. Further, although the decoding delay may be large, there is a problem that when the decoding error rate is desired to be improved, it cannot be performed because the capacity of the reception buffer is small.

[0014]

According to the present invention, there is provided a sequential decoder that restores an encoded received symbol sequence to the original information symbol sequence in symbol units, wherein the input received symbol sequence is sequentially A receiving buffer for storing and a state holding circuit for adding the symbol read from the receiving buffer to a holding symbol sequence and at the same time outputting the oldest symbol to form a new symbol sequence and holding the new symbol sequence A decoding buffer for storing the oldest symbol output from the state holding circuit, and a function generator for generating an estimated code symbol from the new symbol sequence,
Sequential decoding that controls the reception buffer, the state holding circuit, the decoding buffer, and the function generator, and restores an information symbol sequence based on the read symbols and the estimated code symbols according to a predetermined algorithm. In a sequential decoder having a control circuit and an address control circuit for designating addresses of the reception buffer and the decoding buffer based on an instruction from the sequential decoding control circuit, the address control circuit outputs a select signal to be input. Based on this, by changing the addressing ranges of the receiving buffer and the decoding buffer, the memory capacity of the receiving buffer and the decoding buffer is substantially changed, thereby obtaining a sequential decoder.

[0015]

The received symbol string is temporarily stored in the receiving buffer having a ring structure whose memory capacity can be changed. After that, it is taken out from the reception buffer for each symbol and sent out to the state holding circuit for holding for a certain period for each symbol. The function generator generates an estimated code symbol from the symbol string held by the state holding circuit. The sequential decoding control circuit obtains the likelihood of the estimated code symbol and the corresponding symbol read from the reception buffer, adds this likelihood to the past cumulative likelihood, and a threshold variable according to the decoding state. Comparison is made to determine whether the estimated information symbol sequence is correct. Depending on the result of the judgment, the successive decoding control circuit extracts the received symbol from the reception buffer again and transmits the symbol to the state holding circuit, and then performs the above operation or returns the state holding circuit to the past state one symbol before. Alternatively, either of the above operations is performed after holding the current state and changing the corresponding portion of the state holding circuit. Here, the successive decoding control circuit sends out the oldest symbol from the state holding circuit to the decoding buffer whose memory capacity can be changed each time a new symbol is input to the state holding circuit, and conversely causes the state holding circuit to output one symbol. When returning to the previous state, the input / output control of the reception buffer and the decoding buffer is performed so that the corresponding symbol is read from the decoding buffer. The address control circuit is a receive buffer,
When a new receive symbol is to be written to the symbol part of the receive buffer that is currently undergoing decoding, the buffer overflow signal is issued and the receive buffer is written to the receive buffer. The operation of discarding all accumulated data and restarting decoding again is performed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic configuration of a successive decoder according to an embodiment of the present invention is shown in FIG. The sequential decoder of the present embodiment also has the reception buffer 11, the state holding circuit 12, the decoding buffer 13, the function generator 14, the sequential decoding control circuit 15, and the address control circuit 16 as in the conventional case.

Further, the reception buffer 11 and the decoding buffer 1
3, and the address control circuit 16 is connected to the select signal input terminal 19 so that the select signal is input.

FIG. 2 is a diagram showing a method of controlling the count value of the address counter 20 which indicates a designated portion at the time of input / output of the reception buffer 11 and the decoding buffer 13 inside the address control circuit 16. For example, if the terminal a is selected by the selector 21, the address counter for the receiving buffer and the address counter for the decoding buffer are 0 to 63.
You can only count up to. If the terminal b is selected, the address counter can only count from 0 to 127. In this way, the address control circuit 16 can change the apparent capacity of the reception buffer 11 and the decoding buffer 13. Therefore, if the address counter is set by the selector signal before decoding, the decoding speed can be changed and the error rate can be adjusted.

Also in this embodiment, the decoding operation can be performed in the same manner as the conventional method. Note that, here, the systematic code is used in order to easily obtain the estimated code symbol.

The received symbol string is input from the input terminal 17 for each symbol, is temporarily stored in the reception buffer 11, and is stored in a designated portion of the address control circuit 16 when the successive decoding control circuit 15 requires it. The present symbol is read from the reception buffer 11 and input to the left end of the state holding circuit 12. The function generator 14 includes a state holding circuit 12
An estimated code symbol is generated from the contents of the above and is output to the successive decoding control circuit 15. The successive decoding control circuit 15 sends the corresponding received symbol to the address control circuit 16 and the receiving buffer 1.
The likelihood between two symbols is calculated, and the likelihood added to the past cumulative likelihood is compared with a threshold that varies depending on the decoding state. Sequential decoding control circuit 15
Determines that the past estimation is correct, the state holding circuit 1
The symbol string held by No. 2 is shifted to the right, and the protruding symbol is stored in the location designated by the address control circuit 16 of the decoding buffer 13. Then, the designated symbol is read again from the reception buffer 11 and input to the left end of the state holding circuit 12.

When the sequential decoding control circuit 15 determines that the past estimation is incorrect, it shifts the symbol string held by the state holding circuit 12 to the left and stores it in the location designated by the address control circuit 16. Stored symbols are read from the decoding buffer 13 and input to the right end of the state holding circuit 12 to reproduce the state of one symbol before, or the left end symbol of the state holding circuit 12 with the current state held. A series of processes for obtaining the likelihood of the received symbol corresponding to the estimated code symbol by changing it as much as possible is performed.

While performing the trial and error operation as described above, the information symbol sequence that gives the code symbol sequence closest to the received symbol sequence is estimated. Finally, every time the received symbol is stored in the location specified by the address control circuit 16 of the receive buffer 11, the estimated information symbol is
The data is read from the location designated by the address control circuit 16 of the decoding buffer 13 and output from the output terminal 18. When a new received symbol is to be written in the position of the symbol currently undergoing the decoding process in the reception buffer 11, the address control circuit 16 issues a buffer overflow signal, and the data stored in the reception buffer 11 is output. , And outputs a signal to the successive decoding control circuit 15 to restart the decoding again.

[0023]

As described above, according to the present invention, the capacity of the receiving buffer and the decoding buffer is made substantially variable.
Although the decoded bit error rate fluctuates somewhat, it has the result that the decoding delay suitable for the system design can be set.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a method of controlling the count value of an address counter inside the address control circuit 16 of FIG.

FIG. 3 is a block diagram of a conventional sequential decoder.

[Explanation of symbols]

 11 reception buffer 12 state holding circuit 13 decoding buffer 14 function generator 15 successive decoding control circuit 16 address control circuit 17 input terminal 18 output terminal 19 select signal input terminal 20 address counter 21 selector 31 reception buffer 32 state holding circuit 33 decoding buffer 34 Function generator 35 Successive decoding control circuit 36 Address control circuit 37 Input terminal 38 Output terminal

Claims (3)

[Claims] 1. A sequential decoder that restores an encoded received symbol sequence to an original information symbol sequence in symbol units, a receive buffer that sequentially stores the input received symbol sequence, and a receive buffer from the receive buffer. At the same time as adding the read symbol to the holding symbol sequence, the oldest symbol is output as a new symbol sequence, and a state holding circuit for holding the new symbol sequence and the state holding circuit While controlling the decoding buffer that stores the oldest symbol, the function generator that generates the estimated code symbol from the new symbol sequence, the reception buffer, the state holding circuit, the decoding buffer, and the function generator, Sequentially restoring an information symbol sequence based on the read symbols and the estimated code symbols according to a predetermined algorithm In a sequential decoder having a decoding control circuit and an address control circuit that specifies addresses of the reception buffer and the decoding buffer based on an instruction from the sequential decoding control circuit, the address control circuit inputs a select signal A sequential decoder characterized in that the memory capacities of the reception buffer and the decoding buffer are substantially changed by changing the addressing ranges of the reception buffer and the decoding buffer based on the above. 2. The sequential decoder according to claim 1, wherein the address control circuit has a ring-shaped memory configuration. 3. The sequential decoding according to claim 1, wherein the address control circuit erases all the reception symbols stored in the reception buffer when the reception buffer overflows. vessel.