JPH05235702A - Filter device - Google Patents

Abstract

PURPOSE:To make the entire group delay characteristic almost flat by setting a group delay characteristic of an analog filter and an IIR (infinite length impulse response) filter to be almost equal to each other. CONSTITUTION:An intermediate frequency signal from a band pass filter 6 is fed to multipliers 7,8 being components of an orthogonal detector, from which base band signals I,Q are obtained and they are fed respectively to A/D converters 13,14, in which the signals are converted into digital signals xi,yi, written and read under the control of a digital signal processor (DSP) 20 and the signals are processed by the DSP 20. That is, the digital signals xi,yi from the A/D converters 13,14 are written in dual port RAMs 15,16, the written signals are inverted timewise and read, the IIR filtering processing arithmetic operation is implemented and the result is inverted timewise and read, and demodulation processing is implemented. Then the group delay characteristic and the amplitude characteristic for the filtering processing of the band pass filter 6 and the IIR filter are set respectively almost identically.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a filter device.

[0002]

2. Description of the Related Art A time division multiple access digital communication method for wirelessly connecting a base station (fixed station) and a mobile station (car phone) is 900 MH.
Six reception slots are provided for each channel in the z band, and a reception signal of one slot in the z-band is received every 20 msec for 20 msec.
The number of transmission slots is provided, and the transmission signal of one of the slots is transmitted.

A conventional example of such a receiver for a mobile telephone of the digital communication system will be described with reference to FIG. The reception signal from the antenna 31 is a reception burst signal (quadrature phase-shift keyed (QPSK) audio signal of a certain reception slot) of 25
Bandpass filter 32 that passes 0 channels)
And the received signal is supplied to the mixer 34, and the local oscillation signal from the local oscillator 35 is supplied to the mixer 34.
To the bandpass filter 36 to obtain an intermediate frequency signal, which is supplied to a demodulator 37 such as a quadrature detector for demodulation.

FIG. 14 shows a communication system, which includes base stations BS1 and BS2, mobile stations MS1, MS2 and MS3 communicating with the base station BS1, and a mobile station MS4 communicating with the base station BS2. And the mobile station MS
1, MS2 and MS3 receive transmission signals (adjacent channel signals) transmitted from the base station BS1 and having different transmission frequencies, respectively, and the mobile station M
It is assumed that S4 receives a transmission signal from the base station BS2 having a transmission frequency different from the frequency of the transmission signal from the base station BS1. In this case, the mobile stations MS1 to MS4
The receiving device is assumed to have the configuration shown in FIG. The frequency spectrums of these transmission signals are shown in FIG.
5 shows.

The mobile station MS1 has a carrier frequency of 9
When trying to receive a transmission signal (desired signal) of 00 MHz, the pass frequency band of the band pass filter 32 of the receiving apparatus of FIG. 9 is selected to 875 MHz to 925 MHz, and the local oscillation frequency of the local oscillator 35 is selected to 970 MHz. , The intermediate frequency is 70 MHz. The band pass filter 36 is for attenuating the intermediate frequency signals of the adjacent channel signals.

By the way, when the received signal is a digitally modulated signal such as a QPSK modulated signal, it is strongly required that the amplitude characteristic of the bandpass filter 36 is steep and the group delay characteristic is flat within the band. It Figure 10
11 and 12 show the required specifications of the bandpass filter 36. FIG. 10 shows the amplitude characteristic and FIG. 11 shows the group delay, which are quite demanding. And
FIG. 12 and FIG. 13 respectively show the amplitude characteristic and the group delay characteristic when the bandpass filter 36 is configured by a Butterworth characteristic fourth-order LC filter. Both are far from the required specifications, but especially the group delay characteristic is It does not satisfy the specifications at all.

[0007]

By the way, when the bandpass filter 36 is composed of an LC filter and an active filter, if the group delay characteristic is made flat, a Bessel characteristic filter is used. The amplitude characteristic does not become steep even if is raised. Further, if the bandpass filter 36 is composed of a transversal filter using a SAW or a CCD, a sharp amplitude characteristic and a flat group delay characteristic can be obtained. It may not be possible because it is subject to restrictions. Furthermore, a FIR (finite length impulse response) filter is also a kind of transversal filter, and one that satisfies both of the above characteristics can be obtained, but the amount of calculation becomes enormous, which is not preferable.

In view of such a point, the present invention has a steep amplitude characteristic and a substantially flat group delay characteristic, and also has a high degree of freedom in designing the amplitude characteristic, so that a transversal filter is partially used. Despite this, an attempt is made to propose a filter device with a small calculation amount.

[0009]

According to a first aspect of the present invention, an analog filter 6, A / D converters 13 and 14 provided at a subsequent stage of the analog filter 6, and an A / D converter 1 thereof are provided.
Time reversing means 15, 16 provided at the latter stage of 3, 14
And the I provided in the latter stage of the time changing means 15 and 16.
An IR (infinite length impulse response) filter means 20 is provided, and the group delay characteristics and the amplitude characteristics of the analog filter 2 and the IIR filter means 20 are set to be substantially the same.

The second aspect of the present invention is the same as the first aspect of the present invention.
The second time inverting means 19 is provided after the IIR filter means 20.

[0011]

According to the present invention described above, the analog filter 6
By setting the group delay characteristics of the IIR filter 20 to be substantially the same, the group delay characteristics of the entire filter device become substantially flat. Therefore, the analog filters 6 and I
There is no need to flatten the individual group delay characteristics of the IR filter 20, and the amplitude characteristics may be designed so that the desired amplitude characteristics are obtained mainly by the analog filter 6. Therefore, the frequency of the clock signal of the A / D converters 13 and 14 can be low, its dynamic range can be low, and the number of quantization bits can be low.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A digital communication system of a time division multiple access system in which a base station (fixed station) and a mobile station (mobile telephone) are wirelessly connected to each other with reference to FIG. A detailed description will be given of an embodiment applied to the receiving device of the car telephone set. In this digital communication system,
Six reception slots are provided for each channel of the 900 MHz band, and the reception signal of one of the slots is set to 120
20 msec is received every msec, and 6 transmission slots are similarly provided for each channel, and the transmission signal of one of the slots is transmitted.

In the embodiment shown in FIG. 1, a case where a received signal having a carrier frequency of 900 MHz in a certain receiving slot (π / 4 shifted four-phase modulated burst signal) is received will be described as an example. The received signal from the antenna 1 has a pass band center frequency of 900 MHz and a pass band frequency of 875 MH
It is supplied to the high frequency amplifier 3 through the band pass filter 2 adjusted to have a frequency of z to 925 MHz. The reception signal from the high frequency amplifier 3 is supplied to the mixer 4, and after being mixed with the local oscillation signal from the local oscillator 5 whose oscillation frequency supplied to the mixer 4 is adjusted to 970 MHz,
The bandpass filter 6 having a passband center frequency of 70 MHz is supplied.

Intermediate frequency signal from bandpass filter 6
Is a quadrature detector (quasi-synchronous detector)
The carrier wave signal supplied to the multipliers 7 and 8 and the multiplier 7.
70 MHz carrier signal from the signal generator 9 and its carrier
After the wave signal is phase-shifted by 90 ° by the phase shifter 10,
A carrier signal with a phase of 90 ° supplied to the calculator 8 and
They are multiplied and demodulated in π / 4 shifted 4 phase,
Baseband signals I and Q are obtained respectively. This base
The sub-band signals I and Q have the 140 MHz component removed, respectively.
Through low-pass filters 11 and 12 to remove
It is supplied to the A / D converters 13 and 14 respectively and
1 MHz clock signal from the signal generator 17
For example, a parallel 8-bit digital sampler
Signal x _i, Y_iIs converted to.

These digital signals x _i and y _i are supplied to the dual port RAMs 15 and 16 and written by the write / read switching control signal and the address signal from the timing signal generator 17 which are supplied to the dual port RAMs 15 and 16, respectively. It is also read out, supplied to the RAM 19 through the bus, written and read out under the control of the digital signal processor (DSP) 20, and processed by the DSP 20. The ROM 18 stores a processing program by the DSP 20. Then, a digital audio signal is obtained as a demodulation output from the DSP 20, and the CPU 21
Is supplied to.

The bandpass filter 2 described above has the same characteristics as the bandpass filter 32 of the conventional example of FIG. 11, but the bandpass filter 6 has the amplitude of the bandpass filter 36 of the conventional example of FIG. Compared with the breaking characteristics,
Its amplitude cutoff characteristic is half, and the group delay characteristic is not required. The specifications of the amplitude characteristics of the bandpass filter 6 are shown in FIG.

Next, the firmware by the DSP 20
The signal processing by the DSP 20 will be described with reference to FIG.
To do. As shown in block 25, A / D converters 13, 1
Digital signal (sampling signal) s from 4_i= (X
_i, Y_i), That is, s₀, S ₂, S₃, …………
Write to Alport RAM15, 16 and reverse it in time
Then digital signal s_N, S_N-1Read as …………
Then, as shown in block 26, the IIR filter
And then, as shown in block 27,
Digital signal γ after filtering calculation_N, Γ
_N-1, ………… is written in RAM19 and it is reversed in time
Then digital signal γ₀, Γ₂, Γ₃Read as …………
After that, demodulation processing is performed as shown in block 28.
Incidentally, the processing by the block 27 may be omitted.

The above IIR filtering is represented by an equivalent circuit as shown in FIG. 4, and in this case IIR2.
It is the next filter. That is, the input signal X (z) from the input terminal 41 is supplied to the adder 42, which is added to the addition output supplied from the adder 52 to the adder 42, and the addition output W (z) is 1 It is supplied to the delay unit 46 for the clock period and also supplied to the coefficient multiplier 43 to be multiplied by the coefficient a and then supplied to the adder 44. The delay output of the delay device 46 is
Supplies to one clock cycle of delay unit 49 is supplied to a coefficient multiplier 47 and 48, respectively coefficients -b _1, a
After being multiplied by ₁ , they are supplied to adders 52 and 53, respectively. The delay output of the delay unit 49 is supplied to the coefficient multipliers 50 and 51 to be multiplied by the coefficients -b ₂ and a ₂ , respectively. The outputs of the coefficient multipliers 47 and 50 are supplied to the adder 52 and added,
The addition output is supplied to the adder 42. Coefficient multiplier 4
The outputs of 8 and 51 are supplied to the adder 53 and added. The outputs of the coefficient multiplier 43 and the adder 53 are supplied to the adder 44 and added, and the output signal Y (z) is output from the output terminal 45.

The amplitude characteristic of the bandpass filter 6 is represented by | H ₁
(F) |, its group delay characteristic is represented by τ ₁ (f), the amplitude characteristic of IIR filtering is represented by | H ₂ (f) |, and its group delay characteristic is represented by τ ₂ (f). The amplitude characteristic is | H (f) | = | H ₁ (f) | · | H ₂ (f) |, and the combined delay characteristic is τ (f) = τ ₁ (f) −τ ₂ (f) Become. Then, the absolute value of the amplitude characteristic of the bandpass filter 6 is set as shown in FIG. Then, when the bilinear transformation is used, the amplitude characteristic of the bandpass filter 6 and I
The amplitude characteristic and the group delay characteristic of IR filtering can be set to be substantially the same as shown in the following equations. | H (f) | ≈ | H ₁ (f) | ² ≈ | H ₂ (f) | ² τ (f) = τ ₁ (f) −τ ₂ (f) ≈0

The bandpass filter 6 is set to the Butterworth characteristic 2
FIGS. 5 and 6 show the amplitude characteristics a and b and the group delay characteristics a and b when the IIR filtering is composed of the Butterworth characteristic second-order IIR filter and the IIR filtering is composed, respectively. The amplitude characteristics and the combined delay characteristics are shown in FIGS. 7 and 8, respectively, and it can be seen that these combined characteristics sufficiently satisfy the specifications of the amplitude characteristics and the flat group delay characteristics of FIG.

[0021]

According to the present invention described above, the amplitude characteristic is steep, the group delay characteristic is substantially flat, the degree of freedom in designing the amplitude characteristic is high, and a transversal filter is partially used. Nevertheless, it is possible to obtain a filter device with a small amount of calculation. Further, since the analog filter can sufficiently limit the band, the frequency of the clock signal supplied to the A / D converter can be low, its dynamic range can be low, and its quantization bit number can be low.

[Brief description of drawings]

FIG. 1 is a block diagram showing a receiving device to which the present invention is applied.

FIG. 2 is a block diagram showing the firmware of the DSP of the embodiment.

FIG. 3 is a diagram showing specifications of amplitude characteristics of a bandpass filter according to an embodiment.

FIG. 4 is an equivalent circuit of the IIR filter means of the embodiment.

FIG. 5 is a curve diagram showing the amplitude characteristics of the bandpass filter and IIR filter means of the embodiment.

FIG. 6 is a curve diagram showing the group delay characteristics of the bandpass filter and IIR filter means of the embodiment.

FIG. 7 is a curve diagram showing a composite amplitude characteristic of the bandpass filter and IIR filter means of the embodiment.

FIG. 8 is a curve diagram showing a combined delay characteristic of the bandpass filter and the IIR filter means of the embodiment.

FIG. 9 is a block diagram showing a conventional receiving device.

FIG. 10 is a diagram showing specifications of amplitude characteristics of a conventional bandpass filter.

FIG. 11 is a diagram showing specifications of group delay characteristics of a conventional bandpass filter.

FIG. 12 is a curve diagram showing amplitude characteristics when a conventional bandpass filter is composed of a Butterworth fourth-order LC filter.

FIG. 13 is a curve diagram showing a group delay characteristic when a conventional bandpass filter is composed of a Butterworth fourth-order LC filter.

FIG. 14 is a diagram showing a communication system for explaining a conventional example.

FIG. 15 is a curve diagram showing a frequency spectrum of a received signal for explaining a conventional example.

[Explanation of symbols]

 6 Analog Filter 13 A / D Converter 14 A / D Converter 15 Dual Port RAM 16 Dual Port RAM 19 RAM 20 DSP

Claims (2)

[Claims] 1. An analog filter, an A / D converter provided after the analog filter, a first time inverting means provided after the A / D converter, and a time changing means. A filter device having IIR filter means provided in a subsequent stage, wherein the group delay characteristics and the amplitude characteristics of the analog filter and the IIR filter means are set to substantially the same characteristics, respectively. 2. The filter device according to claim 1, further comprising a second time reversal unit provided after the IIR filter unit.