JPH05234931A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method wherein contact resistance is reduced, regarding the formation of contact between a diffusion layer and a wiring layer of the substrate surface of a semiconductor device. CONSTITUTION:Impurities are implanted in a diffusion layer 2 at the bottom of a contact hole 4. After a thin oxide film 7 is formed on at least the diffusion layer 2, the impurities are activated by heat treatment. Thereby the carrier density of the diffusion layer 2 surface is increased, and then a wiring layer is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a fine contact in a semiconductor device, and more particularly to a method of reducing the contact resistance thereof.

[0002]

2. Description of the Related Art The progress and development of semiconductor devices are remarkable. Taking a semiconductor memory device as an example, 1 Mb, 4 Mb and 16 Mb.
b, 64Mb and its large scale never stop, and there is no limit to the miniaturization of design rules.

When the design rule is miniaturized, various problems naturally occur when forming a MOS FET or a bipolar device. In particular, in the contact connecting the semiconductor substrate and the wiring layer formed of metal metal, the problem is remarkable.

This is a problem of disconnection at the contact portion of the metal metal wiring, and contact resistance at the contact portion between the semiconductor substrate and the metal metal wiring (hereinafter referred to as contact resistance).
Is a problem. Each will be briefly described below.

As described above, as the diameter of the contact hole (hereinafter referred to as the contact diameter) is made finer by making the design rule finer, the thickness of the insulating film for opening the contact is determined by the stray capacitance between the wiring layer and the substrate. The contact depth with respect to the contact diameter, that is, the aspect ratio, increases because the thickness cannot be reduced for the purpose of reducing the power consumption and preventing the parasitic MOS transistor formed by the insulating film, and the probability of disconnection when metal wiring is applied to this contact. Is to be large.

Further, the above is a problem that the contact resistance value generally depends on the size of the contact diameter, and the resistance increases as the contact diameter decreases.

As a measure for avoiding these problems, a contact embedding technique has been developed, and a contact layer impurity implantation technique (referred to as contact implantation) has been developed.

The conventional contact forming method will be described below in order with reference to FIGS.

3A, a semiconductor element (only one P-type diffusion layer 102 is shown here) is formed on a semiconductor substrate 101, and an insulating film 103 is formed on the surface thereof.
(b) The contact hole 104 is opened using a well-known photolithography (hereinafter referred to as photolithography) / etching technique.

Then, as shown in FIG. 3 (c), boron is ion-implanted (105) to form a compensation diffusion layer for lowering the contact resistance.
A high-concentration boron implantation layer 106 is automatically formed using the insulating film 103 as a mask.

FIG. 3D: Activated boron is activated. Since the layer 106 injected at this time has a high concentration, the P-type diffusion layer 102 spreads deep only in the contact region (bottom of the contact hole 104) (107). Then, W (tungsten) 108 is sputter-deposited on the entire surface.

FIG. 3 (e) W is left only in the contact opening 104 by the etch back technique (109), and metal such as AL for forming the wiring layer is sputter-deposited on the entire surface (not shown). The wiring layer 110 is formed by the photolithography / etching technique.

[0013]

However, with the above-mentioned method, the problem of disconnection of the metal-metal wiring layer at the contact portion can be avoided, but the problem of increased contact resistance is adopted by the use of contact implantation technology. Although it is better than the case where it is not, the resistance value does not become satisfactory, and especially when the contact diameter is 1 μm or less, the rate at which this increase in resistance value affects the device performance is at a level that cannot be ignored. Was there. As an example of this, FIG. 4 shows the relationship between the contact diameter and the contact resistance value obtained by experiments by the inventors. The diffusion layer is P-type, and as can be seen from the figure, the resistance value is 100 to 120 Ω when the contact diameter is 0.08 μm.

According to the present invention, when the design rules described above are miniaturized, in order to avoid the problem that the contact resistance is increased and as a result the performance of the device is hindered from being hindered, in forming the contact, after ion implantation into the contact region. By coating a thin oxide film and performing activation treatment, the impurity carrier concentration on the surface is increased compared to the conventional one, and the diffusion layer having the high concentration carrier is brought into contact with the wiring metal or burying material. Thus, it is intended to form a contact having a low resistance contact resistance.

[0015]

According to the present invention, in order to obtain the above-mentioned low resistance contact resistance, in forming a contact, (1) impurities are ion-implanted into the contact portion, and then (2) a thin oxide film is coated. Then, (3) activation treatment is performed to increase the carrier concentration on the surface of the diffusion layer.

In removing the coated thin oxide film, (1) a sidewall is formed along the wall of the contact hole using a material having an etching selection ratio to the thin oxide film, and (2) by self-alignment. The bottom oxide film can be removed.

[0017]

As described above, according to the present invention, the carrier concentration on the surface of the contact portion diffusion layer is improved.
A contact having a low resistance can be formed in forming a contact in a submicron region of μm or less.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of an embodiment of the present invention is shown in FIGS.
And will be described in the order of FIGS.

FIG. 1 (a) First, a semiconductor substrate 1 as in the prior art
A semiconductor element (only one P-type diffusion layer 2 is shown here) is formed on the upper surface, and a 8000 Å CVD film (chemical vapor deposition) such as 8000 Å is formed on the surface. Then, the insulating film 3 is formed by the method (film by the method).

1 (b) A contact hole 4 having a width of 0.5 μm (W _{1 in the} drawing) is formed by using a well-known photolithography / etching technique. At this time, the thickness of the insulating film 3 is 8000.
Å and the contact hole 4 has an aspect ratio of 8000Å /
0.5 μm = 1.6.

FIG. 1 (c) Next, for the purpose of forming a compensation diffusion layer for lowering the contact resistance, boron (B ⁺ ) as an impurity is ion-implanted (5) under the conditions of 40 KeV and 5 × 10 ¹⁵ . A high-concentration boron implantation layer 6 is automatically formed by self-alignment using the insulating film 3 as a mask only in the opened contact region.

Next, as shown in FIG. 1 (d), 200 Å of ozone TEOS (Tetra EthylthoS
Ilicate) The oxide film 7 is grown.

By the way, the conventional CVD oxide film does not have sufficient step coverage. In other words, due to the geometric shadowing effect, the step of the contact opening, that is, FIG.
It was not possible to form a thin (100 to 500Å) oxide film having a uniform thickness on the insulating film 3 of (d) and on the bottom and side surfaces of the contact hole 4. Therefore, if an oxide film as thin as 200Å is to be formed, the contact opening 4
However, there were problems such as an overhang and almost no growth on the side surface of the contact hole 4. On the other hand, the above-mentioned ozone TEOS method for growing an insulating film using an organosilicon compound having a high surface mobility, which is a kind of CVD method, has a local solid angle as the mean free path of surface migration increases. Averaging is promoted and step coverage and conformality are improved. Therefore, as shown in FIG. 1 (d), the top surface, side surface, and bottom surface of the step like the contact hole 4 have a uniform oxide film 7 (C
(Also referred to as a VD film) can be grown.

Next, FIG. 1 (e) is performed to activate the implanted boron under the N ₂ atmosphere at 850 ° C. for 20 minutes. At this time, the carrier concentration on the surface of the substrate 1 is shown in FIG.
Further, since the boron injected at this time has a high concentration, the P-type diffusion layer 2 extends deeply (8) only in the contact opening portion.

As shown in FIG. 5, this thin oxide film 7 is
The carrier profile of boron on the substrate surface is about twice that of the case without it. The carrier concentration on the surface of the ion-implanted semiconductor substrate is
The reason why the difference is caused by nothing is not well understood, but the inventors have found that the amount of outdiffusion of impurities from the surface of a semiconductor substrate which has been ion-implanted at a high concentration and amorphized is larger than expected, It is assumed that the activation rate will change if an oxide film is present.

Although not shown, the thin oxide film 7 in this region is removed by etching by a well-known photolithography technique using a mask having a diameter larger than the contact diameter W ₁ by one.
By forming a wiring layer by embedding W9 in the contact region as shown in the conventional example, that is, as shown in FIGS.
It is possible to realize a contact resistance lower than the conventional one. Further, in the etching of the thin oxide film 7, if HF-based wet etching having a high selection ratio with the semiconductor substrate is used, a portion having a high carrier profile on the surface of the semiconductor substrate 1 is not etched, so that the contact resistance is lowered. The effect is further improved.

However, in this method, when the thin oxide film 7 is removed by etching, some overetching must be performed in order to absorb variations in the oxide film 7 on the semiconductor substrate 1. At this time, as shown in FIG. It is undeniable that the contact diameter indicated by W ₁ in FIG. 4) becomes slightly larger because the side of the insulating film 3 is also etched.

Therefore, in the present embodiment, FIG. 1 and FIG.
The method of avoiding this problem is shown in (i).

That is, FIG. 1 (f) In other words, after the boron activation treatment, a material having an etching selection ratio with respect to the thin oxide film 7 such as polysilicon may be used, but here, W (tungsten) 9 is entirely coated. ..

Next, as shown in FIG. 2 (g), the sidewall 10 of W only on the wall of the contact hole 4 is formed by the well-known RIE technique. The aperture width at this time is W ₂ .

FIG. 2 (h) The substrate 1 is placed in an HF-based wet etching solution, and the thin oxide film 7 at the bottom of the contact is etched and removed in a self-aligned manner by using the W sidewall 10 as a mask to obtain an opening 11. Opening width W at this time
₃ is controlled by the etching conditions, but since contact resistance generally depends on the contact diameter,
It is desirable close to as large as possible W ₁ than W _2. At this time, the thin oxide film 7 covering the insulating film 3 is also removed by etching.

FIG. 2 (i). Then, W is grown on the entire surface of the substrate by the CVD method (not shown). At this time CVD
The thin oxide film 7 shown in FIG.
There can also W is grown in a gap between W ₁₀ and the substrate 1 can after it has been etched away.

Further, as in the conventional example, W is left only in the contact openings by the etch back technique (14), and a metal such as AL for forming a wiring layer is sputter-deposited on the entire surface (not shown). The wiring layer 15 is formed by a well-known photolithography / etching technique.

It should be noted that the number of masks does not particularly increase as compared with the conventional example through the above steps.

In this embodiment, the technique of burying W in the contact region has been described as an example, but the present invention for lowering the resistance of the contact does not necessarily require the use of the burying technique. The thin oxide film 7 is removed by etching by adding a mask only to the contact region, which has been described with reference to FIG. 1D, and then a normal wiring metal is sputter-deposited to form a wiring layer by using a well-known photolithography / etching technique. However, low resistance can be realized. Here, Table 1 shows the results of evaluation by the inventors of the present invention regarding the contact resistance of the contact prototyped by the method of this embodiment using the Kelvin pattern. As is clear from Table 1, the contact resistance, which was 100 to 120Ω in the past due to P ⁺ diffusion when the contact diameter was 0.8 μm, could be reduced to 20Ω, which is about 1/5 of that in the conventional case. The results are shown in FIG. 4 in comparison with the conventional example.

[0036]

[Table 1]

[0037]

As described above, according to the present invention,
Since the carrier concentration on the surface of the diffusion layer is improved, it is possible to form a contact having a low resistance even when forming a contact in the submicron region of 1.0 μm or less.
Therefore, a high performance device can be obtained.

[Brief description of drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is a second embodiment of the present invention.

FIG. 3 Conventional example

[Figure 4] Relationship between contact diameter and contact resistance

FIG. 5: Carrier concentration on the substrate surface

[Explanation of symbols]

 1 Semiconductor Substrate 2 Diffusion Layer 3 Insulating Film 4 Contact Hole 6 Boron Injection Layer 7 Oxide Film 9 W

Claims (3)

[Claims] 1. A step of: (a) forming a first insulating film on a semiconductor substrate and forming a contact hole in a part of the insulating film; (b) implanting impurities into the substrate surface at the bottom of the contact hole. (C) forming a second insulating film over the contact bottom surface, side surface and entire surface of the first insulating film, (d) performing a process for activating the impurities, (e) A method of manufacturing a semiconductor device, comprising: a step of removing at least the second insulating film in the contact hole to form a wiring layer in the contact hole; 2. A step of: (a) forming a first insulating film on a semiconductor substrate and forming a contact hole in a part of the insulating film; (b) implanting impurities into the substrate surface at the bottom of the contact hole. (C) forming a second insulating film over the contact bottom surface, side surface and entire surface of the first insulating film, (d) performing a process for activating the impurities, (e) A step of forming a sidewall with a conductive material on the side wall of the contact hole in which the second insulating film is formed, (f) using the sidewall as a mask, at least the second insulating film at the bottom of the contact hole A method of manufacturing a semiconductor device, comprising the steps of: (g) filling the contact hole with a conductive material to form a wiring layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film is an oxide film formed by an ozone TEOS method.