JPH05234006A - Floppy disk driving device - Google Patents

Abstract

PURPOSE:To correct a peak shift and to compensate the temperature characteristic of a medium. CONSTITUTION:This floppy disk 10 is used for writing data from a host computer 100 in the floppy disk and sending data read from the floppy disk to the host computer 100. It is provided with a write compensation circuit 12 for compensating the peak shift between the data written in the floppy disk and the data read from the floppy disk and further, the write compensation amount of this write compensation circuit 12 is controlled by a thermister RT and a condensor C.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floppy disk drive device which is used, for example, in a so-called floppy disk device and which writes data from a host computer to a floppy disk and sends the data read from the floppy disk to the host computer. It is a thing.

[0002]

[Prior Art]

A schematic configuration of a conventional floppy disk device is shown in FIG. In FIG. 5, the floppy disk device is simply a host computer 100.
, A floppy disk drive (floppy disk drive device) 110, and a head 111. Further, the host computer 100 of the floppy disk device includes a floppy disk including an encoder 103 that encodes write data to be recorded on the floppy disk 112 and a decoder 104 that decodes a read serial data string RD read from the floppy disk 112. It has a controller 102 and a CPU (central processing unit) 101 that controls each unit and processes write and read data. In this floppy disk device, the write serial data string WD from the encoder 103 of the floppy disk controller 102 is sent to the head 111 via the floppy disk drive 110, and is written in the floppy disk 112. Further, the read serial data string RD read from the floppy disk 112 by the head 111 via the floppy disk drive 110 is the floppy disk controller 10 described above.
The second CPU 104 is decoded by the second decoder 104.
Sent to 1.

Heretofore, when writing data to a floppy disk by the above-mentioned floppy disk device, for example, an FM (Frequency Modulati) is used.
on) recording method and MFM (Modified Frequency Modulat)
ion) recording method is generally used.

In the above-mentioned FM recording method, the data transfer rate of the serial data string recorded / reproduced on / from the floppy disk is, for example, 250 kbps, and the pulse intervals of the serial data string are of two types, 2 μs and 4 μs. There is. In the MFM recording method, the data transfer rate of the serial data string recorded / reproduced on / from the floppy disk is, for example, 500 kbps.
Then, each pulse interval of the serial data string is 2 μs, 3
There are three types, μs and 4 μs.

By the way, in recent years, it has been proposed to record data on the floppy disk at a higher density and a higher transfer rate. For example, in the MFM recording method, recording / recording on the floppy disk is performed.
The data transfer rate of the reproduced serial data string is 1 Mb
made in ps. In this case, there are three types of pulse intervals of the serial data string, 1 μs, 1.5 μs, and 2 μs.

[0007]

However, it is attempted to record / reproduce on / from a floppy disk at a high density and a high transfer rate as described above by using the head (head having a low resolution) of the conventional floppy disk device. Then, depending on the pattern of the serial data pulse train, so-called peak shift occurs, which causes a problem that an error is likely to occur during reading. That is, for example, as shown in FIG. 6, the pulse interval of, for example, 1 μs of the write serial data string WD (A in FIG. 6) is equal to the read serial data string RD.
In (B of FIG. 6), there occurs a problem of peak shift to a pulse interval of 1.2 μs, for example.

As shown in FIG. 7, when writing a write pulse WP consisting of two pulses at intervals of, for example, x μs to a floppy disk, the magnetization of the floppy disk is inverted according to the write pulse WP. It is considered that the isolated waveform is recorded in the opposite polarity by the write signal MR, and that when the floppy disk is played back, the isolated waveform interferes with each other and the composite waveform re shown by the solid line in the figure becomes the playback output. At this time, the position of the peak of the reproduction output deviates from the actually written position as indicated by the waveform im shown by the dotted line in the figure, and thus the reproduction pulse RP to be reproduced is displaced. .. This is called peak shift. Further, this peak shift is advanced peak shift ps _T and delayed peak shift ps
There is _D.

Further, the maximum value of the peak shift is, for example, as shown in FIG. 8, when a pulse group having a smaller pulse interval y among three types of pulse intervals is sandwiched by a larger pulse interval Y. Occurs in. For example, the data transfer rate is 1 Mbps, and the pulse intervals are 1 μs and 1.5.
In the case of three types of serial data strings of μs and 2 μs, the maximum peak shift occurs when a pulse interval group of y = 1 μs as the pulse interval y is sandwiched by pulse intervals of Y = 2 μs as the pulse interval Y. Will occur. In FIG. 8, the same reference numerals as those in FIG. 7 are attached, and detailed description of each waveform is omitted.

Here, in the conventional floppy disk device, a peak shift compensating circuit for correcting the peak shift is provided in the floppy disk controller, and the peak shift compensating circuit predicts the pattern of the serial data pulse train. There are also those which are adapted to record on a floppy disk after compensating for the peak shift. That is, for example, as shown in FIG. 9, by performing peak shift correction on the pulse interval of the write serial data string WD (A in FIG. 9) to a pulse interval of 0.8 μs, for example, the read serial data string RD (FIG. 9). B)
Then, for example, data with a normal pulse interval of 1 μs is obtained.

However, when the conventional floppy disk drive as shown in FIG. 5 is manufactured, the floppy disk drive 110, which is separately manufactured, is usually mounted in the floppy disk drive. Disk device host computer 100 side (floppy disk controller 102 side)
Then, the resolution of the head 111 on the side of the floppy disk drive 110 cannot be managed. Therefore, the floppy disk controller 100 cannot judge whether or not the peak shift compensation should be applied to the serial data pulse train, and cannot set the optimum compensation amount, for example.

Further, in recent years, for example, barium ferrite (B) has been used as a magnetic material for high density floppy disks.
A medium using aFe) or the like is used.

However, this magnetic material has a drawback that the temperature gradient of resolution is large as shown by the temperature characteristic curve Ta shown by the dotted line in FIG. That is, there is a drawback that the peak shift amount becomes large in a low temperature region. Therefore, the conventional floppy disk drive device must be designed and manufactured in advance in consideration of the deterioration due to the temperature characteristic of the medium as a margin, which hinders the improvement of the productivity of the floppy disk drive device and the head.

Therefore, the present invention has been proposed in view of the above-mentioned circumstances, and it is possible to effectively perform peak shift compensation for a serial data string recorded on a floppy disk, and at the same time, perform media compensation. It is an object of the present invention to provide a floppy disk drive device capable of compensating for the drawback of the temperature characteristics of the above.

[0015]

DISCLOSURE OF THE INVENTION A floppy disk drive device of the present invention is proposed in order to achieve the above-mentioned object, and is a floppy disk drive device for writing / reading data to / from a floppy disk. The pulse relationship determining means for determining the relationship between the pulse of interest in the serial data string written to the floppy disk and the pulses before and after the pulse of interest and the pulse of interest for a predetermined time from 0 to The delay means for outputting each delay pulse delayed by n times and the selection means for selecting each delay pulse output of the delay means according to the judgment result of the pulse relation judging means are written on the floppy disk. For the serial data string, the serial data string written to the floppy disk and the floppy disk It is obtained by such a built-in write compensation circuit for compensating the difference between the serial data sequences read from the disk.

The floppy disk drive device of the present invention has a temperature characteristic compensating means for compensating the temperature characteristic of the floppy disk, and the temperature characteristic compensating means controls the write compensation amount in the write compensating circuit. I also try to do it.

Here, it is assumed that the pulse relationship determining means of the write compensation circuit determines the magnitude relationship of the pulse intervals between the pulse of interest in the serial data string and the pulses before and after the pulse of interest. be able to.

Further, the pulse relation judging means of the write compensating circuit may judge whether or not the pulse before and after the pulse of interest in the serial data string is at a predetermined position.

[0019]

According to the floppy disk drive device of the present invention, the compatibility of the floppy disk drive device viewed from the floppy disk controller and the media (floppy disk) viewed from the floppy disk drive device are improved by incorporating the write compensation circuit. It becomes possible to compensate for the peak shift while ensuring compatibility.

Further, since the temperature characteristic compensating means for compensating the temperature characteristic of the floppy disk is provided and the writing compensation amount in the writing compensation circuit is controlled by this means, the temperature characteristic of the medium resolution is compensated. can do.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the floppy disk drive apparatus of this embodiment writes data (WD) from the host computer 100 to a floppy disk (not shown) and reads the data read from the floppy disk. A floppy disk drive device (10) for sending to a host computer (100), and a pulse relation judging means for judging a relation between a pulse of interest and a pulse before and after the pulse of interest in a serial data string written to the floppy disk. A delay means for outputting each delay pulse obtained by delaying the pulse of interest by 0 to n times a predetermined time; and a selection means for selecting each delay pulse output of the delay means according to the determination result of the pulse relation determining means. Serial that has and is written to the floppy disk The write compensation circuit 12 shown in FIG. 2, which will be described later, is provided for compensating the difference between the serial data sequence written to the floppy disk and the serial data sequence read from the floppy disk for the data sequence. It was done like this.

In FIG. 1, the host computer 1
00 and the head 111 are the same as those in FIG. 5 described above, and only the write serial data string WD is shown in the example of FIG. 1 to simplify the description. That is, the write serial data string WD from the host computer 100 is
It is sent to the control logic circuit 11 of the floppy disk drive device 10. The control logic circuit 11 performs processing according to the specifications of the interface with the host computer 100. The output of the control logic circuit 11 is supplied to the write compensation circuit 12. The serial data string that has been subjected to peak shift correction as described later in the write compensation circuit 12 is read / read.
It is sent to the writing circuit 13. The read / write circuit 13 generates a current according to the supplied serial data string, and this current becomes a drive current for writing to the head 111.
The read / write circuit 13 also converts the read current from the head 111 into a data string when reading the floppy disk.

Here, as shown in FIG. 2, the write compensating circuit 12 has a serial data string written on a recording medium such as a so-called floppy disk and a serial data string written on the floppy disk and a serial data string written on the floppy disk. A write compensating circuit for compensating in the opposite direction of the peak shift generated between the serial data string read from the floppy disk and the peak shift amount, which is supplied through an input terminal 1. Pulse relationship determining means for determining the relationship between the pulse of interest in the serial data string WD written to the floppy disk and the pulses before and after the pulse of interest, and the pulse of interest is 0 to n for a predetermined time. As delay means for outputting each delayed pulse delayed by a multiple (n is an integer, n = 2 in this embodiment) The delay circuits 5, 6 and 6 and a selection switch 8 for selecting each delayed pulse output of the delay circuits 5, 6 and 7 according to the determination result of the pulse relation determination means (output of the comparison circuit 4). It will be.

Further, the pulse relation judging means judges the magnitude relation of the pulse intervals between the pulse of interest and the pulses before and after the pulse of interest in the serial data string from the input terminal 1. For example, the pulse interval measuring circuit 2 for measuring the interval between each pulse of the serial data string, and the pulse before and after any pulse of interest among the pulse interval values measured by the pulse interval measuring circuit 2 are concerned. A shift register 3 for storing the pulse interval value with the pulse, and the shift register 3
Comparison circuit 4 for comparing the magnitude of two pulse interval values from
Can consist of and.

In this embodiment, the input terminal 1 has a data transfer rate of 1 Mb according to the MFM recording method.
ps, 3 for each pulse interval of 1 μs, 1.5 μs, 2 μs
Suppose a type of serial data string is supplied.

In FIG. 2, the write serial data string via the input terminal 1 is supplied to the pulse interval measuring circuit 2. The pulse interval measuring circuit 2 measures the pulse interval of each pulse of the serial data string by counting the reference clock, for example. The pulse interval value (count value) is sent to the shift register 3.

The shift register 3 stores two pulse interval values supplied from the pulse interval measuring circuit 2. In other words, the shift register 3 concerned
In, the value of the pulse interval between the above-mentioned arbitrary pulse of interest and the pulses before and after it is stored. The pulse interval values stored in the shift register 3 are sent to the comparison circuit 4, respectively.

The comparison circuit 4 compares the magnitudes of the two pulse interval values (count values) supplied from the shift register 3 and outputs the comparison result as a selection control signal for the selection switch 8 in the subsequent stage.

On the other hand, the serial data string via the input terminal 1 is also sent to the delay circuits 5, 6, 7. The delay circuit 5 delays each pulse of the serial data string by a time (delay amount β) corresponding to the delay amount in the pulse interval measuring circuit 2, shift register 3, and comparison circuit 4. The delay circuit 6 delays each pulse of the serial data string by a time (delay amount α) corresponding to the delay amount β and a predetermined time (delay amount β +
α). The delay circuit 7 delays each pulse of the serial data string (delay amount β + 2α) by twice the delay amount β and a time (delay amount α) corresponding to a predetermined time (delay amount 2α). is there. In other words, each of the delay circuits 5, 6 and 7 delays the delay amount β, and the delay circuit 5 delays the delay amount α corresponding to the predetermined time by 0 times (only the delay amount β). The delay circuit 6 delays the delay amount α by 1 time (delay amount β + α), and the delay circuit 7 delays the delay amount α by 2 times (delay amount β + 2α).

In this embodiment, the delay amount α
Is about 0.08 for 1 μs, for example. In the case of a 4M floppy disk, the delay amount β is set to be, for example, more than 2 μs.

The delay pulses from the delay circuits 5, 6 and 7 are sent to the corresponding selected terminals a, b and c of the selection switch 8. The selection switch 8 selects each of the selected terminals a, b, c based on the output (selection control signal) of the comparison circuit 4.

More specifically, in the selection switch 8, the comparison result of the comparison circuit 4 indicates that, for example, one of the pulse intervals of the pulse of interest and the pulses before and after it is 1 μs and the other is 1.5μs or 2μs
If it indicates that the pulse interval is set to, the selection process is performed to select the output of the delay circuit in which the pulse of interest is shifted to the interval side of 1 μs by a certain amount. For example, if the other one has a pulse interval of 1.5 μs, the selection switch 8 selects the output of the delay circuit 6, and if the other one has a pulse interval of 2 μs, the selection switch 8 delays the delay. Select the output of circuit 7. If the other one also has a pulse interval of 1 μs, the output of the delay circuit 5 is selected.

That is, the delay amounts α and 2α in the delay circuits 6 and 7 become the peak shift correction amounts, and are selected by the selection switch 8 in accordance with the pulse interval between the pulse of interest and the pulses before and after it. The above delay circuits 6 and 7
Output becomes a serial data string with peak shift correction. In addition, both the above-mentioned pulse interval and the other are 1 μm.
If the pulse interval is s, there is no need for peak shift correction, so the output of the delay circuit 5 is used as output data. The output of the selection switch 8 becomes the output of the writing correction circuit of this embodiment, and is output from the output terminal 9.

Further, the write compensating circuit 12 of the present embodiment can be configured as shown in FIG. The above-described configuration of FIG. 2 uses a counter (pulse interval measurement circuit 2) for pulse interval comparison, but in the example of FIG. 3, the delay circuit 2 of 1 μs and 2 μs is used for the pulse interval comparison.
1 and 22 are used. In FIG. 3, the same components as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

That is, in the configuration of FIG. 3, a 1 μs delay circuit 21 and a 2 μs delay circuit 22 and a determination circuit 20 are provided as the pulse relationship determination means, and the pulse relationship determination means is used to determine the internal serial data string. It is determined whether or not the pulses before and after the above-mentioned pulse of interest are at a predetermined position.

More specifically, the serial data string via the input terminal 1 is directly sent to the determination circuit 20, and each pulse of the serial data string is delayed by 1 μs and delayed by 2 μs. 21 and is sent to the determination circuit 20. The output of the delay circuit 21 which delays by 1 μs is sent to each of the delay circuits 5, 6 and 7. In the determination circuit 20, for example, one position of a pulse before and after the pulse of interest is a position having a pulse interval of 1 μs with respect to the pulse of interest, and the other position is a position having a pulse interval of 1.5 μs or 2 μs. In this case, the output of the delay circuits 6 and 7 in which the pulse of interest is shifted to the interval side of 1 μs by a certain amount (peak-shift compensated) is selected by the selection switch 8.

That is, in the configuration of FIG. 3, the determination circuit 20 has, for example, the other position of 1.5 μs.
If it is at the pulse interval position of
Then, the output of the delay circuit 6 is selected, and if the other position is a position with a pulse interval of 2 μs, the output of the delay circuit 7 is selected by the selection switch 8. When the other position is also a position with a pulse interval of 1 μs, the output of the delay circuit 5 is selected by the selection switch 8. The delay circuits 5, 6 and 6 having the configuration of FIG.
The delay amount β in 7 corresponds to the delay amount in the determination circuit 20.

Here, the selection process in the configuration of FIG. 3 will be described with reference to FIG. 4 showing a timing chart of each part of the configuration of FIG.

In FIG. 4, it is assumed that the serial data string WD supplied to the input terminal 1 is as shown in A of FIG. Note that FIG. 4 shows an inverted version of the serial data string WD. The output of the 1 μs delay circuit 21 is the serial data string WD as shown in FIG. 4B.
Becomes a data string (WD + 1 μs) delayed by 1 μs,
The output of the 2 μs delay circuit 22 becomes a data string (WD + 2 μs) obtained by delaying the serial data string WD by 2 μs, as shown in C of FIG. The output of the delay circuit 6 is 1 when the serial data string WD is 1 as shown in D of FIG.
μs and the data string delayed by the delay amount α (WD + 1 μs
+ Α), and the output of the delay circuit 7 becomes a data string (WD + 1 μs + α) obtained by delaying the serial data string WD by 1 μs and a delay amount 2α as shown in E of FIG.

That is, in FIG. 4, the determination circuit 20 having the configuration shown in FIG.
The output of the s delay circuit 21 (B in FIG. 4) has a pulse, the write serial data string WD (A in FIG. 4) directly supplied has a pulse, and the output of the 2 μs delay circuit 22 (C in FIG. 4). ), There is no pulse, the selection switch 8 is made to select the output of the delay circuit 7 (E in FIG. 4). Further, in the determination circuit 20 having the configuration shown in FIG. 3, the output of the 1 μs delay circuit 21 (B in FIG. 4) has a pulse, and the pulse is directly supplied to the write serial data string WD (A in FIG. 4). If there is a pulse in the output of the 2 μs delay circuit 22 (C in FIG. 4), the selection switch 8 is made to select the output of the delay circuit 5 (B in FIG. 4). Further, the determination circuit 2 having the configuration shown in FIG.
0 is the case other than the above, that is, the above 1 μs delay circuit 2
1 output (B in FIG. 4) has a pulse, the write serial data string WD (A in FIG. 4) directly supplied has no pulse, and the output of the 2 μs delay circuit 22 (C in FIG. 4) has a pulse. Or there is a pulse in the output (B in FIG. 4) of the 1 μs delay circuit 21 and there is a pulse in the write serial data string WD (A in FIG. 4) which is directly supplied.
When the output of the μs delay circuit 22 (C in FIG. 4) has a pulse, the selection switch 8 is made to select the output of the delay circuit 6 (D in FIG. 4).

As described above, by applying the write compensating circuit 12 to the floppy disk drive device 10 of the floppy disk device, the compatibility of the floppy disk drive device 10 from the viewpoint of the floppy disk controller 100 and the floppy disk drive device are seen. It becomes possible to compensate for the peak shift while ensuring the compatibility of the medium (floppy disk) seen from the tenth point.

From the above, according to the present embodiment, it is possible to obtain the floppy disk drive device in which the peak shift is compensated and the error is small. Further, it is not necessary for the host computer to judge whether or not the floppy disk drive device to be used requires write compensation, and the floppy disk drive device that does or does not perform the compensation can be used in the same row. become. Furthermore, when manufacturing a floppy disk drive device, the presence or absence of compensation or the amount of compensation can be set according to the head to be used, so that it is possible to use a head with a wide range of resolution. Yield is improved. Furthermore, since it becomes possible to perform compensation according to the writing resolution of the head, compatibility of the written medium is not lost.

Referring back to FIG. 1, the floppy disk drive apparatus 10 of the embodiment of the present invention includes a capacitor C and a thermistor (temperature sensitive resistor) RT as temperature characteristic compensating means for compensating the temperature characteristic of the floppy disk. The write compensation circuit 12 is provided by the temperature characteristic compensating means.
Also, the write compensation amount is controlled.

That is, in the floppy disk drive device 10 of this embodiment shown in FIG. 1, a delay circuit (for example, a monomulti 30) for delaying the delay amount α arranged in the write compensation circuit 12 is used. By connecting the temperature characteristic compensating means including the capacitor C and the thermistor RT, the write compensation amount (delay amount α) in the write compensation circuit 12 is controlled. As a result, when barium ferrite, for example, is used as the magnetic material of the floppy disk, it becomes possible to perform recording in which the characteristics in the low temperature region are compensated by the temperature characteristic compensating means. Therefore, when the floppy disk recorded by the floppy disk drive device 10 of this embodiment is reproduced, data in which the temperature characteristic of the medium resolution is compensated is obtained as shown by the temperature characteristic curve Tb shown by the solid line in FIG. Like

From the above, according to the floppy disk drive apparatus of the present embodiment, the temperature characteristic of the resolution of the medium (floppy disk) using barium ferrite or the like is compensated, so that, for example, in the low temperature range. The characteristics do not deteriorate even when used (a floppy disk drive device that does not deteriorate the window margin even at low temperatures can be obtained). Therefore, the range of usable resolutions of the floppy disk drive device and the head is expanded, and the productivity is improved. Further, the temperature characteristic of the medium is mainly the temperature characteristic at the time of writing, but the compatibility of the written medium is not lost by changing the compensation amount at the time of writing.

[0047]

As described above, in the floppy disk drive device of the present invention, the write compensating circuit is arranged in the floppy disk drive device, so that the floppy disk drive device is compatible with the floppy disk controller. And the compatibility of the media (floppy disk) seen from the floppy disk drive device can be ensured and the peak shift can be compensated.

Further, the floppy disk drive device of the present invention has a temperature characteristic compensating means for compensating the temperature characteristic of the floppy disk, and the temperature compensating means controls the write compensation amount in the write compensating circuit. Therefore, the defect of the temperature characteristic of the medium can be compensated.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a floppy disk drive device according to an embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a schematic configuration of a write compensation circuit of the present embodiment.

FIG. 3 is a block circuit diagram showing a schematic configuration of another write compensation circuit.

FIG. 4 is a timing chart of each part of another write compensation circuit.

FIG. 5 is a diagram showing a schematic configuration of a conventional floppy disk device.

FIG. 6 is a waveform diagram for explaining a read serial data string having a peak shift with respect to a write serial data string.

FIG. 7 is a waveform diagram for explaining the principle of peak shift occurrence.

FIG. 8 is a waveform diagram for explaining the principle of occurrence of maximum peak shift.

FIG. 9 is a waveform diagram for explaining conventional peak shift compensation.

FIG. 10 is a characteristic diagram for explaining temperature characteristics of the conventional media and the media of the present embodiment.

[Explanation of symbols]

 2 ... Pulse interval measurement circuit 3 ... Shift register 4 ... Comparison circuit 5, 6, 7, 21, 22 ... Delay circuit 8 ... Selection switch 10 ... ... Floppy disk drive device 11 ... Control logic 12 ... Write compensation circuit 13 ... Read / write circuit 20 ... Judgment circuit 30 ... Mono delay multi-multi RT ・ ・ ・ ・ Thermistor C ・ ・ ・ Capacitor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Watanabe 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (2)

[Claims] 1. A floppy disk drive device for writing data from a host computer to a floppy disk and sending data read from the floppy disk to the host computer, wherein the serial data string written to the floppy disk is A floppy disk drive device comprising a write compensating circuit for compensating a difference between a serial data string written to a floppy disk and the serial data string read from the floppy disk. 2. A temperature characteristic compensating means for compensating the temperature characteristic of the floppy disk, wherein the temperature characteristic compensating means controls the write compensation amount in the write compensating circuit. The described floppy disk drive device.