JPH05233462A - Information processor - Google Patents

Abstract

PURPOSE:To obtain the information processor which can easily recover in case of data trouble of a flash ROM. CONSTITUTION:In case of the data trouble of the flash ROM 3, the 1st interface 6 of an information processing part 1 and the 2nd interface 8 of a data repair adapter 7 are connected to each other and then the input of a selecting means 5 which is pulled up by a resistance 11 is grounded to a grounding control line 28 through a control signal line 26. The result of AND between the ground level and the control signal from the control signal line 25 of a CPU 2 is sent out to a flash ROM control part 4 and a ROM control part 9 through a control signal line 27, the flash ROM 3 is inhibited from being read out, and a ROM 10 is accessed to perform data processing with the CPU 2 through an address bus 21, a data bus 22, and a control line 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device,
In particular, it relates to an information processing device using a flash ROM.

[0002]

2. Description of the Related Art In recent years, as a memory for storing software for starting up an information processing apparatus, an electrically erasable and writable flash ROM is used because the software can be easily upgraded after the product is shipped. There are many things.

As shown in FIG. 2, in the conventional information processing unit 101, a flash ROM 3 is connected to a CPU 102 via an address bus 21, a data bus 22 and a control signal line 23, and the CPU 102 is connected to the flash ROM 3 via a control signal line 24. To access and process data.

[0004]

However, in the above-described information processing apparatus, once the writing to the flash ROM fails, the information processing apparatus cannot be started again.

In such a situation, the information processing apparatus must be disassembled once and the IC or the board must be replaced, which is very troublesome for maintenance.

An object of the present invention is to provide an information processing apparatus capable of easily repairing a problem stored in a ROM without disassembling the apparatus in order to solve such a conventional drawback. That is.

[0007]

In order to solve the above-mentioned problems, an information processing apparatus of the present invention has a ROM in which backup data of a system program is stored in advance and this RO.
A ROM controller for controlling reading of M, a control signal line connected to an input terminal of the ROM controller, a ground signal line for sending a ground signal, and a first interface including the address and data buses of the ROM. A data repair adapter, a CPU, a flash ROM connected via the CPU's address and data bus, and storing the system program data, and the flash RO
A second interface including a flash ROM control section for controlling reading of M, a control signal line connected to an input terminal of the flash ROM control section, and an address and data bus of the flash ROM, and the second interface. And only when the above-mentioned first interface is connected,
The flash RO is generated by the output signal of the logical product of the ground signal from the ground signal line and the control signal from the CPU.
And an information processing unit having a selection means for accessing the ROM by prohibiting the access of M, and when the data stored in the flash ROM has a failure, the data repair adapter is connected to connect the data. It is characterized by performing processing.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

Flash RO mounted on the information processing unit 1
M3 is connected to the CPU 2 via an address bus 21, a data bus 22, and a control signal line 23, and the control signal line 24 is C
PU2 is a signal line for selecting the ROM 10, the control signal line 24 is connected to the flash ROM 3 via the flash ROM control unit 4, and the CPU 2 causes the flash ROM 3 to operate.
To access.

In the selecting means 5, the output signal of the logical product of the control signal of the control signal line 25 and the control signal of the control signal line 26 is output via the control signal line 27 to the flash ROM control section 4 and R.
It is output to the OM control unit 9.

The first interface 6 has an address bus 21, a data bus 22, and control signal lines 24 and 2.
6, 27 are connected.

The data repair adapter 7 includes a ROM 10 storing data of system programs, and the ROM 10
Address bus 21, data bus 22, ground signal line 28
Etc. are connected to the second interface 8.

The control signal line 24 is a control signal line 27.
ROM through the ROM control unit 9 controlled by the output signal of
The control signal line 26 connected to 10 is connected to the ground on the data repair adapter 7 side.

Next, the operation according to one embodiment of the present invention will be described with reference to FIG.
Will be explained.

When the second interface 8 of the data repair adapter 7 is not connected to the first interface 6 of the information processing section 1, the control signal line 26 is "
H ”, regardless of the output signal of the control signal line 24,
The control signal line 27 is “H”, and the flash ROM control unit 4 makes the flash ROM 3 accessible via the control signal line 24.

Further, the first interface 6 of the information processing unit 1 is provided with the second interface 8 of the data repair adapter 7.
Is connected, the ground signal line 2 of the data repair adapter 7
A ground signal is sent from 8 and the control signal line 26 is "L".
The control signal line 25 from the CPU 2 is "
Since the control signal line 27 becomes "L", the control signal line 27 becomes "L", the flash ROM control unit 4 cuts off the control signal line 24, and CP
U2 is RO via the control signal line 24 and the ROM control unit 9.
Access M10.

Next, a conventional information processing apparatus will be described with reference to FIG.

FIG. 2 is a configuration block diagram showing a conventional example.

In the conventional information processing unit 101, as shown in FIG. 2, the flash ROM 3 is connected to the CPU 102 via an address bus 21, a data bus 22 and a control signal line 23, and the CPU 102 is connected to the flash ROM 3 via a control signal line 24. To access and process data.

[0021]

As described above, according to the information processing apparatus of the present invention, the data in the flash ROM in the apparatus is
Even if it is damaged for some reason, you can easily start up the device by connecting the data repair adapter.
Moreover, it is effective in reducing the failure recovery time.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration block diagram showing a conventional example.

[Explanation of symbols]

 1, 101 Information processing section 2, 102 CPU 3 Flash ROM 4 Flash ROM control section 5 Selection means 6 First interface 7 Data repair adapter 8 Second interface 9 ROM control section 10 ROM 11 Selection means (resistor) 21 Address bus 22 data bus 23, 24, 25, 26, 27 control signal line 28 ground signal line

Claims (1)

[Claims] 1. A ROM in which backup data of a system program is stored in advance, a ROM control section for controlling reading of the ROM, a control signal line connected to an input terminal of the ROM control section, and a ground for sending a ground signal. A data repair adapter having a signal line and a first interface including an address and a data bus of the ROM, a CPU, and an address and a data bus of the CPU, which are connected to each other and store data of the system program. A flash ROM, a flash ROM control section for controlling reading of the flash ROM, and a second interface including a control signal line connected to an input terminal of the flash ROM control section and an address and data bus of the flash ROM. , The second interface and the first interface And a selecting means for prohibiting the access to the flash ROM and accessing the ROM only when the connection is continued by the output signal of the logical product of the ground signal from the ground signal line and the control signal from the CPU. The flash RO is composed of an information processing unit.
An information processing apparatus, wherein the data repair adapter is connected to perform data processing when a failure occurs in the data stored in M.