JPH05233150A - Disk controller operating by ckd-ex command - Google Patents

Abstract

PURPOSE:To prevent the deterioration of access efficiency with respect to a disk device. CONSTITUTION:A disk controller 2 controls a disk devices 3 and 4 provided with the disks of format designating the reading of a next record on the record, and transfers data with a host device 1 by a CKD-EX command. A cache memory 5 having a storage capacity storing the records for one track in the disk in accordance with the number of the disks 3 and 4 and a control means 6 indicating to store all the records of the track to which the record being the object of access is recorded to the cache memory 5 are provided. Whenever a new CCW chain is issued after the initial CCW chain is terminated, the record which the newly issued CCW chain designates is read from the cache memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk controller which operates by a CKD-EX (count key data extended form) command given from a host device, and more particularly to a CCW.
The present invention relates to a disk control device that operates with a CKD-EX command that prevents deterioration of access efficiency to a disk device when a PCI (program control interrupt) fetch mode is specified by (channel command word).

Some CKD command systems are used for data transfer between a host device and a disk device.
In this CKD command system, it is unknown whether the next command is a read command or a write command until the disk control device receives the command.

Therefore, at the beginning of the command chain, the CKD-EX command system is used in which the command to be sent from now is designated as a read command or a write command, and the number of records to be read or written is designated. It has become.

However, in this CKD-EX command system, the number of records to be read or written is declared in advance as described above, and it is prohibited to rearrange CCW after reading the records.

Before the practical use of the cache mechanism, as a method of accessing the disk device when reading data on tracks sequentially at high speed, is it necessary to use the next record among the records of the disk device? The PCI fetch operation for writing the data indicating whether or not it was valid.

However, for this PCI fetch operation, the upper device needs to recompose the CCW.
CCW recombination is prohibited in the CKD-EX command system. Therefore, it is necessary to prevent the access efficiency to the disk device from decreasing.

[0007]

2. Description of the Related Art In a disk device accessed by the CKD command system, a data storage area is managed by a VTOC (volume list). The VTOC records the addresses of cylinders and heads. The exact number of records in the set is not recorded.

Therefore, as described above, before the cache mechanism was put into practical use, the PCI fetch operation was effective as an access method to the disk device when sequentially reading data on tracks at high speed.

Therefore, the upper-level device reads a certain record, analyzes the data of this record, and if the next record is necessary, rearranges the CCW to efficiently access the disk device.

However, in this way, a disk drive equipped with a disk of a format for recording the data instructing to read the next record in the previous record is used as a CKD-E.
When accessing with the X command system, as described above, CC
Since the rearrangement of W is prohibited, it is necessary to analyze the record data and read the next record after exceeding the number of records declared in advance.
The chain will be terminated and a new CCW chain will be issued again.

[0011]

As described above, conventionally, when it is necessary to read the next record beyond the number of records declared in advance, the host device terminates the CCW chain once issued and then re-executes. Although a new CCW chain is created and issued, it takes time to create and issue this new CCW chain, and when the new CCW chain is received by the disk controller, the target record of the disk device is , It passes the head position.

Therefore, there is a problem that one revolution of the disk device is waited for each new CCW chain and the access efficiency is lowered. In view of such a problem, the present invention, when the PCI fetch mode is designated in advance by CCW, that is, data for instructing to read the next record,
When the mode for declaring access of the disk device with the disk of the format to record in the previous record is specified, all the records on the track where the target record exists are expanded to the cache memory, and the disk is written from this cache memory. New CCW, independent of media rotation
The purpose is to prevent the deterioration of access efficiency by making it possible to read the target record specified by the chain.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. The disk control device 2 is a disk device 3 to 4 equipped with a disk of a format for recording the data designating the read of the next record in the record.
Data is transferred to and from the host device 1 based on the CKD-EX command sent by the host device 1.

When a cache memory 5 having a storage capacity for storing one track of a disk corresponding to the number of the disk devices 3 to 4 and a PCI fetch mode is designated by the CKD-EX command. , And a control means 6 for instructing to store all the records of the track in which the record to be accessed is recorded in the cache memory 5, and a new CCW chain is issued following the end of the first CCW chain. Every time, the record specified by the newly issued CCW chain is read from the cache memory 5.

[0015]

With the above configuration, the CCW chain once issued by the host device 1 is terminated and a new CC is created.
Disk controller 2 when creating and issuing a W chain
Under the control of the control means 6, the target record designated by the new CCW chain is read from the records for one track stored in the cache memory 5, so there is no need to wait for the rotation of the disk. It is possible to prevent the access efficiency to the disk device 3 or 4 from being lowered.

[0016]

1 is a block diagram of a circuit showing an embodiment of the present invention, and FIG. 3 is a detailed block diagram of each functional unit.

The disk controller 2 is composed of a plurality of functional units, and the channel adapters 9 and 10 are shown in FIG.
With the configuration shown in FIG.
The program stored in the memory is read and operated, the CCW is received from the channel 7 or 8 through the interface circuit 17, the data is transferred between the channel 7 and 8, and the common bus control circuit 18 is controlled. Common bus 16
Data is transferred to and from other functional units via the.

The device adapters 11 and 12 are shown in FIG.
With the configuration as shown in FIG. 3, the processor 19 reads out a program stored in the control memory 20 to operate, sends a command to the disk device 3 or 4 via the interface circuit 17, and transmits data to and from the disk device 3 or 4. While performing the transfer, the common bus control circuit 18 is controlled to control the common bus 16
Data is transferred to and from other functional units via the.

The resource manager 13 has a configuration as shown in FIG. 3B, and the processor 22 operates by reading the program stored in the control memory 21, and controls the common bus control circuit 23 to operate the common bus 16. Via the access, the information of access to the disk device 3 or 4 indicated by the CCW from the channels 7 and 8 is received and stored in the RAM 24, this information is centrally managed, and the channel adapters 9 and 10 are provided for each CCW. The device adapters 11 and 12 are instructed to perform data transfer processing.

Further, the received control information for each CCW, control information for each channel path, and control information for the disk devices 3 and 4 are stored in the RAM 24, and other functional units pass through the RAM access control circuit 25 and It is possible to access the RAM 24 and read the above information, and centrally manage this information.

For example, channel 7 is channel adapter 9
However, when instructing to read data, the next CC
Chain W and send out. That is, DX (Define extent) that defines a read or write operation and indicates whether or not it is in the PCI fetch mode, LR (Locate record) that indicates the read or write operation start position, and RD (Read Each CCW of (data) is chained and transmitted.

Upon receiving the DX command, the channel adapter 9 sends P to the resource manager 13 via the common bus 16.
In order to notify the CI fetch mode, the resource manager 13 creates in the shared memory 14 a cache memory area 15 having a capacity capable of storing all records recorded in one track.

When the disk device 3 is designated by the LR command, the channel adapter 9 requests the resource manager 13 for the right to use the common bus 16, and when it is permitted, it is designated by the LR command in the RAM 24 in the resource manager 13. It stores the cylinder address and head address.

The device adapter 11 reads the information in the RAM 24, that is, the cylinder address and the head address according to the instruction of the resource manager 13, controls the disk device 3, and positions the head at the cylinder address given from the channel adapter 9. Then, the data read by the designated head is stored in the cache memory area 15. That is, all the records of the corresponding track are read and stored.

The channel adapter 9 selects one track of the records stored in the cache memory area 15 from
The number of records designated by the RD command is read from the record designated by the LR command and transferred to the channel 7.

The channel adapter 9 continues to the channel 7
When a new CCW chain is sent from the CCW
The number of records designated by the RD command is read from the record designated by the LR command of the chain from the cache memory area 15 and transferred to the channel 7.

The same applies when the disk device 4 is accessed from the channel 8 via the channel adapter 10 and the device adapter 12, and the channel adapter 10 to the PCI is accessed.
The resource manager 13 notified of the fetch mode expands the area of the cache memory area 15 of the shared memory 14 and secures a capacity capable of storing all the records for one track read from the disk device 4.

The cache memory area 15 is controlled based on the well-known LRU (Least Recently Used) control,
Until the record for the next one track is stored from the same disk device 3 or 4, the previously stored record for the one track is left, so that the record of the same track is read in the next CCW chain. When specified in the PCI fetch mode, the target record is transferred from this cache memory area 15.

[0029]

As described above, the present invention is CKD-E.
If PCI fetch mode is specified by the X command,
End the CCW chain once issued by the channel,
When a new CCW chain is created and issued, the disk controller reads the target record specified by the new CCW chain from the records for one track stored in the cache memory area, so the disk rotation There is no need to wait, and it is possible to prevent the efficiency of access to the disk device from decreasing.

For example, if the track to be read in the PCI fetch mode is composed of 20 records, normally 4 records are regarded as one block, and the fetch is performed in units of this block.

If the present invention is not applied and the time required for one rotation of the disk is 16 ms, 16 × 5 = 80 ms is calculated by simple calculation to read these 20 records.
However, when the present invention is applied, at most 1
The process ends in 6 ms.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention.

FIG. 3 is a detailed block diagram of each functional unit.

[Explanation of symbols]

 1 host device 2 disk control device 3, 4 disk device 5 cache memory 6 control means 7, 8 channels 9, 10 channel adapter 11, 12 device adapter 13 resource manager 14 shared memory 15 cache memory area 16 common bus 17 interface circuit 18, 23 Common bus control circuit 19, 22 Processor 20, 21 Control memory 24 RAM 25 RAM Access control circuit

Claims (1)

[Claims] 1. A CKD-EX command sent by a higher-level device (1) for controlling a disk device (3) to (4) equipped with a disk of a format for recording data designating reading of the next record in a record. A disk controller (2) that transfers data to and from the host device (1) based on the above, and records one track of the disk into the numbers of the disk devices (3) to (4). A cache memory (5) having a corresponding storage capacity, and all records of the track in which the record to be accessed is recorded in the cache memory (5) when the PCI fetch mode is specified by the CKD-EX command. And a control means (6) for instructing to store C, and a new CW following the end of the first CCW chain.
Each time a CW chain is issued, the newly issued C
The record specified by the CW chain is stored in the cache memory.
(5) A disk control device which operates by CKD-EX command, which is characterized by reading from.