JPH05224976A - Program development back-up device - Google Patents

Abstract

PURPOSE:To provide a program development back-up device which can develop the programs simply and in a short time. CONSTITUTION:A program development back-up device is provided with a personal computer 1, a host computer 2, an ICE unit 3, and a CRT 4. The source program produced by the computer 1 is transferred to the computer 2 to undergo the assembly processing and the link processing and then converted into an object program. When both assembly and link processing are through via the computer 2, the object program is stored in an emulator RAM 205. Then the unit 3 actuates a test game machine 5 to carry out the program stored in the RAM 205. In such a constitution, the program is verified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program development supporting device, and more specifically, it is created by converting an input source program into an object program and then executing the object program in a test device. The present invention relates to a program development support device for developing a program while verifying the program.

[0002]

2. Description of the Related Art A data processing device such as a video game machine (for example, a product name "Super Family Computer" sold by the applicant of the present application) that operates according to a predetermined program has been known. Conventionally, the development of a program used for such a data processing device, for example, a video game machine has been performed as follows.

In the first method, a source program input by a general-purpose personal computer (hereinafter abbreviated as a personal computer) is temporarily stored in a working RAM in the personal computer, and after the source program is completed, the data in the working RAM is transferred to a video game machine. It is a method of converting into a machine language conforming to the above, burning it on an external ROM board, and inserting this ROM board into a video game machine for checking.

In the second method, a source program input by a general-purpose personal computer is temporarily stored in a working RAM in the personal computer.
Stored in the working RA after completion of the source program
In this method, M data is converted into a machine language suitable for a video game machine, copied to an external emulator RAM, and the emulator RAM is inserted into the video game machine for checking.

[0005]

The first method has a problem in that a new ROM board must be prepared when modifying the created game program, which requires a great deal of time and labor. there were. Also, the personal computer performs various operations, that is, data input processing, monitor display processing, interface with an external storage device (floppy disk, hard disk, etc.), writing control to the ROM board, and program data assembly. Also, the link processing and the control of the test operation of the video game machine must be performed, and the load on the personal computer becomes extremely large. As a result, the processing speed of the personal computer slows down, and it takes a long time to develop the program.

In the second method, when the created game program is modified, the modified game program may be copied again to the same emulator RAM, and the problem as in the first method using the ROM substrate may occur. Although it does not occur, the load on the personal computer is still heavy and it takes a long time to develop the program.

[0007] Therefore, an object of the present invention is to provide a program development support device that can create a program more easily and in a shorter time.

[0008]

The invention according to claim 1 is
A program development support device for converting a source program that has been input into an object program and then executing the object program in a test device to develop the program while verifying the program that is being created. Means, first data processing means, and second data processing means communicatively coupled to the first data processing means. First
The data processing means of the first input means for inputting the source program, the transmitting means for transmitting the input source program to the second data processing device, and the first monitoring means for the input data from the input means. And display control means for displaying on. The second data processing means is
Receiving means for receiving the source program sent by the sending means, object program creating means for assembling and linking the source program received by the receiving means to convert into an object program, and creating by the object program creating means An emulator memory for storing the stored object program and a test device control means for causing the test device to execute the object program stored in the emulator memory.

According to the second aspect of the invention, the first data processing means responds to a source program storage means for storing the source program input from the input means and an access request for the source program from the second data processing means. In response, it further includes transmission control means for reading the source program from the source program storage means and causing the transmission means to transmit the source program. Further, the second data processing means further includes a cache memory for storing the object program being created by the object program creating means. The object program creating means directly loads the corresponding data from the cache memory when the data to be processed next is stored in the cache memory and processes it, and when the data to be processed next is not stored in the cache memory, the first program
A source program access request is issued to the data processing means.

In the invention according to claim 3, the test apparatus comprises:
It includes an image processing means and a second monitor means. The image processing means is configured such that an external memory cartridge storing an image processing program is detachably attached, and generates an image signal based on the image processing program. The second monitor means is connected to the image processing means and generates an image based on the image signal supplied from the image processing means.
Monitoring means. The test device control means
By giving the object program stored in the emulator memory as the image processing program to the image processing means, the image based on the program being created is output to the second monitor means.

[0011]

In the program development support apparatus according to the first aspect, the object program created by the object program creating means is stored in the emulator memory, and the object program stored in the emulator memory is read and executed by the test apparatus. Even when modifying the created program, it is only necessary to rewrite the contents of the emulator memory, and there is no need to prepare a new memory board as in the conventional case. Also, the first data processing means performs data input processing, monitor display processing, and interface with an external storage device (floppy disk, hard disk, etc.), and the second data processing means performs emulator memory. Writing control, assembling and linking of program data, and operation control of the test device are performed, so that the load is distributed and the program can be developed in a short time.

In the program development support apparatus according to the second aspect, the object program being created by the object program creating means is stored in the cache memory, and when the object program creating means executes the assemble or link processing, If the cache memory is accessed and the corresponding data is stored in this cache memory, the object program creating means loads the data directly from this cache memory and processes the data, so high-speed data access Is possible.

In the program development support device according to the third aspect, the test device control means gives the image processing means an object program stored in the emulator memory as an image program, so that an image based on the program being created is displayed. It is output to the second monitor means. Therefore, since the created program can be confirmed immediately, the program can be easily modified.

[0014]

1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the program development support apparatus of this embodiment is shown as a personal computer 1 and a host computer 2.
And ICE (In Circuit Emulator)
It has a unit 3 and a CRT 4 as a monitor means.

The personal computer 1 is used as a terminal device for inputting character data for image display and for inputting program data for designating display coordinates, display timing, type, etc. of the character. If the present invention is applied to the development of a game program, the personal computer 1 is a terminal for inputting a game sound effect or a game music program, in addition to the input of the program for displaying an image as necessary. Also used as a device. This personal computer 1 is specifically a CPU 101
, RAM 102, ROM 103, and video RAM 1
04, a parallel transmission interface 105, a parallel reception interface 106, a keyboard / mouse interface 107, a keyboard / mouse 108,
Floppy interface 109, floppy disk drive 110, hard disk interface 1
11, a hard disk drive 112, and a CRT controller 113.

RAM 102, ROM 103 and video RAM 104 are connected to CPU 10 via memory bus 115.
It is connected to 1. The RAM 102 includes storage areas 102a to 102d, as shown in FIG. Storage area 10
A parallel transmission / reception program for a personal computer for data transmission with the host computer 2 is stored in 2a. The storage area 102b stores a personal computer side macro command execution program for executing a personal computer side macro command. The storage area 102c stores an application program read from a floppy disk or a hard disk. The storage area 102d is used as a work area for storing work data of the CPU 201.

The ROM 103 includes a storage area 103a as shown in FIG. In this storage area 103a, I
PL (Initial Program Load)
r) is stored. The IPL is a program that has a function of reading an initial program of an application program when the personal computer 1 is started.

The video RAM 104 is a memory for storing image data to be displayed on the CRT 4. The image data read from the video RAM 104 is CR
It is given to the T controller 113.

Parallel transmission interface 105, parallel reception interface 106, keyboard / mouse interface 107, floppy interface 10
9. Hard disk interface 111 and CRT
The controller 113 is connected to the CPU 101 via an input / output (hereinafter abbreviated as I / O) bus 116.

The parallel transmission interface 105 is C
This is a circuit for transmitting the output data of the PU 101 as parallel data to the host computer 2, and its transmission output is given to the parallel reception interface 207 in the host computer 2. The parallel reception interface 106 is a circuit for receiving parallel data transmitted from the parallel transmission interface 208 of the host computer 2 and outputting it to the CPU 101. The keyboard / mouse interface 107 takes in the input data from the keyboard / mouse 108 and outputs C
This is a circuit for outputting to the PU 101. The floppy interface 109 is the floppy disk drive 1
A circuit for outputting the data read from a floppy disk (not shown) by the CPU 10 to the CPU 101. The hard disk interface 111 is a circuit for outputting data read from a hard disk (not shown) by the hard disk drive 112 to the CPU 101.

The CRT controller 113 is the CPU 10
1. Control data given from 1 and video RAM 104
It is a circuit for displaying an image on the CRT 4 based on the image data read from the.

The host computer 2 has a CPU 201.
, Main RAM 202, ROM 203, cache RAM 204, emulator RAM 205, common RAM 206, parallel reception interface 207
And a parallel transmission interface 208.

The parallel reception interface 207 and the parallel transmission interface 208 are connected to the I / O bus 21.
It is connected to the CPU 201 via 0. The parallel reception interface 207 is a circuit for receiving parallel data transmitted from the parallel transmission interface 105 in the personal computer 1 and outputting it to the CPU 201. The parallel transmission interface 208 is a CPU
It is a circuit for transmitting the data given from 201 to the parallel reception interface 207 of the personal computer 1 as parallel data.

The main RAM 202 includes storage areas 202a to 202i, as shown in FIG. Storage area 20
A user command collation / execution program program for collating and executing a user command given from the personal computer 1 is stored in 2a. Storage area 20
A user command table containing various user command data is stored in 2b. Storage area 202
In c, a host side macro command execution program for executing the host side macro command is stored.
An intermediate language conversion program for converting the source program into an intermediate language is stored in the storage area 202d. The storage area 202e stores an assemble operation table containing various operation data required when executing the assemble processing. The storage area 202f stores intermediate language data created by executing the intermediate language conversion program. An assemble execution program for assemble processing is stored in the storage area 202g. A link execution program for link processing is stored in the storage area 202h. The storage area 202i is used as a work area for storing work data of the CPU 101.

The ROM 203 includes storage areas 203a and 203b, as shown in FIG. Storage area 203a
Stores a parallel transmission / reception program for a host for data transmission with the personal computer 1. An IPL is stored in the storage area 203b.

The cache RAM 204 stores the source program transmitted from the personal computer 1 or the object program being created. Emulator RAM2
Reference numeral 05 stores the object program completed by the assemble process and the link process. Here, the assemble processing refers to converting a source program created in the assembler language into a machine language (a sequence of 1 or 0). Further, the link processing means to connect two or more program files into an executable format. In this linking process, for example, a subroutine that performs a specific work is linked to the main program to create an executable program. The source program is the first program that the programmer directly inputs to the computer based on the flowchart. An object program is a program in which a source program is translated by an assembler and converted into a form (machine language) that can be directly executed by a computer. The object program as a machine language stored in the emulator RAM 205 is given to the external test game machine 5. The common RAM 206 is used as a buffer for data communication with the ICE unit 3.

The ICE unit 3 includes a CPU 301 and an R
It includes an AM 302, a ROM 303, and a test game machine control interface 304. RAM 302 and R
The OM 303 is the CPU 301 via the memory bus 305.
It is connected to the. Further, the common RAM 206 in the host computer 2 is connected to the CPU 301 via the memory bus 305. The test game console control interface 304 is connected to the CPU 301 via the I / O bus 306. The test game machine control interface 304 is further connected to an external test game machine 5.

The test game machine 5 is a game machine for testing the created object program.
The configuration of the test game machine 5 may be arbitrary, but in this embodiment, the name of the product sold by the applicant is “Super Nintendo” or “Super Nintendo”.
"ENTERTAINMENT SYSTEM" is used. Therefore, the test game machine 5 is configured such that the ROM cartridge storing the game program is detachable. Then, the test game machine 5 causes the monitor device 6 such as a CRT to display an image and outputs a sound in accordance with the game program read from the program ROM. The emulator RAM 205 in the host computer 2 is used instead of the ROM cartridge, and the program read from the emulator RAM 205 is given to the test game machine 5 as a game program. Therefore, the test game machine 5 has the emulator RAM 2
An image signal and an audio signal are generated in accordance with a program given from 05 and given to the monitor device 6. The ICE unit 3 controls the operation when the test game machine 5 tests a program.

Next, the operation of the embodiment shown in FIG. 1 will be described. 6 and 7 are flow charts related to the operations of the personal computer 1 and the host computer 2 when creating and modifying a program. Hereafter, this FIG.
The overall flow of the operation of the program development support apparatus shown in FIG. 1 will be described with reference to FIG.

When the power source (not shown) of the program development support device shown in FIG. 1 is turned on, the CPU 1 on the personal computer 1 side
01 starts an application program in step S101. The operation of step S101 is executed according to the IPL stored in the storage area 103a (see FIG. 3) of the ROM 103. That is, the CPU
Reference numeral 101 drives a floppy disk drive 110 or a hard disk drive 112, reads a parallel transmission / reception program for a personal computer, a personal computer side macro command execution program, and an application program from a floppy disk or a hard disk (not shown), and stores them in a storage area in a RAM 102, respectively. 1
02a, 102b and 102c. After that, C
The PU 101 operates according to each program stored in the RAM 102.

On the other hand, the CPU 2 on the host computer 2 side
01 performs initial setting in step S201.
The initial setting in step S201 is executed according to the IPL stored in the storage area 203b (see FIG. 4) of the ROM 203. At this time, the ICE unit 3 is also activated.

Next, the CPU 201 executes step S202.
At, the program load instruction is transferred to the personal computer 1. At this time, the program load instruction is the I / O bus 2
It is given to the parallel transmission interface 208 via 10 and transmitted from the parallel transmission interface 208 to the personal computer 1. The personal computer 1 receives the program load command transmitted from the host computer 2 by the parallel reception interface 106. The reception data of the parallel reception interface 106 is I / O.
It is given to the CPU 101 via the bus 116. CPU
In response to the given program load command, the 101 reads the program data for the host computer 2 from the floppy disk or hard disk, and transmits it to the host computer 2 by the parallel transmission interface 105 (step S10).
2). In the host computer 2, each program data transmitted from the personal computer 1 is received by the parallel reception interface 207 and given to the CPU 201. The CPU 201 stores the given program data in the storage areas 202a to 202a of the main RAM 202.
202e, 202g, 202h, and first, the host side macro command execution program loaded in the storage area 202c is activated (step S203).

Next, the CPU 201 executes step S204.
At, the one-line input command is transferred to the personal computer 1. This one-line input command is a command for allowing the user to input a command to the personal computer 1. CPU10
In response to a one-line input command given from the CPU 201, the computer 1 puts the personal computer 1 in a command input enable state (so-called prompt state). At this time, the user operates the keyboard or the mouse, and the editor start command is input to the CPU 101 via the keyboard / mouse interface 107 (step S103). In response, the CPU 101 transfers the input editor activation command to the host computer 2 (step S10).
4). CPU 201 that received the editor start command
Interprets the command and transfers the editor start instruction to the personal computer 1 (step S205). Depending on the CPU
101 starts an editor (step S10)
5). Here, the editor means a tool for editing a program or data according to a user's instruction, and is mainly used when creating a source program. This editor is realized by software processing of the CPU 101.

Next, the CPU 101 edits the data input by the user operating the keyboard or mouse with an editor to create a source program (step S106). The source program created at this time is temporarily stored in a floppy disk or hard disk. The CPU 201 is in a standby state while the source program is being created (step S206). When the creation of the source program is completed, the CPU 101 terminates the editor and transfers a message to that effect to the host computer 2 (step S107).
In response, the CPU 201 transfers the one-line input command to the personal computer 1 (step S207).

Next, the user operates the keyboard or mouse to input an assemble / link command to the CPU 101 (step S108). Depending on the CPU
The 101 transfers the input assemble / link command to the host computer 2 (step S109).

Upon receiving the assemble / link command, the CPU 201 executes the assemble process. That is, the CPU 201 converts the source program created by the personal computer 1 into a machine language. On the other hand, the CPU 10
1 starts the editor in response to the editor start command input from the keyboard or mouse in step S110 (step S111). When the assembling process in the host computer 2 ends (step S209), the CPU 201 next executes the link process (step S210). By this linking process, a plurality of program files are linked and integrated into one object program as a whole. Usually, the source program is created by being divided into a plurality of blocks. In the assemble processing, the source program is converted into machine language for each block. In the linking process, the data of each block converted into a machine language is connected. When the link processing in the host computer 2 ends (step S211), the CPU 201 transfers the result of the assemble and link processing to the personal computer 1 (step S21).
2). In response, CPU 101 displays the result of the assemble and link processing on CRT 4 (step S11).
2).

Next, the CPU 201 transfers the one-line input command to the personal computer 1 (step S213). At this time,
The user inputs an emulator RAM transfer command and an ICE unit operation command from the keyboard or mouse to the CPU 101 (step S113). In response, the CPU 101 transfers the input emulator RAM transfer command and ICE unit operation command to the host computer 2 (step S114). CP
In response to the emulator RAM transfer command, the U 201 transfers the object program stored in the cache RAM 204 to the emulator RAM 205 (step S214).

Subsequently, the CPU 201 gives an instruction to start the test operation to the ICE unit 3 (step S21).
5). Accordingly, the CPU 301 in the ICE unit 3
Outputs an activation command to the test game machine 5 via the test game machine control interface 304. Depending on,
The test game machine 5 reads the object program stored in the emulator RAM 205 and executes it. At this time, the ICE unit 3 controls the operation of the test game machine 5. For example, ICE unit 3
Gives a reset signal to the test game machine 5 and a step operation control signal for the debugger. The step operation means an operation of stopping the execution of the program at an arbitrary timing.

On the other hand, in the personal computer 1, the user inputs an editor activation command from the keyboard or mouse to the CPU 101 (step S115). In response, CPU 101 activates the editor (step S116). Next, the CPU 101 edits the data input by the user using an editor and corrects the created source program (step S11).
7). At this time, the user inputs data for modifying the source program based on the image display result and the audio output result of the monitor device 6 in the test game machine 5. When the correction of the program ends, the CPU 101 ends the editor (step S118).

When the operation of step S118 ends, the CPU 101 returns to step S108 and repeats the operations of step S108 and thereafter. When the operation of step S215 ends, the CPU 201 returns to step S207 and repeats the operations of step S207 and thereafter.
Therefore, the modified source program is reassembled and linked. After that, the same operation is repeated, and the created program is corrected a plurality of times to complete the final program. The object file created by the CPU 201 performing the link process is the cache RA.
Emulator RAM 205 without going through M204
May be directly stored in. As a result, the cache RA
Data transfer time from the M204 to the emulator RAM 205 can be saved, and the processing time can be further shortened.

FIG. 8 is a flow chart showing the details of the operation when the CPU 201 transfers the one-line input command to the personal computer 1 and interprets and executes the command data returned from the personal computer 1. The flowchart of FIG. 8 corresponds to the operation of steps S204 and S205 or steps S207 and S208 of FIG. 6 or steps S213 and S214 of FIG. Hereinafter, with reference to FIG. 8, the transfer operation of the one-row input command by the CPU 201 and the processing operation of the command data returned based on the transfer operation will be described.

First, the CPU 201 executes step S301.
In, the one-line input process is performed. This step S301
For details of the subroutine, refer to steps S401 to S401 in FIG.
408. Note that FIG. 9 also shows a flowchart of corresponding operations in the CPU 101 in order to clarify the correspondence relationship with the personal computer 1.

Referring to FIG. 9, first, CPU 201 determines whether or not the personal computer reception flag is turned on (step S401). This personal computer reception flag indicates whether or not the personal computer 1 can receive the transmission data from the host computer 2, and is transferred from the CPU 101 to the CPU 201 before the personal computer 1 enters the receivable state. When the personal computer 1 receives a personal computer reception flag, the CPU 201 loads and retains the personal computer reception flag in an internal register. When the personal computer reception flag is turned on, that is, when the personal computer 1 is in the receivable state, the CPU 201 determines in step S402.
PC 1 for macro command to instruct 1-line input
Send to. Next, the CPU 201 performs step S403.
At, the host transmission flag is turned on, and the turned on host transmission flag is transmitted to the personal computer 1.

In response, the CPU 101 determines that the host transmission flag is turned on (step S50).
1) Input a macro command for one-line input transmitted from the host computer 2 (step S50)
2). Next, the process proceeds to step S503, and the CPU 101
Turns on the PC reception flag. Succeedingly, in a step S504, the CPU 101 executes the macro command for inputting one line. That is, the CPU 101
It is displayed on the CRT 4 that it is in a command input enabled state (so-called prompt state), and command input from the keyboard or mouse is accepted.

Next, in step S505, the CPU 1
01 determines whether or not the host reception flag is turned on. At this time, since the host reception flag is on, the process proceeds to step S506, and the CPU 101 transmits the execution result of the macro command, that is, the character data representing the command to the host computer 2. Succeedingly, in a step S507, the CPU 101 turns on the personal computer transmission flag, and transmits the turned-on personal computer transmission flag to the host computer 2.

In response, CPU 201 determines that the PC transmission flag is turned on (step S40).
4). Next, in step S405, the CPU 201
Inputs the command data sent from the personal computer 1 in step S506 described above. Next, proceeding to step S406, the CPU 201 turns on the host reception flag. Next, in Step S407, the CP
The U201 stores the data input in step S405 in the work area 202i of the main RAM 202. Next, proceeding to step S408, the CPU 201 determines whether the input data is a carriage return code (code indicating the end of data). If the input data is a carriage return code, step S40 is executed again.
The operations of 4 to S408 are executed. On the other hand, if the input data is the carriage return code, the data input from the personal computer 1 has been completed, and thus step S30 in FIG.
Return to 2.

Referring again to FIG. 8, the CPU 201 interprets the command data stored in the work area 202i of the main RAM 202 in step S407 (step S302). The process of step S302 is performed based on the user command collation / execution program stored in the storage area 202a of the main RAM 202. That is, the CPU 201 collates the command data stored in the work area 202i of the main RAM 202 with a plurality of types of user commands stored in advance in the user command table 202b, and the command data given from the personal computer 1 determines which one. Detects a match with a user command.

Next, in step S303, the CPU 2
01 indicates whether the user command given from the personal computer 1 is a command to be processed by the host computer 2,
It is determined whether the command should be processed by the personal computer 1.
If the user command is a command to be processed by the host computer 2, the process proceeds to step S304 and the CP
U201 executes the program corresponding to the user command. That is, the corresponding host side macro command execution program is selected and executed from the storage area 202c of the main RAM 202. After the operation of step S304, the CPU 201 ends the operation and returns to the operation of FIG. 6 or 7 again.

On the other hand, if the user command is a command to be processed by the personal computer 1, the process proceeds to step S305, and the CPU 201 determines whether or not the personal computer reception flag is turned on. When the personal computer reception flag is turned on, the process proceeds to step S306, and the CPU 201 outputs the macro command corresponding to the user command and transmits it to the personal computer 1. The macro command transmitted at this time is generated based on the user command collation / execution program stored in the storage area 202a of the main RAM 202. Next, in step S307, the CPU 2
01 turns on the host transmission flag. continue,
In step S308, the CPU 201 determines whether the personal computer transmission flag is turned on. When the personal computer transmission flag is turned on, the process proceeds to step S309, and the CPU 201 inputs the data transmitted from the personal computer 1. Next, in step S310, C
The PU 201 turns on the host reception flag. After that, the CPU 201 transfers the macro command again to the personal computer 1 as necessary, and inputs the return data from the personal computer 1 (step S311). Then CP
U201 ends the operation and returns to the operation of FIG. 6 or 7.

FIG. 10 shows step S208 in FIG.
8 is a flowchart showing a more detailed operation of the CPU 201 corresponding to steps S211. 11 and 12 are flowcharts showing details of the subroutine of step S601 in FIG. FIG. 13 is a flowchart showing details of the subroutine of step S602 in FIG. FIG. 14 shows step S6 in FIG.
It is a flowchart which shows the detail of the subroutine of 03. The CPU 2 will be described below with reference to FIGS.
Detailed operations of the assemble process and the link process executed by 01 will be described.

First, in step S601 of FIG. 10, the CPU 201 assembles the source file (data group forming one block in the source program) or object file (source file data) to be subjected to the assemble process or link process. Data group) is loaded. Next, in step S602,
The CPU 201 converts the loaded source file data into an intermediate language. Here, the intermediate language has a function of saving the memory capacity by replacing the data of a plurality of characters representing each instruction on the source program with the corresponding code. The coded version of this source program is called an intermediate language. Next, step S603.
Then, the CPU 201 assembles the source program converted into the intermediate language, that is, converts it into a machine language directly executable by the computer.

Next, in step S604, the CPU 2
01 performs a link process on each object file stored in the cache RAM 204. Next, the processing proceeds to step S605, and the CPU 201 determines whether or not the link processing has ended. If the link processing has not ended, the operations of steps S604 and S605 are executed again. When the link process is completed, the process returns to the operation of FIG.

Next, referring to FIGS. 11 and 12, a more detailed operation of the subroutine of step S601 in FIG. 10 will be described. First, in step S701, C
The PU 201 determines whether or not the cache RAM 204 stores a source file or an object file required for the assemble process or the link process. If the corresponding file is not stored in the cache RAM 204, the process proceeds to step S702 and CP
U201 determines whether or not the personal computer reception flag is turned on. If the PC reception flag is turned on, the process advances to step S703, the CPU 201 outputs a macro command for loading the source program,
Send to PC 1. Next, proceeding to step S704, the CPU 201 determines whether or not the personal computer reception flag is turned on. When the PC reception flag is turned on, the data and parameters required for loading the source program are output byte by byte and sent to the PC 1. Next, the process proceeds to step S706 and the CPU 20
1 turns on the host transmission flag. Next, proceeding to step S707, the CPU 201 determines whether or not the output of data to the personal computer 1 has been completed. If the output of data has not been completed, the operation returns to step S704 again, and the operations of steps S704 to S707 are repeated.

When the output of data to the personal computer 1 is completed, the process proceeds to step S708 in FIG. 12, and the CPU 201 determines whether or not the personal computer transmission flag is turned on. At this time, the personal computer 1 reads the source program from the floppy disk or hard disk,
It transmits to the host computer 2 byte by byte. If the personal computer transmission flag is turned on, the process advances to step S709, and the CPU 201 inputs the source program data sent from the personal computer 1 byte by byte and stores it in the cache RAM 204. Next, proceeding to step S710, the CPU 201 turns on the host reception flag. Next, proceeding to step S711, the CPU 201 determines whether or not the source program data transmitted from the personal computer 1 has ended. If the transmission data has not ended, the operation returns to step S708 again, and the operations of steps S708 to S711 described above are repeated.

On the other hand, when the transmission data is completed, the process proceeds to step S712, and the CPU 201 creates a cache directory. The cache RAM 204 has a directory area and a data area. In the data area,
Each file of the source program is stored. The directory area stores the file name, size, data creation date, and start address of the data area for each file. In step S712, the directory data of each file in the data area is created and stored in the directory area of the cache RAM 204. Next, proceeding to step S713, the CPU 201 loads the start address of each file stored in the cache RAM 204 into the internal register as a parameter.

On the other hand, when the corresponding file is stored in the cache RAM 204 in the above-mentioned step S701, the CPU 201 executes steps S702-S702.
The operation of S712 is skipped, and step S713 is directly executed.
Perform the operation of. That is, the CPU 201 does not transfer the data from the personal computer 1 and the cache RAM 2
The start address of each file in 04 is loaded as a parameter.

Next, with reference to FIG. 13, a more detailed operation of the subroutine of step S602 shown in FIG. 10 will be described. First, the CPU 201 reads the first source file from the cache RAM 204 in step S801. This reading operation is performed by the above-mentioned step S713.
In FIG. 12, reference is made to the start address of each source file loaded in the internal register of the CPU 201. Next, in step S802, the CPU 2
01 refers to the assemble operation table stored in the storage area 202e of the main RAM 202. Next, proceeding to step S803, the CPU 201 converts the data of the source file read at step S801 into intermediate language data, and stores the data in the storage area 2 of the main RAM 202.
It is stored in 02f. The conversion processing into intermediate language data in step S803 is performed based on the assemble operation code in the assemble operation table referenced in step S802. Then step S
Proceeding to 804, the CPU 201 determines the cache RAM 204.
Determines whether all source files inside have been translated into an intermediate language. When the source file to be converted into the intermediate language remains, the operations of steps S801 to S804 are repeated again. On the other hand, when the conversion of all source files is completed, the process returns to the operation of FIG.

Next, referring to FIG. 14, a more detailed operation of the subroutine of step S603 shown in FIG. 10 will be described. First, in step S901, the CPU 201 reads the source file data converted into the intermediate language from the storage area 202f of the main RAM 202. Next, proceeding to step S902, the CPU 201 calculates the relative address value of the instruction label given to the predetermined instruction by calculating the number of instructions in the source file. Next, proceeding to step S903, the CPU 201 determines whether the calculation of relative address values has been completed for all the source files in the cache RAM 204. When the calculation of the relative address value is not completed, the operations of steps S901 to S903 are repeated again.

On the other hand, when the calculation of the relative address value for all the source files is completed, step S90
In step 4, the CPU 201 reads the source file converted into the intermediate language from the storage area 202f of the main RAM 202. Next, in step S905, the CPU 20
1 assembles the source file converted into the intermediate language, that is, converts into the machine language, and stores it in the cache RAM 204 as an object file. Next, proceeding to step S906, the CPU 201 causes the cache RA
It is determined whether the assembling process for all the source files in M204 is completed. When the source file to be subjected to the assemble processing remains, the operations of steps S904 to S906 are repeated. on the other hand,
When the assembling process for all the source files is completed, the process returns to the operation of step S604 in FIG.

Next, the cache RAM in this embodiment
The operation and advantages of 204 will be described in more detail.

First, in the process of assembling the source program, the source files are sequentially transferred from the personal computer 1 to the host computer 2, and the cache RAM 204
Stored in. The CPU 201 is the cache RAM 20
Assembling processing is performed on each source file stored in 4. Next, when link processing is performed, since each object file is already stored in the cache RAM 204, the CPU 201 causes the cache RAM 2
It is possible to directly load each object file from 04 and execute the link processing. Therefore, since it is not necessary to transfer data from the personal computer 1, the data access time can be shortened. Next, when modifying any part of the prototyped program, only the corresponding source file (modified source file) is input from the personal computer 1 and transferred to the host computer 2. Since the other source files are stored in the cache RAM 204, the CPU 201 does not need to instruct the personal computer 1 to transfer each file. Therefore, the time for data transfer can be saved. Furthermore, regarding the link processing of the object file obtained by assembling the modified source file, only the modified object file is stored in the cache RAM 204 because another object file is already stored in a linked form. Link processing should be performed. Therefore, the link processing time can be shortened.

[0062]

As described above, according to the present invention, the first
The second data processing means cooperates with each other to create a program for displaying an image, and the created source program is converted into a machine language and immediately displayed on the test device. The load is distributed and each data processing device can perform its processing at a higher speed than the conventional program development device that performs the processing. Therefore, the program can be developed in a short time.

According to the second aspect of the present invention, when the object program creating means executes the assemble or link processing, the cache memory is first accessed and the corresponding data is stored in the cache memory. Since the object program creating means loads the data directly from the cache memory to process the data, the data can be accessed at high speed and the processing speed of the program can be improved.

According to the third aspect of the present invention, the source program data stored in the emulator memory is given to the image processing means of the test apparatus, and the image based on the source program data being created is sent to the second monitor means. Since it is made to output, the created source program data can be confirmed immediately. Therefore,
Easy to modify the program.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

2 is an illustrative view showing a memory map of a RAM provided in the personal computer in FIG. 1. FIG.

3 is an illustrative view showing a memory map of a ROM provided in the personal computer in FIG. 1. FIG.

4 is an illustrative view showing a memory map of a main RAM provided in the host computer in FIG. 1. FIG.

5 is an illustrative view showing a memory map of a ROM provided in the host computer in FIG. 1. FIG.

FIG. 6 is a flowchart showing the overall flow of operations when creating and modifying a program in the embodiment shown in FIG. 1 for each of a personal computer and a host computer.

FIG. 7 is a flowchart showing a continuation of the operations of the personal computer and the host computer shown in FIG.

8 is a flowchart showing an operation in the case where the host computer shown in FIG. 1 transfers a one-line input command to a personal computer and processes return command data from the personal computer.

9 is a flowchart showing a more detailed operation of the subroutine of step S301 shown in FIG. 8 and the corresponding operation of the personal computer.

10 is a flowchart showing an operation when the host computer shown in FIG. 1 executes an assemble and link process.

11 is a flowchart showing a more detailed operation of a subroutine of step S601 in FIG.

12 is a flowchart showing a continuation of the operation of the subroutine shown in FIG.

13 is a flowchart showing a more detailed operation of the subroutine of step S602 in FIG.

14 is a flowchart showing a more detailed operation of a subroutine of step S603 in FIG.

[Explanation of symbols]

 1: Personal computer 2: Host computer 3: ICE unit 4: CRT 5: Test game machine 101, 201, 301: CPU 102, 302: RAM 103, 203, 303: ROM 202: Main RAM 204: Cache RAM 205: Emulator RAM 105, 208: Parallel transmission interface 106, 207: Parallel reception interface 113: CRT controller

Claims (3)

[Claims] 1. A program development support device for converting an input source program into an object program and then executing the object program in a test device to develop the program while verifying the program being created. A first program processing means, a first data processing means, and a second data processing means communicatably coupled with the first data processing means for data transmission, wherein the first data processing means is a source program. Input means for inputting, input means for transmitting the input source program to the second data processing device, and input data from the input means for displaying on the first monitor means. Display control means, the second data processing means, the source transmitted by the transmission means A receiving means for receiving the program, an object program creating means for assembling and linking the source program received by the receiving means to convert into an object program, and an object program created by the object program creating means. A program development support device comprising: an emulator memory to be stored; and a test device control means for causing the test device to execute an object program stored in the emulator memory. 2. The first data processing means responds to a source program storage means for storing a source program input from the input means and an access request for the source program from the second data processing means. Further comprising: a transmission control means for reading the source program from the source program storage means and transmitting the source program to the transmission means, wherein the second data processing means stores the object program being created by the object program creation means. If the data to be processed next is stored in the cache memory, the object program creating means directly loads the corresponding data from the cache memory, processes the data, and stores the data in the cache memory. If not, the first data processing is performed. Generating an access request of said source program with respect to unit, the program development support apparatus according to claim 1. 3. The test apparatus, wherein an external memory cartridge storing an image processing program is detachably configured, and an image processing means for generating an image signal based on the image processing program, and the image processing means. A second monitor unit that is connected and that generates an image based on an image signal given from the image processing unit, wherein the test device control unit includes the object program stored in the emulator memory as the image processing program. The program development support apparatus according to claim 2, wherein the image based on the program being created is output to the second monitor means by being given to the image processing means as.