JPH05224970A - Error detection system - Google Patents

Abstract

PURPOSE:To enhance the processing efficiency for restoration of the faults by discriminating the position of an error when it is detected. CONSTITUTION:Registers 107-1 to 107-4 hold the results of comparison carried out between the bits of the output 101 of one of both data processors 11 and 12 of a duplex system and the bits of the output 102 of the other processor. The information held in those registers are read by each CPU of both processors 11 and 12, thereby the bit position of an error can be easily detected. Thus it is possible to easily discriminate the type of the error, a specific faulty part of hardware, etc., and to simplify the fault restore operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data processing device 2
An error detection method in a redundant system.

[0002]

2. Description of the Related Art An error detection mechanism in a conventional duplex system will be described with reference to FIG. here,
In order to distinguish the inside of the duplex system, one system is A system,
The other system is system B.

In FIG. 6, a 4-bit A-system signal 20
Comparator 203-for 1- and 4-bit B-system signal 202
1 to 203-4 are used to compare the values. Comparator 20
3-1 to 203-4 generate comparison result signals C0 to C4 of logic "0" when the two input signals are the same, and logic "1" when they are different. Comparison result signal C
0 to C4 are error detection circuits 205 each including an OR circuit.
Are combined into one signal as the detection signal 206.

More specifically, the A system signal 201 (a
0, a1, a2, a3) is (0,1,1,0),
The B system signal 202 (b0, b1, b2, b3) is (0,
1, 1, 0), the comparators 203-1 and 203-1
The comparison result signals C0 to C4 output from the circuit 03-4 are "0", "0", "0", "0", and the error detection signal 206 output through the error detection circuit 205 is logic "0". .. When the logical value is "0", the operations of the A system and B system are the same and are considered to be normal.

Further, the A system signal 201 (a0, a1, a
2, a3) is (0, 0, 1, 1), and the B-system signal 20
When 2 (b0, b1, b2, b3) is (0,1,1,1), the comparison result signals C0 to C3 output from the comparators 203-1 to 203-4 are "0". , "1",
The error detection signal 206 is "0" or "0", and the error detection signal 206 output through the error detection circuit 205 has a logic "1" value. In the case of logic "1", there is a difference between the operations of the A system and the B system, that is, an error has been detected.

In the error detecting mechanism of the conventional duplex system configured as described above, the information in which an error has occurred can be notified to the CPU or the outside as an error detection signal, but the position in which the error has occurred is determined. There is a problem that it is necessary to find some error position while verifying the circuit by giving some test patterns to the system.

[0007]

Conventionally, it is necessary to perform a test from the outside again using test data in order to detect an error occurrence position, and there is a drawback that it takes time to recover from a failure.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an error detection system capable of determining an error occurrence position at the time of error detection and facilitating failure recovery. To do.

[0009]

According to the error detecting method of the present invention, in the duplication system having the first and second data processing devices that execute the same processing in parallel, the first data A comparison means for comparing the output of a plurality of bits from the data processing device and the output of a plurality of bits of the second data processing device corresponding to this output in bit units, and a comparison result by the comparison means. Holding means for holding each bit and the first means by the comparing means
Means for detecting a bit position in which an error has occurred based on the comparison result held in the holding means when a mismatch between the outputs of the data processing device and the second data processing device is detected. And is provided.

In this error detection system, since the comparison result for each bit is held by the holding means, the error bit position can be easily detected by reading the held information. .. Normally, the error bit position can be effectively used as a guide for determining what kind of malfunction has occurred, what part of the hardware has failed, etc., so the error recovery operation can be performed by detecting the error bit position. It ’s easy, and it ’s a hur
The selection process of hardware is simplified.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an error detecting mechanism of a duplex system according to an embodiment of the present invention. The first and second data processing devices 11 and 12 compose a duplicated system (dual system) and each have the same CPU, storage device, and other various peripheral circuits. These first and second data processing devices 11,
The 12 CPUs execute the same processing in parallel by executing the same program.

An A system signal 101 (a0, a1, a2, a3) output from the first data processing device (A) 11 and a B system signal 1 output from the second data processing device (B) 12.
02 (b0, b1, b2, b3) is the four comparators 10
3-1 to 103-4 are input. That is, the comparator 1
03-1 to 103-4 respectively have corresponding bit signals (a0 and b0, of A system signal 101 and B system signal 102).
a1 and b1, a2 and b2, a3 and b3) are connected.

The comparators 103-1 to 103-4 compare the two signals respectively inputted, and if they are the same, the logic "0" is given, and if they are different, the logic "1" is given and the comparison result signals C0 to C0 are given. Output as C3. These comparators 103-1 to 103-1
Each of 103-4 can be easily realized by an exclusive OR circuit (EXOR).

The error detection circuit 105 is composed of a logical sum circuit, and has four comparators 103-1 to 10-3.
If there is a logic "1" in at least one of the comparison result signals C0 to C3 output from 3-4, a logic "1"
The error detection signal (E) is output. Also, 4
If all the comparison result signals C0 to C3 output from the one comparator 103-1 to 103-4 are logic "0", the error detection signal (E) of logic "0" is output.

The error detection signal (E) of logic "1" is a signal for notifying that an error has been detected, and is an interrupt input (INT) to the CPU of each of the data processors 11 and 12.
Is supplied to. When the error detection signal (E) becomes logic "1", an interrupt occurs in the CPU and the error processing program is executed. In the error processing program, the service to the user is stopped and the diagnosis of the system error is performed by each CPU.

If the result of the diagnosis is normal and it is a temporary failure, the erroneous portion is restored and the service to the user is restarted. If there is an abnormality, the data processing device in which the failure has occurred is disconnected from the system, and the system is operated only by the normal data processing device. In this case, the data processing device in which the failure has occurred performs a recovery process, for example, replacement of the hardware causing the error.

The four registers 107-1 to 107-4 store the results of comparison by the comparators 103-1 to 103-4, that is, the comparison result signals C0 to C3, respectively. Each of these registers 107-1 to 107-4 is
It is composed of a D flip-flop and stores the value of the comparison result signal at that time at the rising timing of the clock signal. In addition, the registers 107-1 to 107-
The value stored in each of 4 is erased by the clear signal.

Output e of registers 107-1 to 107-4
0 to e3 are seen as a part of the memory from the CPUs of the data processing devices 11 and 12, read by an error processing program, and provided as detailed error detection information to a service processor for system diagnosis. .. Next, a description will be given while showing the actual operation.

First, the A system signal 101 (a0, a1, a
2, a3) becomes (1, 1, 0, 1), and the B system signal 102
(B0, b1, b2, b3) is set to (1, 1, 0, 1).

These A system signal 101 and B system signal 102
Are compared by the comparators 103-1 to 103-4,
The values of the comparison result signals C0 to C3 are determined. In this case, all bit pairs (a0 and b0, a1 and b1, a
2 and b2, a3 and b3) are signals of the same value, so C
0, C1, C2, C3 are "0", "0", "0",
It becomes "0".

The error detection circuit 105 takes the logical sum of the comparison result signals C0 to C3. Comparison result signals C0 to C
Since all 3 are "0", the error detection signal (E) becomes "0", indicating that no error has been detected.

The registers 107-1 to 107-4 fetch and store the comparison result signals C0 to C3 at the rising edge of the clock signal. Here, since the comparison result signals C0 to C3 are all "0", the four registers 107-1 to 107-
“0” is stored in 4. Therefore, the register outputs e0, e1, e2, e3 are "0", "0", "0",
It becomes "0".

Next, the A system signal 101 (a0, a1, a
2, a3) is (1, 1, 1, 0), and B system signal 102 (b
Assume that 0, b1, b2, b3) is set to (1,1,1,1).

In this case, since the difference between a3 and b3 is detected, the comparison result signals C0, C1, C2 and C3 are
It becomes "0", "0", "0", "1". The error detection circuit 105 inputs the values indicated by the comparison result signals C0, C1, C2 and C3 and performs a logical sum. Since the comparison result signal C3 of a3 and b3 is "1", the error detection signal (E) becomes "1". Therefore, an error has been detected. This error detection signal (E) is used for each C of the duplicated data processing devices 11 and 12 to notify the occurrence of an error.
It is transmitted to the interrupt input (INT) of PU.

The registers 107-1 to 107-4 have comparison result signals C0, C1 and C at the rising edge of the clock signal.
2 and C3 are respectively captured and stored. Here, the comparison result signals C0, C1, C2 and C3 are "0", "0",
Since they are “0” and “1”, the registers 107-1 to 10-10
"0", "0", "0", and "1" are stored in 7-4. Therefore, outputs e0 of 107-1 to 107-4
e3 becomes "0", "0", "0", "1". In the error processing in each CPU of the data processing devices 11 and 12, the following processing is performed.

That is, as shown in the flow chart of FIG. 2, in the case of an interrupt due to an error detection signal (E) of logic "1" (step S11), each CPU of the data processing devices 11 and 12 The error processing program is executed, and the values of the four registers 107-1 to 107-4 are read in order to find the bit position of the output in which the error has occurred (step S12). Each CPU reads the values (e0 to e3) of the four registers 107-1 to 107-4.
By doing so, it is known that the value of e3 is “1”. Based on this information, each CPU analyzes the bit position where the error has occurred (step S13).
It can be determined that an error has occurred in the signals of 3 and b3.

In this case, each CPU has a corresponding output (a
3 or b3), the presence or absence of a fault in its own device is checked, and the CPU with the fault performs the necessary recovery processing (step S14), and if restoration is possible, the clear signal causes the register 107-1 to register. The value stored in 107-4 is reset to (0,0,0,0), and the normal operation is resumed.

As described above, in the error detection mechanism of FIG. 1, since the comparison results of the bits of the outputs 101 and 102 are held in the registers 107-1 to 107-4, the held information is stored. By reading, the error bit position can be easily detected. Therefore, it becomes possible to easily determine what malfunction has occurred, which part of the hardware has failed, and the failure recovery operation is simplified. Next, a second embodiment of the present invention will be described with reference to FIG.

Similar to FIG. 1, four comparators 103-1 to 103-3 are provided.
103-4 includes A system signals 101 (a0, a1, a2,
a3) and a pair of signals of the B system signal 102 (b0, b1, b2, b3) (a0 and b0, a1 and b1, a2 and b2).
a3 and b3) are respectively connected. Comparator 103
-1 to 103-4 compare two input signals, and if they are the same, logic "0", and if they are different, logic "1"
Are output as comparison result signals C0 to C3, respectively. Each of these comparators 103-1 to 103-4 can be easily realized by an exclusive OR circuit (EXOR).

Registers 108-1 to 108-4 have comparison result signals C0 to C0 from the comparators 103-1 to 103-4.
C3 is stored. In this case, the registers 108-1 to 1
The current storage state (outputs e0 to e3) of 08-4 is fed back to the input side, and the comparison result signal of logic "1" is accumulated and held. Further, by the status setting signals S0 to S3, the registers 108-1 to 108-
4 can be set to "1" forcibly. This is performed for the purpose of an operation test of the error processing program.

As shown in FIG. 4, each of these registers 108-1 to 108-4 is composed of a D flip-flop 201 and a 3-input logical sum circuit 202, and the rising timing of the clock signal. Then, the value of the output of the OR circuit 202 at that time is stored. Therefore,
When the state setting signal Sn (n = 0 to 3) is “0”,
Once the comparison result signal Cn (n = 0 to 3) of “1” is input, the D flip-flop 201 receives “1” even if the comparison result signal Cn input thereafter is “0”. Is retained. Also, the registers 108-1 to 10
The value stored in each of 8-4 is the D flip-flop 2
It is erased by the clear signal supplied to 01.

Output e of registers 108-1 to 108-4
0 to e3 are seen as a part of the memory from the CPUs of the data processing devices 11 and 12, and are read regularly by the error monitoring program, or a server for performing system diagnosis.
It is provided to the bisprocessor as detailed error detection information.

The error monitoring program periodically reads the registers 108-1 to 108-4 to check the duplex system for errors. If there is an error, the error processing program is executed. The error handling program stops the service to the user and diagnoses the system error. If the result of the diagnosis is normal and it is a temporary failure, the erroneous part is restored and service to the user is restarted. If there is an abnormality, replace the faulty hardware or isolate it and then restore the system. Next, a description will be given while showing the actual operation.

First, the A system signal 101 (a0, a1, a
2, a3) becomes (1, 1, 0, 1), and the B system signal 102
(B0, b1, b2, b3) is set to (1, 1, 0, 1).

These A system signal 101 and B system signal 102
Are compared by the comparators 103-1 to 103-4,
The values of the comparison result signals C0 to C3 are determined. In this case, all bit pairs (a0 and b0, a1 and b1, a
2 and b2, a3 and b3) are signals of the same value, so C
0, C1, C2, C3 are "0", "0", "0",
It becomes "0".

The registers 108-1 to 108-4 fetch and store the comparison result signals C0 to C3 at the rising edge of the clock signal. Here, since the comparison result signals C0 to C3 are all "0", the four registers 108-1 to 108-
“0” is stored in 4. Therefore, the register outputs e0, e1, e2, e3 are "0", "0", "0",
It becomes "0".

Here, the error monitoring program reads the registers 108-1 to 108-4 and analyzes the system state on the CPU. Registers 108-1 to 108
Since all -4 are "0", it is recognized as normal and the normal operation is resumed.

Next, the A system signal 101 (a0, a1, a
2, a3) is (1, 1, 1, 0), and B system signal 102 (b
Assume that 0, b1, b2, b3) is set to (1,1,1,1). In this case, since the difference between a3 and b3 is detected, the comparison result signals C0, C1, C2, C3
Becomes "0", "0", "0", "1".

The registers 108-1 to 108-4 receive the comparison result signals C0, C1 and C at the rising edge of the clock signal.
2 and C3 are respectively captured and stored. Here, the comparison result signals C0, C1, C2 and C3 are "0", "0",
Since they are "0" and "1", the registers 108-1 to 108-10
"0", "0", "0", "1" are stored in 8-4. Therefore, the outputs e0 to e3 of the registers 108-1 to 108-4 are "0", "0", "0", "1".

Register 10 storing error state "1"
The output 8-4 holds the value "1" indicating that an error has occurred in the next cycle due to the feedback of the output e.

Next, the A system signal 101 (a0, a1, a
2, a3) is (0, 0, 1, 1), and the B system signal 102 (b
0, b1, b2, b3) is set to (0, 0, 0, 1). The comparison result signals C0 to C3 are "0",
It becomes "0", "1", "0".

The logical sums of the comparison result signals C0 to C3 and the feedback output signals e0 to e3 are input to the inputs of the registers 108-1 to 108-4. CPU now
(S0 to S3 =
"0"), comparison result signals C0 to C3 (0,0,1,0)
And output signals e0 to e3 (0, 0,
The value obtained by ORing with 0, 1) is selected. Therefore,
The inputs of the registers 108-1 to 108-4 are "0",
The values become "0", "1", "1", and these values are stored in the registers 108-1 to 108-4 at the rising edge of the next clock.

The CPUs of the data processing devices 11 and 12 are
As shown in the flow chart of FIG. 5, the error monitoring program registers 1 for each checkpoint.
08-1 to 108-4 are read (steps S21, S
22), it is checked whether or not an error has occurred depending on whether or not "1" is held (step S23). Register 10
When "1" is held in any of 8-1 to 108-4, it is determined that an error has occurred, and the error processing program is executed. In addition, the register 108-1
If "1" is not held in any of the items 108 to 108-4, it is determined that no error has occurred, and the process ends. In this example, since "1" is held in the registers 108-3 and 108-4, the error processing program is executed.

In the error processing, each CPU analyzes the bit position in which an error has occurred based on the outputs e2 and e3 holding "1" in the read registers 108-1 to 108-4. Is performed (step S24), and it is determined that an error has occurred in a3, b3, and a4, b4.

In this case, each CPU examines the corresponding output (a3, a4 in the data processing device 11 and b3, b4 in the data processing device 12) for a fault in its own device, and the CPU in which the fault has occurred is After performing necessary recovery processing (step S25), if recovery is possible, the value stored in the registers 108-1 to 108-4 is reset to (0,0,0,0) by a clear signal. , Return to normal operation.

According to this error detection mechanism, since the occurrence of an error is accumulated and stored in the registers 108-1 to 108-4, the CPU can register the register 10 at any time.
The error information stored in 8-1 to 108-4 can be checked. That is, the error can be detected as a register read, which is a normal operation of the CPU, instead of the error notification by the interrupt from the error detection mechanism to the CPU as in the first embodiment shown in FIG.

Specifically, the processing is divided into blocks, and check points are set between the blocks. When the process reaches the checkpoint, the environment in the block is saved. Then, the registers 108-1 to 108
-4 is checked, and if there is no error, the process proceeds to the next block. If there is no error, register 108-1 with a clear signal.
It is possible to avoid a temporary failure by clearing the error state held in 108-4, returning to the previous checkpoint, restoring the environment in that block, and re-executing the processing.

Further, by accumulating and holding the information of disagreement from the results of comparing the outputs in this way, if the statistics of the error occurrence positions are collected over a plurality of check points, the statistical results are displayed. It can also be used as a guide for when to replace hardware and for system reliability.

Although the output contents of the A-system output 101 and the B-system output 102 are not specified in the above description, for example, the A-system output 101 and the B-system output 102 are functional (data and address). Etc.),
Error detection can be performed by providing an error detection mechanism for each section.

Further, here, the data processing devices 11 and 1 are
Although each of the two CPUs themselves read the register by executing the error processing program, it is also possible to perform the register read by using the service processor provided in the duplex system.

[0052]

As described above in detail, according to the present invention, it is possible to easily obtain detailed error position information regarding error detection in a duplex system.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an error detection mechanism according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram showing the configuration of an error detection mechanism according to the second embodiment of the present invention.

FIG. 4 is a circuit diagram showing an example of a specific configuration of a register used in the second embodiment.

FIG. 5 is a flowchart for explaining the operation of the second embodiment.

FIG. 6 is a block diagram showing a conventional error detection mechanism.

[Explanation of symbols]

101 ... A system signal, 102 ... B system signal, 103-1 to 1
03-4 ... comparator, 105 ... error detection circuit, 107-
1 to 107-4, 108-1 to 108-4 ... Registers.

Claims (3)

[Claims] 1. In a duplex system having first and second data processing devices that execute the same processing in parallel, an output consisting of a plurality of bits from the first data processing device and this output are provided. Comparing means for comparing the corresponding output of the second data processing device consisting of a plurality of bits on a bit-by-bit basis, holding means for holding the comparison result by the comparing means for each bit, and the comparing means When a mismatch between the outputs of the first data processing device and the second data processing device is detected, the bit position in which an error has occurred is detected based on the comparison result held in the holding means. An error detection method for a duplex system, comprising: 2. A first data processing device and a second data processing device having the same circuit are duplicated, and the first data processing device and the second data processing device are duplicated. -In a duplex system in which the same program is executed in the data processing device, the output of the first data processing device and the output of the second data processing device are compared, and an error is detected due to a mismatch. Means for holding, for each bit, the result of comparing the output of the first data processing device consisting of a plurality of bits and the output of the second data processing device consisting of a plurality of bits; When a mismatch occurs between the outputs of the second data processing device, the first and second data processing devices are interrupted and an error occurs in each of the first and second data processing devices. And a means for notifying and holding in the holding means that is activated in response to the notification. An error detecting method for a duplex system, comprising means for detecting a bit position where an error has occurred based on the compared result information. 3. A first data processing device and a second data processing device having the same circuit are duplicated, and the first data processing device and the second data processing device are duplicated. -In a duplex system in which the same program is executed in the data processing device, the output of the first data processing device and the output of the second data processing device are compared, and an error is detected due to a mismatch. Holding means for accumulating and holding, for each bit, the disagreement information between the plurality of bits of the output of the first data processing apparatus and the plurality of bits of the output of the second data processing apparatus; The duplication is characterized by further comprising: means for periodically reading the inconsistency information accumulated and retained in the retaining means, and detecting the presence / absence of an error and the bit position in which the error has occurred based on the inconsistency information. System error detection method.