JPH0522299A - Node equipment for indefinite communication network - Google Patents

Abstract

PURPOSE:To prevent a path fixed in error due to successive change in an ACK input means by improving the method in accordance with the patent whose disclosure number is 1-215149 (1989) in the processing limiting the ACK input means to one. CONSTITUTION:In a node equipment for an indefinite communication network in which a first come input detection means 21 identifying an input means to which a signal arrives at first among plural input means and an input detection means 22 having selection means 25,26,27 selecting one input means alternatively according to priority when plural return signals are received and detecting whether or not the return signal reaches the input means through a reception line after lapse of a prescribed period from the identification by the first come input detection means 21 are provided to start an ACK sequence to fix a path with respect to relevant input and output means, a fixing means 34 is provided, which keeps fixedly the alternative selection of the input means with priority by the selection means 25,26,27 to start the ACK sequence.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a node device of an irregular communication network applicable to multimedia communication represented by a local area network (LAN).

[0002]

2. Description of the Related Art Conventionally, there are various types of communication networks of this type, and one of them is a multi-channel lattice communication network based on the analogy of biological nerve cells.
-74349 publication. This is an undefined communication network (LADERNET = LatticeDyn) in which a communication control element for multi-input / single-output signals is connected as a node to a multi-coupling structure.
amic Architecture Network), and each node has a communication network form that transfers digital signals by first-come-first-served logic.

This grid communication network has many advantages, but is particularly excellent in the following points. One is the high degree of freedom in network topology due to the multi-connection structure. Therefore, the fault tolerance is high. That is, even if there is a failure in a part of the network, communication can be properly secured by another route. Second, the first-come-first-served logic selects an optimal communication path (shortest path) for each communication. In addition, this system adopts a multi-channel method in which a plurality of connection channels are simultaneously established in a node and efficiently establishes full-duplex communication.
Therefore, the present system is effectively applied to the physical layer and the network layer of OSI (Open System Interconnection), for example.

Regarding such an irregular communication network, there is one disclosed in Japanese Patent Application Laid-Open No. 1-215149 as an improvement of the start control unit in the node device in order to prevent double connection. That is, in this publication, when a plurality of ACK signals indicating the arrival of a back signal and performing an ACK sequence for path fixing are returned before the path fixing, the priority is given to 1 I'm trying to decide.

[0005]

However, the first AC
ACK from when the K signal is input until the path is fixed
There is a possibility of an erroneous operation in which an incorrect path is fixed due to a port change, or when the timeout timer is changed, the ACK port changes after the timer is determined.

[0006]

A first-come-first-served input detecting means for identifying the input means having the earliest signal from among the plurality of input means, and one input means according to the priority order when a plurality of return signals are received. And an input detection means for detecting whether or not a return signal has arrived through the reception line to the input means after a predetermined period has elapsed from the identification by the first-arrival input detection means, which has a selection means for selectively selecting. In a node device of an irregular communication network in which a path is fixed between corresponding input / output means, the selective selection of the input means according to the priority order by the selection means is fixedly maintained to start the ACK sequence. A fixing means was provided.

[0007]

After the selection means selectively selects the input means in accordance with the priority order, the fixing means keeps the selected state fixed, so that a plurality of recovered signals arrive after the ACK sequence starts. Even if the input means does not change, the correct path can be fixed by the first one.

[0008]

An embodiment of the present invention will be described with reference to the drawings. This embodiment is intended for a node device of an irregular communication network as disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-215149, and the basic schematic configuration of each node device 1 is shown in FIG.
FIG. 1 shows the configuration of the start control unit, which is one of the constituent elements and is included in the gist of the invention.

First, a configuration example of each node device 1 will be described with reference to FIG. 2. An input port (input means) 2 to which a receiving line from a transmission line (not shown) is connected and a transmission line to the transmission line are provided. It has an output port (output means) 3 to be connected, and both are connected to each other via a switching gate section 4. The input port 2 has in this embodiment eight receive or input channels i0 to i7, and the output port 3 correspondingly has eight transmit or output channels o0 to o.
Have 7. As a result, the node device 1 includes all the other node devices 1 and terminals (not shown) via the transmission line.
Up to two can be connected. Among the output channels o0 to o7, the output channels having the same numbers as the input channels i0 to i7, that is, the "corresponding" output channels are connected to the transmission path of the same route.

The switching gate section 4 includes any one of the input channels i0 to i7 and the output channels o0 to o.
7 is a gate circuit for selectively interconnecting any of the seven. The input port 2 is also connected to the start control unit 6 and the end control unit 7 via the control gate unit 5. The control gate unit 5 appropriately supplies the signal from the input port 2 to the start control unit 6 and the control signals from the start control unit 6, the failure storage unit 8, and the end control unit 7 to the switching gate unit 4 and the end control unit 7, respectively. It is a gate circuit that controls connection. As will be described in detail later, the start control unit 6 is a functional unit that identifies the input channel that the input signal arrives first and that detects whether or not there is an input signal in each input channel. Further, the start control unit 6 serves as an output means, and when an input signal arrives at any of the input channels i0 to i7 in the idle state, the channel where the input signal comes first (first-come-first-served input channel) is the first-come-first-served logic. And the signal received from the first-arrival input channel is transmitted to all output channels other than the corresponding output channel. The termination control unit 7 is a circuit that detects that there is no input signal in the input channel of the already set communication path and performs termination processing of the communication. Switching gate unit 4, start control unit 6, and end control unit 7
Are mutually connected by a gate set bus 9.

An active signal output section 10 is also connected to the switching gate section 4, which is a start control section 6.
Is also connected to. The start control unit 6 and the end control unit 7 are also connected to a fault storage unit 8 that stores a channel in which a fault has occurred. The fault storage unit 8 is also connected to the gate set bus 9.

The switching gate unit 4, the control gate unit 5, the start control unit 6, the end control unit 7, the active signal output unit 10 and the fault storage unit 8 are controlled by a sequence control unit 11 including the above, which controls the entire apparatus. To be done.

Next, the start controller 6 will be described with reference to FIG. FIG. 1 shows an example in which the input and output are each 4 channels, and when roughly classified, a first-arrival input signal detection unit (first-arrival input signal detection means) 21 and an input signal detection unit (input signal detection means) 22 are provided. Become. First-arrival input signal detector 2
Reference numeral 1 denotes a functional unit that identifies the first input signal among the input channels i0 to i3 according to the first-come-first-served logic, but this is the same as the above-mentioned publication method, and the details will be omitted here. On the other hand, the input signal detector 22 is a circuit for detecting whether or not an input signal arrives at the input port 2, and basically, four D-type flip-flops 23 for each channel are provided.
And the flip-flops 24 that collect the negative outputs and 4
One NAND gate 25 and three NAND gates 26
And a pair of NAND gates 27 and 28 each constituting a selecting means, a four-input NOR gate 29, and an inverter 30.

First, the D-type flip-flop 23 is a circuit for holding the state of the input channel where the input signal arrives, and the flip-flop 24 stores the output states of these D-type flip-flops 23 and outputs their S inputs. It is a circuit that sets it to a low level and fixes that state. Further, the output of the D-type flip-flop 23 is reported to the failure storage unit 8. The 4-input NOR gate 29 takes the logical sum of the outputs of the flip-flops 22 and transmits the arrival of the first recovery signal as an ACK signal to the sequence control unit 11 via the inverter 30.

Further, the group of NAND gates 27 is the above-mentioned D
The type flip-flop 22 is a circuit for giving a priority to the outputs, and the other group of NAND gates 28 is a circuit for masking the priority. The switch 31 is provided so as to enable priority assignment for a single path when it is off and mask this priority because it is multipath when it is on. The state of the switch 31 is
The NAND gate 27 is directly applied to the NAND gate 28 through an inverter 32, the outputs of the two NAND gates 27 and 28 are narrowed to one by the NAND gate 26, and the first-arrival input signal is passed through the NAND gate 26. It is input to the NAND gate 33 in the detection unit 21.

Here, any of the input channels i0 to i7
When the first outgoing signal arrives at, the start control unit 6 detects this by the input signal detection unit 22, and the first arrival input signal detection unit 21 identifies the first arrival input channel. The first forward signal is the flip-flop 2 of the input signal detector 22.
Detected at 1. The identified first-arrival input channel is connected to all output channels except the output channel corresponding to the first-arrival input channel by the switching gate unit 4, and the first outgoing signal is broadcast.

As for the first return signal returned in response to the first forward signal, the start controller 6 similarly identifies the first return signal. This identification is done by detecting the reception of an active signal within a given time period and monitoring the signal arriving at the input channel after the elapse of the next given time period. The input channel in which the first recovery signal is detected first is connected to the output channel corresponding to the first-arrival input channel by the switching gate unit 4. Then, the other channels are opened, and finally one communication path is fixed. The single path mode connection setting connects the input and output channels in a one-to-one path in this way. In the multipath mode, the switching gate unit 4 sets a communication path between three or more output channels.

Here, the first return signal is also detected by the input signal detector 22. That is, after the lapse of a predetermined period,
When a signal arrives while waiting for the arrival of the first recovered signal, an ACK signal is output from the NOR gate 29 through the inverter 30, and the sequence control unit 11 responds to this by an ACK sequence, that is, a pair of input / output. The process moves to a path fixing sequence for fixing the communication path between channels.

At this time, tentatively, the gate groups 26, 27, 2
Assuming that there is no lockout circuit composed of 8, if any signal arrives from another input channel before the ACK sequence is activated and the communication path is fixed, this erroneous signal causes the flip-flop 23 to be set. There is a possibility that an incorrect communication route will be set,
With the lockout function, even if an input signal is input to a plurality of input channels at the time when the return signal should arrive, the transition to the path setting is limited to one input channel. That is, after a lapse of a predetermined period, the input channel in which the first recovered signal arrives is stored in the flip-flop 23 of the input signal detector 22. The input channel is normally notified from the NAND gate 25 to the first-arrival input signal detector 21. However, in the detection period of the first recovery signal, the true first
An input signal that is not the second recovery signal may be input to another input channel. This input signal is similarly input to the flip-flop 23. Therefore, the plurality of input channels from which these input signals arrive are
By the lockout function of the NAND gate 27 of No. 2, any one is forcibly selected according to a predetermined priority.
The selected one input channel does not necessarily have the true recovery signal input, but in any case, only one NAND gate 25 corresponding to the single input channel is the NAND gate of the first-arrival input signal detection unit 21. 3 will be selectively activated. Therefore, in the switching gate unit 4, the connection between the pair of input / output channels is performed.

As described above, according to the already proposed method, although the double connection can be prevented, it does not guarantee the true path fixing. As described in the problem, the path fixing is performed after the first ACK signal is input. There is a possibility of erroneous operation such that the ACK port changes until the time is reached and an incorrect path is fixed, or when the timeout timer is changed, the ACK port changes after the timer is determined. That is, in FIG. 1, when the flip-flop 23 detects the ACK signal, the gate groups 26, 27, 28
Is prioritizing it and flip-flop 2
If any one of 3 is set, the inverter 30
The level becomes ACK sequence, and after that, when a plurality of ACK signals enter the flip-flop 23, the ACK ports may change one after another.

Therefore, in this embodiment, the flip-flop 2 is used.
Since the output of the 4-input NOR gate 29 as well as the output of 4 is used for the S input control of the flip-flop 23, the AND gate 34 serving as a fixing means is provided. Therefore, when the 4-input NOR gate 29 outputs the ACK sequence to start the ACK sequence, the outputs of the AND gates 34 are all at the L level.
The value of 3 is set and held. Therefore, even if a plurality of ACK signals are input after the sequence is started, the ACK port does not change, and erroneous path fixing is prevented even when the path is fixed thereafter. Therefore, even if the timeout timer is variable, ACK
It is possible to perform the two operations of limiting the port and fixing the path without contradiction.

[0022]

As described above, according to the present invention, the fixing means for fixedly maintaining the selective selection of the input means according to the priority order by the selection means and starting the ACK sequence is provided. The input means does not change even when a plurality of recovered signals arrive, the correct path can be fixed by the earliest one, and the malfunction at the time of determining the timer for the timeout can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of a start control unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a node device.

[Explanation of symbols]

 2 input means 3 output means 21 first-arrival input detection means 22 input detection means 25, 26, 27 selection means 34 fixing means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location 8020-5K H04L 13/00 305 D

Claims (1)

Claim: What is claimed is: 1. A first-come-first-served input detecting means for identifying an input means that receives a signal first among a plurality of input means, and one input according to a priority order when a plurality of return signals are received. And an input detecting means for detecting whether or not a backward signal has arrived through the receiving line to the input means after a predetermined period has passed from the identification by the first-arrival input detecting means. In the node device of the irregular communication network for starting the ACK sequence for fixing the path between the corresponding input / output means, the selective selection of the input means according to the priority order by the selection means is maintained fixed. Then ACK
A node device of an irregular communication network, characterized in that a fixing means for starting a sequence is provided.