JPH0521790A - Manufacture of vertical-type transistor - Google Patents

Abstract

PURPOSE:To provide a method for producing a vertical-type transistor where wiring to a gate electrode can be easily made and a withstand voltage between a source and a drain is high. CONSTITUTION:An epitaxial silicon layer 24 which is subjected to patterning in ring shape is formed on an N<-> diffusion region 23 at a silicon substrate 21 which is subjected to N<-> implantation. A source 28 is formed in contact with the N<-> diffusion region 23 of the silicon substrate 21. An oxide silicon layer 29 is formed and flattened and an epitaxial silicon layer 30 is formed on ring-shaped the epitaxial silicon layer 24 and a polysilicon layer 31 is formed on the oxide silicon layer 29 and N<-> implantation is made. An inside of the ring-shaped epitaxial silicon layer 24 is etched and a gate electrode 33 is formed. With a gate electrode 33 as a mask, N<+> implantation is made, thus forming a drain 34 which is in contact with the N<-> diffusion region 30. Therefore, a vertical-type transistor in LDD structure can be formed and a withstand voltage between the source and the drain can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method of manufacturing a vertical transistor.

[0002]

2. Description of the Related Art Transistor structures are roughly classified into vertical transistors and planar transistors. Also,
As one of the structures of the planar transistor, there is a light doped drain (LDD) structure in which generation of hot carriers is suppressed and the breakdown voltage between the source and the drain is improved. The vertical transistor and the planar transistor having the LDD structure are manufactured by the following manufacturing process. FIG. 4 is a manufacturing process diagram of a conventional vertical transistor. Hereinafter, a conventional method for manufacturing a vertical transistor will be described with reference to FIG.

As shown in FIGS. 4A and 4B, a silicon pillar 2 is formed on a silicon substrate 1 by using a trench technique. Next, as shown in FIG. 4C, the gate insulating film 3 is formed on the silicon pillar 2 by thermal oxidation or vapor phase epitaxy.
Then, the N ⁺ polysilicon layer 4 is formed by vapor phase epitaxy. Then, the N ⁺ polysilicon layer 4 is entirely etched by a reactive ion etching (RIE) method to form a gate electrode 4 ′ around the silicon pillar 2 as shown in FIG. 4D.

Next, as shown in FIG. 4E, a drain electrode 5 and a source electrode 6 are formed by ion implantation.
After that, a vertical transistor is formed by the same process as a normal metal oxide semiconductor field effect transistor (hereinafter abbreviated as MOSFET) manufacturing process. The vertical transistor manufactured in this manner has a characteristic that it occupies a small area because it is a vertical transistor and that the gate surrounds the silicon pillar 2 so that good characteristics can be obtained. ..

FIG. 5 is a manufacturing process diagram of a planar transistor having an ordinary LDD structure. Hereinafter, according to FIG. 5, LDD
A method of manufacturing a planar transistor having a structure will be described.
As shown in FIGS. 5A and 5B, a field oxide film 13, a gate insulating film 12 and a gate electrode 14 are formed on a silicon substrate 11 by a normal MOSFET manufacturing process.

Next, as shown in FIG. 5C, a low concentration diffusion layer 15 is formed by ion implantation. Furthermore, FIG.
As shown in FIG. 5D, after forming the spacer 16 with a silicon oxide film, as shown in FIG. 5E, the source electrode 17 and the drain electrode 18 are formed by ion implantation. Thus, the low-concentration diffusion layer 15, at the source end and the drain end,
15 is provided to improve the withstand voltage between the source and the drain.

[0007]

However, in the above-described conventional method of manufacturing a vertical transistor, the N ⁺ polysilicon layer 4 formed on the silicon pillar 2 is entirely etched to form the gate electrode 4 '. Therefore, the gate electrode 4'in the obtained vertical transistor is formed in a very thin film shape on the side wall of the silicon pillar 2. Therefore, it is necessary to connect to the gate electrode 4 ', which is a very thin film, and there is a problem that it is extremely difficult to contact the gate electrode 4'. Further, the vertical transistor created by the above-described conventional method for manufacturing a vertical transistor,
There is a problem that the breakdown voltage between the source and drain decreases as the channel length decreases.

Therefore, an object of the present invention is to provide a method of manufacturing a vertical transistor in which wiring to a gate electrode is easy and a withstand voltage between a source and a drain is high.

[0009]

In order to achieve the above object, a method of manufacturing a vertical transistor according to the present invention is a method of manufacturing an N ^- diffusion obtained by growing an epitaxial silicon layer after N ^- implantation into a silicon substrate. The epitaxial silicon layer on the region is patterned into a ring plate shape, and then the sidewall of the ring plate shaped epitaxial silicon layer is covered with silicon oxide, and then N ⁺ implantation is performed on the silicon substrate to contact the N ⁻ diffusion region. After forming the source region and then planarizing the whole with a silicon oxide layer to expose the surface of the ring plate-shaped epitaxial silicon layer, an epitaxial silicon layer is formed on the ring plate-shaped epitaxial silicon layer, A polysilicon layer is co-grown on the planarized silicon oxide layer and the N the interstitial silicon layer and a polysilicon layer ^- injected, then, inside the gate insulating film of the ring plate-shaped epitaxial silicon layer by removing the interior of polysilicon and silicon oxide of the ring plate-shaped epitaxial silicon layer and the gate It is characterized by forming an electrode, patterning the gate electrode, and then implanting N ⁺ to form a drain region in contact with the N ⁻ diffusion region.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a vertical transistor structure having an LD.
By adopting the D structure, the breakdown voltage between the source / drain is improved and the wiring to the gate electrode is facilitated. Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments. 1 to 3 are manufacturing process diagrams of a vertical transistor according to this embodiment. Hereinafter, a method of manufacturing a vertical transistor will be described with reference to FIGS.

As shown in FIGS. 1A and 1B, after patterning a silicon substrate 21 with a photoresist layer 22, P (phosphorus) ions are implanted to form an N ⁻ diffusion region 23. .. The N ⁻ diffusion region 23 will be a low concentration diffusion layer at the source end of the source formed on the silicon substrate 21 later.

Next, after the photoresist layer 22 is removed, as shown in FIG. 1C, epitaxial silicon is grown to 3000 angstroms to form an epitaxial silicon layer 24. Then, S is formed on the epitaxial silicon layer 24 by using a chemical vapor deposition (CVD) method.
After forming 4000 angstrom of iO ₂ and then patterning into the shape of the channel region, an etching mask 25 of the epitaxial silicon layer 24 is formed. Here, originally, the etching mask 25 has a square ring shape. However, in the figure, since the square-shaped etching mask 25 is cut at substantially the center in order to display a cross section, the etching mask 25 has a U-shaped planar shape. The shape of the etching mask 25 is not limited to the above-mentioned square shape.

Next, as shown in FIG. 1D, the epitaxial silicon layer 24 is etched using the etching mask 25 as a mask. Then, a SiO ₂ film having a thickness of 2000 angstrom is further formed by the CVD method.
The O ₂ layer 26 is formed.

Next, as shown in FIG. 2 (e), the RIE is performed.
The entire surface is etched by the method to leave the SiO ₂ layer 26 on both sides and the upper portion of the epitaxial silicon layer 24. However,
The SiO ₂ layer on the epitaxial silicon layer 24 was the etching mask 25. After that, the photoresist layer 2 is formed on the exposed silicon substrate 21.
After patterning with 7, the photoresist layer 27
As (arsenic) is ion-implanted using as a mask to form an N ⁺ diffusion layer, which is used as the source 28. Thus, N ⁻ diffusion region 2
By forming the source 28 in contact with No. 3, a low concentration diffusion region is formed at the source end.

Next, as shown in FIG. 2 (f), after removing the photoresist layer 27, SiO _{2 is formed} by a CVD method.
To a thickness of 6000 angstroms. Then, the SiO ₂ layer 29 is flattened by an etch back method or the like.
To form. Thus, the surface of the epitaxial silicon layer 24 is exposed. Then, as shown in FIG. 2G, an epitaxial silicon layer 30 is grown on the epitaxial silicon layer 24, and a polysilicon layer 31 is grown on the SiO ₂ layer 29 at the same time as the epitaxial silicon layer 30. After that, P (phosphorus) is ion-implanted on the entire surface and N ⁻ diffused. The N ^- diffusion region thus obtained is
It becomes a low-concentration diffusion region at the drain end of the drain to be formed later.

Next, as shown in FIG. 3H, the epitaxial silicon layer 30 and the polysilicon layer 31 corresponding to the drain region are patterned. And FIG.
As shown in (i), the SiO ₂ layer 29 surrounded by the epitaxial silicon layer 24 is etched using a photoresist as a mask. Then, after removing the photoresist used as the mask at that time, a thermal oxidation method and C
The gate insulating film 32 is formed by the VD method. Next, after forming doped polysilicon in the ring-shaped epitaxial silicon layer 24, patterning is performed to form a gate electrode 33. Thus, in this embodiment,
Since the gate electrode 33 is formed inside the ring-shaped channel layer, it is possible to easily form a contact hole in the gate electrode 33 for metal wiring.

Next, using the gate electrode 33 as a mask, As is ion-implanted to form an N ⁺ diffusion region and the drain 3 is formed.
Set to 4. As a result, the N ⁻ diffusion region remains only at the drain end. Thus, by forming the drain 34 in contact with the N ⁻ diffusion region 30, a low concentration diffusion region is formed at the drain end. That is, in this embodiment, as described above, the LDD structure is obtained by forming the low-concentration diffusion regions at the source end and the drain end, so that the breakdown voltage between the source / drain is improved.

Thereafter, a SiO ₂ layer 36 is formed by a normal MOSFET manufacturing process, and then metal wirings 35, 35, 35 are formed on the gate electrode 33, the source 28 and the drain 34, as shown in FIG. 3 (j). The vertical transistor is completed.

As described above, in this embodiment, the epitaxial silicon layer 24 is grown after N ⁻ is implanted into the silicon substrate 21. Then, the epitaxial silicon layer 24 on the N ⁻ diffusion region 23 is patterned into a ring shape, and N ⁺ implantation is performed on the silicon substrate 21 to form the source 28. Next, after forming the SiO ₂ layer 29 and burying the entire surface to flatten the surface, the epitaxial silicon layer 30 and the polysilicon layer 31 are further grown simultaneously. Then, N ^{− is} injected into the epitaxial silicon layer 30 and the polysilicon layer 31 for patterning, and the SiO ₂ layer 2 inside the ring-shaped epitaxial silicon layer 24 is patterned.
9 and the polysilicon layer 31 are removed. Next, the above S
A gate electrode 33 is formed inside the epitaxial silicon layer 24 after the iO ₂ layer 29 is removed. Further, N ⁺ implantation is performed using the patterned gate electrode 33 as a mask to form the drain 34.

Therefore, the low concentration diffusion regions 23 and 30 in which N ⁻ is implanted are formed at the source end and the drain end of the vertical transistor formed as described above, and L
A vertical transistor having a DD structure can be obtained. Therefore, the source decreases as the channel length decreases.
/ The breakdown voltage between drains can be improved. In addition, since the gate electrode 33 is formed inside the ring-shaped channel layer, the surface area of the gate electrode 33 can be increased, and contact / wiring to the gate electrode 33 becomes easy.

[0021]

As apparent from foregoing description, the manufacturing method of the vertical transistor of the present invention, N ^- N in implanted silicon substrate ^- by forming an epitaxial silicon layer is patterned in a ring plate shape on the diffusion region After coating the side wall of the ring-plate-shaped epitaxial silicon layer with silicon oxide, N ⁺ implantation is performed on the silicon substrate to form a source region in contact with the N ⁻ diffusion region, and then the entire surface is flattened with the silicon oxide layer. Then, an epitaxial silicon layer is co-grown on the ring plate-shaped epitaxial silicon layer and a polysilicon layer is co-grown on the flattened silicon oxide layer, and N ⁻ implantation is performed. By removing the polysilicon and the silicon oxide in the silicon layer, the ring plate epitaxy is performed. Since a gate electrode is formed inside the silicon layer and N ^{+ is} injected after patterning the gate electrode to form a drain region in contact with the N ^- diffusion region, a low concentration diffusion region is formed at the source end and the drain end. Are formed to obtain a vertical transistor having an LDD structure. Therefore, it is possible to provide a vertical transistor having a high breakdown voltage between the source and the drain. Also,
Since the gate electrode is formed inside the ring plate-shaped channel layer, the surface area of the gate electrode can be increased. Therefore, the contact and wiring to the gate electrode become easy.

[Brief description of drawings]

FIG. 1 is an explanatory view of an example of a manufacturing process according to a method of manufacturing a vertical transistor of the present invention.

FIG. 2 is an explanatory diagram of the manufacturing process following FIG.

FIG. 3 is an explanatory diagram of the manufacturing process following FIG.

FIG. 4 is an explanatory view of a manufacturing process of a conventional vertical transistor.

FIG. 5 is an explanatory diagram of a manufacturing process of a planar transistor having an LDD structure.

[Explanation of symbols]

21 ... silicon substrate, 23 ... N ^- diffusion region, 24, 30 ... epitaxial silicon layer, 25,26,29,36 ... SiO ₂ layer, 28 ... Source, 31 ... polysilicon layer, 32 ... gate insulating film, 33 ... Gate electrode, 34 ... Drain, 35 ... Metal wiring.

Claims (1)

1. An epitaxial silicon layer is grown after N ⁻ implantation into a silicon substrate, and the obtained epitaxial silicon layer on the N ⁻ diffusion region is patterned into a ring plate shape. After covering the side wall of the ring-plate-shaped epitaxial silicon layer with silicon oxide, N ⁺ implantation is performed on the silicon substrate to form a source region in contact with the N ⁻ diffusion region, and then the entire surface is planarized with the silicon oxide layer. And exposing the surface of the ring-plate-shaped epitaxial silicon layer, an epitaxial silicon layer is simultaneously grown on the ring-plate-shaped epitaxial silicon layer, and a polysilicon layer is simultaneously grown on the flattened silicon oxide layer. by, N on the epitaxial silicon layer and a polysilicon layer ^- injected, then the Li Gupureto shaped internal polysilicon and silicon oxide of the epitaxial silicon layer is removed to form an internal gate insulating film and the gate electrode of the ring plate-shaped epitaxial silicon layer, and N ⁺ implanted after patterning of the gate electrode N ^- A method of manufacturing a vertical transistor, comprising forming a drain region in contact with a diffusion region.