JPH05216947A - Block division system - Google Patents

Block division system

Info

Publication number
JPH05216947A
JPH05216947A JP4020840A JP2084092A JPH05216947A JP H05216947 A JPH05216947 A JP H05216947A JP 4020840 A JP4020840 A JP 4020840A JP 2084092 A JP2084092 A JP 2084092A JP H05216947 A JPH05216947 A JP H05216947A
Authority
JP
Japan
Prior art keywords
division
block diagram
dividing
designing
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4020840A
Other languages
Japanese (ja)
Inventor
Hiroki Yokohama
宏紀 横▲浜▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4020840A priority Critical patent/JPH05216947A/en
Publication of JPH05216947A publication Critical patent/JPH05216947A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To perform a division designing work on a block diagram editor, to reduce the man-hour of work processes, to improve the quality of the division designing and to drastically reduce the number of modification man-hour due to associated work mistakes. CONSTITUTION:The block diagram editor consists of an input/output device 1, an operation processing device 2, a data storage device 3 and a block diagram editor mechanism 4. In the block diagram editor mechanism 4, the division and designing of a block diagram is performed by means of a division line editing part 5 defining a division line indicating the border of block diagram division areas and a division label editing part 6 defining a division label indicating the division regions for a symbol comprising the division areas or the block diagram. A division designing verification part 7 verifies the legality of the divided and designed block diagram and a division circuit information generation part 8 automatically generates division circuit information from the divided and designed block diagram.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電子回路装置のブロック
図エディタのブロック分割方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a block division method for a block diagram editor of an electronic circuit device.

【0002】[0002]

【従来の技術】従来のブロック図エディタは、分割専用
の図面構成要素またはシンボルがないため、属性を持た
ない構成要素を用いてブロック分割設計を行っており、
分割設計の検証および分割回路情報の生成は人手で行っ
ていた。
2. Description of the Related Art A conventional block diagram editor does not have a drawing constituent element or a symbol dedicated to division, so that a block division design is performed using a constituent element having no attribute.
The verification of the divided design and the generation of the divided circuit information were done manually.

【0003】[0003]

【発明が解決しようとする課題】この従来のブロック図
エディタは、分割定義専用の図面構成要素を持っていな
いため、ブロック図分割設計専用の図面表現ができない
という問題点があった。また、分割設計後の検証と分割
回路情報生成を人手で行っていたため、時間がかかるば
かりでなく、検証ミス,生成ミスにより品質が低下し、
その修正作業に伴い工数が増加するという問題点があっ
た。
This conventional block diagram editor does not have a drawing constituent element dedicated to the division definition, so that there is a problem that the drawing representation dedicated to the block diagram division design cannot be performed. In addition, since verification after division design and generation of division circuit information were done manually, not only it takes time, but also quality is deteriorated due to verification errors and generation errors.
There was a problem that the man-hour increased with the correction work.

【0004】[0004]

【課題を解決するための手段】本発明のブロック分割方
式は、電子回路装置のブロック図をブロック図エディタ
上でブロック分割して回路を切り出すブロック分割方式
において、ブロック図分割領域の境界を定義する分割線
編集手段と、分割領域またはブロック図を構成するシン
ボルに対し分割区分を定義する分割ラベル編集手段と、
分割定義の正当性を検証する分割設計検証手段と、前記
分割線編集手段,分割ラベル編集手段および分割設計検
証手段により分割設計されたブロック図から分割回路情
報を自動生成する分割回路情報生成手段とを備えてい
る。
According to the block division method of the present invention, boundaries of block diagram division areas are defined in the block division method of dividing a block diagram of an electronic circuit device on a block diagram editor to cut out a circuit. A dividing line editing means, a dividing label editing means for defining a dividing division for the symbols constituting the divided area or block diagram,
A division design verification means for verifying the correctness of the division definition, and a division circuit information generation means for automatically generating division circuit information from the block diagram divided and designed by the division line editing means, the division label editing means and the division design verification means. Is equipped with.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明のブロック分割方式の一実施例を示す
ブロック図エディタのブロック図、図2は図1における
ブロック図エディタ機構の動作の流れを示すフロー図、
図3は本実施例におけるウインドウ構成の一例を示す図
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a block diagram editor showing an embodiment of a block division method of the present invention, FIG. 2 is a flow diagram showing an operation flow of the block diagram editor mechanism in FIG.
FIG. 3 is a diagram showing an example of a window structure in this embodiment.

【0006】本実施例のブロック図エディタは入出力装
置1と、演算処理装置2と、データ記憶装置3と、ブロ
ック図エディタ機構4とからなる。ブロック図エディタ
機構4では、ブロック図分割領域の境界を示す分割線を
定義する分割線編集部5と、分割領域またはブロック図
を構成するシンボルに対し分割区分を示す分割ラベルを
定義する分割ラベル編集部6とによってブロック図の分
割設計を行う。そして分割設計検証部7により分割設計
したブロック図の正当性を検証し、分割回路情報生成部
8で分割設計が完了したブロック図から分割回路情報を
自動生成する。
The block diagram editor of this embodiment comprises an input / output unit 1, an arithmetic processing unit 2, a data storage unit 3 and a block diagram editor mechanism 4. In the block diagram editor mechanism 4, a dividing line editing unit 5 that defines a dividing line that indicates the boundary of the block diagram dividing region, and a dividing label edit that defines a dividing label that indicates a dividing division for the symbols that form the dividing region or the block diagram. The division design of the block diagram is performed by the unit 6. Then, the division design verification unit 7 verifies the correctness of the divided design block diagram, and the divided circuit information generation unit 8 automatically generates divided circuit information from the block diagram for which the division design is completed.

【0007】続いて本実施例の動作について図2を併用
して説明する。分割線編集部5,分割ラベル編集部6が
ブロック図エディタ上での分割線,分割ラベルを編集し
て分割設計を行った後(ステップ21)、その検証を行
う(ステップ22)。次に、検証結果を判断して設計ミ
スが検証された(ステップ23でNo)のときは、ステ
ップ21に戻り修正設計を行う。また設計ミスがなけれ
ば(ステップ23でYes)、分割回路情報を自動生成
する(ステップ25)。
Next, the operation of this embodiment will be described with reference to FIG. After the dividing line editing unit 5 and the dividing label editing unit 6 edit the dividing line and the dividing label on the block diagram editor to perform the dividing design (step 21), the verification is performed (step 22). Next, when the verification result is judged and the design error is verified (No in step 23), the process returns to step 21 to perform the modified design. If there is no design error (Yes in step 23), divided circuit information is automatically generated (step 25).

【0008】次に図3において、グラフィックウインド
ウ31はブロック図の表示と分割編集の指示を行う。メ
ニューウインドウ36はブロック図エディタが持つ各コ
マンドの起動指示を与える。分割定義に必要な構成要素
は分割線33と分割ラベル32であり、前者は分割領域
の境界を定義し、後者は分割領域の区分を定義する。ブ
ロック図の構成要素であるシンボル34にも分割ラベル
を定義することができる。コマンドである分割チェック
39を起動すると、分割設計の検証を行い、その結果を
メッセージウインドウ35とテキストウインドウ40に
表示する。
Next, in FIG. 3, a graphic window 31 displays a block diagram and gives instructions for division editing. The menu window 36 gives an instruction to activate each command of the block diagram editor. The components necessary for the division definition are the division line 33 and the division label 32, the former defining the boundaries of the division areas, and the latter defining the divisions of the division areas. A division label can also be defined for the symbol 34 that is a component of the block diagram. When the command split check 39 is activated, the split design is verified and the result is displayed in the message window 35 and the text window 40.

【0009】[0009]

【発明の効果】以上説明したように本発明は、電子回路
装置のブロック図を設計するブロック図エディタ機構に
分割線編集手段と分割ラベル編集手段と分割設計検証手
段と分割回路情報生成手段とを備えることにより、ブロ
ック図エディタ上で分割設計作業を行うことが可能とな
り且つ分割設計の検証と分割回路情報生成が自動処理で
きるので、作業工数の削減と分割設計の品質向上および
それに伴う作業ミスによる修正工数の大幅削減ができる
という効果を有する。
As described above, according to the present invention, the block diagram editor mechanism for designing the block diagram of the electronic circuit device includes the dividing line editing means, the dividing label editing means, the dividing design verifying means, and the divided circuit information generating means. With the provision, it becomes possible to perform the division design work on the block diagram editor, and the division design verification and the division circuit information generation can be automatically processed. This has the effect of significantly reducing the number of correction steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のブロック分割方式の一実施例を示すブ
ロック図エディタのブロック図である。
FIG. 1 is a block diagram of a block diagram editor showing an embodiment of a block division method of the present invention.

【図2】図1におけるブロック図エディタ機構の動作の
流れを示すフロー図である。
2 is a flow chart showing a flow of operation of the block diagram editor mechanism in FIG. 1. FIG.

【図3】本実施例におけるウインドウ構成の一例を示す
図である。
FIG. 3 is a diagram showing an example of a window structure in the present embodiment.

【符号の説明】[Explanation of symbols]

1 入出力装置 2 演算処理装置 3 データ記憶装置 4 ブロック図エディタ機構 5 分割線編集部 6 分割ラベル編集部 7 分割設計検証部 8 分割回路情報生成部 31 グラフィックウインドウ 32,38 分割ラベル 33 分割線 34 シンボル 35 メッセージウインドウ 36 メニューウインドウ 37 分割線配線 39 分割チェック 40 テキストウインドウ 1 Input / output device 2 Arithmetic processing device 3 Data storage device 4 Block diagram editor mechanism 5 Dividing line editing unit 6 Divided label editing unit 7 Divided design verification unit 8 Divided circuit information generation unit 31 Graphic window 32, 38 Divided label 33 Divided line 34 Symbol 35 Message window 36 Menu window 37 Dividing line wiring 39 Dividing check 40 Text window

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電子回路装置のブロック図をブロック図
エディタ上でブロック分割して回路を切り出すブロック
分割方式において、ブロック図分割領域の境界を定義す
る分割線編集手段と、分割領域またはブロック図を構成
するシンボルに対し分割区分を定義する分割ラベル編集
手段と、分割定義の正当性を検証する分割設計検証手段
と、前記分割線編集手段,分割ラベル編集手段および分
割設計検証手段により分割設計されたブロック図から分
割回路情報を自動生成する分割回路情報生成手段とを備
えることを特徴とするブロック分割方式。
1. In a block division method of dividing a block diagram of an electronic circuit device on a block diagram editor to cut out a circuit, a dividing line editing means for defining a boundary of the block diagram dividing region and a dividing region or a block diagram are provided. A division label editing means for defining division divisions for the constituent symbols, a division design verification means for verifying the correctness of the division definition, and a division design by the division line editing means, division label editing means and division design verification means. A block division method, comprising: divided circuit information generating means for automatically generating divided circuit information from a block diagram.
JP4020840A 1992-02-06 1992-02-06 Block division system Withdrawn JPH05216947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4020840A JPH05216947A (en) 1992-02-06 1992-02-06 Block division system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4020840A JPH05216947A (en) 1992-02-06 1992-02-06 Block division system

Publications (1)

Publication Number Publication Date
JPH05216947A true JPH05216947A (en) 1993-08-27

Family

ID=12038275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4020840A Withdrawn JPH05216947A (en) 1992-02-06 1992-02-06 Block division system

Country Status (1)

Country Link
JP (1) JPH05216947A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10132667B2 (en) 2014-03-17 2018-11-20 Auxitrol S.A. Method of manufacturing an element sensitive to a physical parameter of a flow of fluid and corresponding sensitive element

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10132667B2 (en) 2014-03-17 2018-11-20 Auxitrol S.A. Method of manufacturing an element sensitive to a physical parameter of a flow of fluid and corresponding sensitive element

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Effective date: 19990518