JPH05216761A - Microprocessor - Google Patents

Abstract

PURPOSE:To reduce the hardware scale of the microprocessor by directly decoding the output of a cache memory regardless of whether the function of the cache memory is freezed or not. CONSTITUTION:The microprocessor in a pipeline processing system directly decode the output of the cache memory 1, operational code register 3, addressing field register 4, displacement register 5 and instruction decoder 7. The aligner 2 divides an instruction codes and stores them in the respective registers 3-5. According to the contents of the operational code register 3 and the addressing field register 4, the instruction decoder 7 outputs the address of a microcode ROM 8. Namely, the output of the cache memory 1 is directly decoded by the aligner 2 and the instruction decoder 7 regardless of whether the function of the cache memory 1 is freezed or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor incorporating a cache memory.

[0002]

2. Description of the Related Art With the increasing integration of LSIs, it has become common to employ a pipeline processing mechanism as a speed-up technology for microprocessors or to integrate a cache memory on the same chip.

Microprocessors of this type are usually
(1) Prefetching instruction code from cache memory,
(2) instruction decoding, (3) effective address calculation,
It has a pipeline structure of (4) instruction execution, and (5) write back of execution result to a register. Conventionally,
An instruction code queue is placed between (1) and (2) to hold the instruction code prefetched from the main memory.

In the microprocessor having this pipeline structure, the internal cache memory may or may not be used, and each of them prefetches an instruction by a separate control circuit, and the output of the cache memory and the main storage unit are used. The data read from the bus and the data from the bus were multiplexed and stored in the instruction code queue.

[0005]

In the above-described conventional microprocessor, the internal cache memory may or may not be used, and since these control circuits are separate, the scale of hardware is small. There was a problem that it would grow.

[0006]

A microprocessor of the present invention is a pipeline processing type microprocessor having a built-in cache memory, the decoding means for directly decoding the output of the cache memory, and the cache memory. And a control means for writing the fetched instruction code to a specific area of the cache memory when the function of the memory is frozen and operating, regardless of whether the function of the cache memory is frozen or unfrozen. It is configured to directly decode the output of the memory.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, in which the present invention is applied to a microprocessor incorporating a direct map type cache memory.

Data RAM1 of cache memory 1
Each entry consists of 128 bits, and the output of the data RAM 10 is directly input to the aligner 2.

The aligner 2 divides the instruction code into an operation code, an addressing field and a displacement and stores them in an operation code register 3, an addressing field register 4 and a displacement register 5, respectively.

The instruction decoder 7 outputs the address of the microcode ROM 8 according to the contents of the operation code register 3 and the addressing field register 4.

The effective address calculator 6 uses the values read from the displacement register 5 and the register file 9 to generate an effective address for external memory across.

When the contents of the operation code register 3, addressing field register 4 and displacement register 5 are no longer needed after the instruction decoding and the generation of the effective address are completed, the instruction prefetcher 12 updates the prefetch address and refers to the cache memory 1. When the cache memory 1 has a mishit, the prefetch address is sent to the bus interface unit 13 to replace the cache memory 1.

When operating without referring to the cache memory 1, the instruction prefetcher 12 uses the cache memory 1.
Whenever the memory 1 is referred to, a replacement is performed assuming that a miss hit occurs. The replaced instruction code is written in the hatched area in FIG. 1, and this output is used as the input of the aligner 2. The data in the hatched area is held until decoding is completed and used as a buffer for prefetched instruction codes.

FIG. 2 is a block diagram showing a second embodiment of the present invention, in which the present invention is applied to a microprocessor incorporating a 2-way set associative cache memory.

Data R in the cache memories 1a and 1b
Each of AM1Da and 1Db consists of 64 bits per entry, and the output of either set of data RAMs is selected by multiplexers 14a and 14b to be used as the input of the aligner 2a.

Since the basic operation is the same as that of the first embodiment, its explanation is omitted.

[0018]

As described above, according to the present invention, the hardware of the instruction code queue can be reduced by directly decoding the output of the cache memory by the aligner and the instruction decoder, and the function of the cache memory is frozen to operate. At times, there is an effect that the instruction prefetch control circuit can be simplified by performing (mishit) processing similar to the case of using the cache memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 1, 1a, 1b Cache memory 1D, 1Da, 1Db Data RAM 1T, 1Ta, 1Tb Tag RAM 2, 2a Aligner 3 Opcode register 4 Addressing field register 5 Displacement register 6 Execution address calculator 7 Instruction decoder 8 Microcode ROM 9 Register file 10 Barrel shifter 11 ALU 12 Instruction prefetcher 13 Bus interface unit

Claims (1)

[Claims] 1. A pipeline processing type microprocessor having a built-in cache memory, wherein the decoding means directly decodes the output of the cache memory, and when the function of the cache memory is frozen to operate. And a control means for writing the fetched instruction code into a specific area of the cache memory, and directly decoding the output of the cache memory regardless of whether the function of the cache memory is frozen or unfrozen. Microprocessor characterized by.