JPH05215776A - Inspector and probe card thereof for semiconductor integrated circuit device and inspection method thereof - Google Patents
Inspector and probe card thereof for semiconductor integrated circuit device and inspection method thereofInfo
- Publication number
- JPH05215776A JPH05215776A JP4271266A JP27126692A JPH05215776A JP H05215776 A JPH05215776 A JP H05215776A JP 4271266 A JP4271266 A JP 4271266A JP 27126692 A JP27126692 A JP 27126692A JP H05215776 A JPH05215776 A JP H05215776A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- semiconductor integrated
- dielectric constant
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置の
プローブ検査のための検査装置、およびそのプローブカ
ード、ならびに半導体集積回路装置の検査方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inspection apparatus for probe inspection of a semiconductor integrated circuit device, a probe card therefor, and a method for inspecting a semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】半導体集積回路装置は、シリコン等の半
導体ウェーハに製造され、ウェーハ段階でその良品、不
良品をプローブ検査（不良チップを次の組立工程から除
外するため、ウェーハ上の全てのチップの良否をウェー
ハ状態でテストする検査）にて判別してから良品のみを
封止して完成品にしている。2. Description of the Related Art A semiconductor integrated circuit device is manufactured on a semiconductor wafer of silicon or the like, and a good product or a defective product is probe-tested at the wafer stage (in order to exclude defective chips from the next assembly process, all chips on the wafer are The quality is determined by the inspection for testing in the wafer state), and only the non-defective product is sealed to complete the product.
【０００３】図８は、従来の半導体集積回路装置の検査
装置の部分断面図であってウェーハの、半導体集積回路
が形成されたチップ１のパッド電極にプローブ針２を立
てプローブ検査を行なっていた。なお、半導体集積回路
が組み込まれたウェーハ１はウェーハチャック（図示せ
ず）に固定されており、連続して隣のチップ１にプロー
ブ針２を立てることができるものである。FIG. 8 is a partial cross-sectional view of a conventional semiconductor integrated circuit device inspecting apparatus, in which a probe needle 2 is set on a pad electrode of a chip 1 on which a semiconductor integrated circuit is formed on a wafer to perform a probe inspection. .. The wafer 1 incorporating the semiconductor integrated circuit is fixed to a wafer chuck (not shown), and the probe needle 2 can be continuously set up on the adjacent chip 1.
【０００４】[0004]
【発明が解決しようとする課題】半導体集積回路装置
は、生産コストの面から樹脂封止されることが多い。し
かし、従来の半導体集積回路装置の検査装置では、半導
体集積回路装置のチップ１の上は空気の雰囲気であるた
め、検査では異常がなくてもチップ１を樹脂封止すると
電気特性が変化することがあり、そのために完成品が電
気特性変化により歩留まりが低下するという問題があっ
た。これは、封止樹脂の誘電率が空気より大きいため
で、半導体集積回路装置の回路間に容量結合が生じるこ
とによって、回路動作が変化するからである。Semiconductor integrated circuit devices are often resin-sealed from the viewpoint of production cost. However, in the conventional inspection apparatus for a semiconductor integrated circuit device, since the atmosphere above the chip 1 of the semiconductor integrated circuit device is an air atmosphere, the electrical characteristics may change when the chip 1 is resin-sealed even if there is no abnormality in the inspection. Therefore, there is a problem that the yield of the finished product is reduced due to the change in electrical characteristics. This is because the permittivity of the sealing resin is larger than that of air, and the capacitive coupling between the circuits of the semiconductor integrated circuit device changes the circuit operation.
【０００５】本発明は、上記問題を解決するもので、電
気特性の変化を最小限にして完成品の歩留まりを向上さ
せた半導体集積回路装置の検査装置およびそのプローブ
カードならびに半導体集積回路装置の検査方法を提供す
ることを目的とするものである。The present invention solves the above problems, and a semiconductor integrated circuit device inspection apparatus, a probe card thereof, and a semiconductor integrated circuit device inspection in which changes in electrical characteristics are minimized to improve the yield of finished products. It is intended to provide a method.
【０００６】[0006]
【課題を解決するための手段】上記問題を解決するた
め、本発明の半導体集積回路装置の検査装置は、ウェー
ハの、半導体集積回路が形成されたチップの上面に当接
する高誘電率の基板を備えている。In order to solve the above problems, an inspection apparatus for a semiconductor integrated circuit device according to the present invention includes a substrate having a high dielectric constant, which is in contact with an upper surface of a chip of a wafer on which a semiconductor integrated circuit is formed. I have it.
【０００７】また、本発明の半導体集積回路装置の検査
方法は、ウェーハの、半導体集積回路が形成されたチッ
プの上面に、高誘電率の基板を当接させて、プローブ検
査をする。Also, in the method for inspecting a semiconductor integrated circuit device of the present invention, a probe having a high dielectric constant is brought into contact with the upper surface of a chip on which a semiconductor integrated circuit is formed on a wafer.
【０００８】さらに、本発明のプローブカードは、プロ
ーブ検査の際、ウェーハの、半導体集積回路が形成され
たチップの上面に当接する高誘電率の基板が取り付けら
れている。Furthermore, in the probe card of the present invention, a substrate having a high dielectric constant is attached which is brought into contact with the upper surface of the chip of the wafer on which the semiconductor integrated circuit is formed during the probe inspection.
【０００９】[0009]
【作用】本発明によれば、ウェーハの、半導体集積回路
が形成されたチップの上面に高誘電率の基板を当接する
ことで、チップを樹脂封止したときと同じ状態にするこ
とができ、半導体集積回路装置間の封止樹脂による容量
結合を生じさせることができる。よって、樹脂封止後の
完成品の電気特性変化をあらかじめ知ることができる。According to the present invention, by bringing a substrate having a high dielectric constant into contact with the upper surface of the chip of the wafer on which the semiconductor integrated circuit is formed, the same state as when the chip is resin-sealed can be obtained, Capacitive coupling between the semiconductor integrated circuit devices can be caused by the sealing resin. Therefore, it is possible to know in advance the changes in the electrical characteristics of the finished product after resin sealing.
【００１０】[0010]
【実施例】本発明の半導体集積回路装置の検査装置、お
よびそのプローブカード、ならびに半導体集積回路装置
の検査方法の第１の実施例について、図１〜図６を用い
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit device inspection apparatus, a probe card therefor, and a semiconductor integrated circuit device inspection method according to a first embodiment of the present invention will be described with reference to FIGS.
【００１１】図１は、本発明の半導体集積回路装置の検
査装置の概念図である。図１において、半導体集積回路
が組み込まれたウェハーをウェーハプロバー１１のウェ
ハーチャック１２上に固定し、そのチップ１３のパッド
電極にプローブ針１４を立てる。高誘電率の基板１５は
チップ１３の集積回路部の上面の大部分と当接してい
る。高誘電率の基板１５は、板ばね１７と支持部材１８
とで、プローブカード１６に固定されている。プローブ
カード１６は、ＬＳＩテスター２０につながるテストヘ
ッド１９に接続されており、ＬＳＩテスター２０で半導
体集積回路が形成されたチップ１３の電気特性を測定検
査する。FIG. 1 is a conceptual diagram of an inspection apparatus for a semiconductor integrated circuit device according to the present invention. In FIG. 1, a wafer in which a semiconductor integrated circuit is incorporated is fixed on a wafer chuck 12 of a wafer prober 11, and a probe needle 14 is set on a pad electrode of a chip 13 thereof. The high dielectric constant substrate 15 is in contact with most of the upper surface of the integrated circuit portion of the chip 13. The high dielectric constant substrate 15 includes a leaf spring 17 and a support member 18.
And are fixed to the probe card 16. The probe card 16 is connected to the test head 19 connected to the LSI tester 20, and the LSI tester 20 measures and inspects the electrical characteristics of the chip 13 on which the semiconductor integrated circuit is formed.
【００１２】図２は、この検査装置で用いた高誘電率の
基板１５の外形を示す。高誘電率の基板１５は、図に示
すように直方体構造で、チップ１３の集積回路部上面に
図２の斜線部である高誘電率の基板１５の底面が接して
いる。高誘電率の基板１５は、透明であれば、このよう
にチップ１３上からプローブ針１４をパッド電極に位置
合わせするのを、従来のように目視で確認しながら所定
位置にセットすることができる。FIG. 2 shows the outer shape of the high dielectric constant substrate 15 used in this inspection apparatus. The high-dielectric constant substrate 15 has a rectangular parallelepiped structure as shown in the figure, and the bottom surface of the high-dielectric constant substrate 15, which is the hatched portion in FIG. If the substrate 15 having a high dielectric constant is transparent, it can be set at a predetermined position while visually confirming that the probe needle 14 is aligned with the pad electrode from above the chip 13 in the conventional manner. ..
【００１３】図３は、本発明の半導体集積回路装置の検
査装置のチップ１３にプローブ針１４が立てられたとこ
ろの拡大図である。ウェーハチャック（図示せず）上に
固定されたウェーハの、半導体集積回路が形成されたチ
ップ１３のパッド電極にプローブ針１４を立てるととも
に、高誘電率の基板１５をチップ１３の上面に当接でき
る構造になっている。FIG. 3 is an enlarged view showing a state where the probe needle 14 is erected on the chip 13 of the inspection device for the semiconductor integrated circuit device of the present invention. A probe needle 14 can be set on a pad electrode of a chip 13 on which a semiconductor integrated circuit is formed on a wafer fixed on a wafer chuck (not shown), and a substrate 15 having a high dielectric constant can be brought into contact with the upper surface of the chip 13. It is structured.
【００１４】図４は、高誘電率の基板１５をチップ１３
の上面に当接したところの断面図である。チップ１３上
には種々の絶縁膜が形成されており、その絶縁膜の所定
位置のコンタクトを通して配線２１がチップ１３に接続
されている。さらに、配線２１上およびチップ１３全面
には、チップ１３を保護するパッシベーション膜２２が
形成されている。高誘電率の基板１５は、そのパッシベ
ーション膜２２上に接して形成されている。これを測定
する場合、これらの構成によっておのずから電気的な容
量結合が発生する。容量結合には大きく二つのものが考
えられる。その一つは、ある配線２１と他の配線２１と
の間に、パッシベーション膜２２と高誘電率の基板１５
とを介して容量が形成されたものである。他の一つは、
高誘電率の基板１５とチップ１３との間に容量が形成さ
れたものである。ここでは、この容量はチップ１３とそ
の上のパッシベーション膜２２、さらに空気の領域を介
して高誘電率の基板１５との間に容量結合が発生してい
る。従来の測定では、高誘電率の基板１５が存在してい
なかったので、容量結合は空気を介してのみ発生してい
た。しかし、測定後チップ１３に樹脂封止を行うと、容
量は樹脂を介して発生するため、チップ１３の状態で測
定した場合とは異なった結果状態となる。これに対し
て、本実施例では高誘電率の基板１５をチップ１３の表
面に接触させているので、樹脂封止したチップ１３の状
態のものとほぼ同じ条件下で測定することができる。In FIG. 4, a substrate 15 having a high dielectric constant is formed on a chip 13.
FIG. 3 is a cross-sectional view of a portion in contact with the upper surface of FIG. Various insulating films are formed on the chip 13, and the wiring 21 is connected to the chip 13 through contacts at predetermined positions on the insulating film. Further, a passivation film 22 for protecting the chip 13 is formed on the wiring 21 and on the entire surface of the chip 13. The high dielectric constant substrate 15 is formed in contact with the passivation film 22. When measuring this, these configurations naturally cause electrical capacitive coupling. There are two major types of capacitive coupling. One of them is that a passivation film 22 and a high dielectric constant substrate 15 are provided between a certain wiring 21 and another wiring 21.
A capacitor is formed through and. The other one is
A capacitor is formed between the substrate 15 having a high dielectric constant and the chip 13. Here, the capacitance is capacitively coupled between the chip 13, the passivation film 22 on the chip 13, and the substrate 15 having a high dielectric constant through the air region. In the conventional measurement, since the high dielectric constant substrate 15 was not present, the capacitive coupling occurred only through the air. However, if the chip 13 is sealed with resin after the measurement, the capacitance is generated through the resin, so that the result state is different from that in the case of measuring the state of the chip 13. On the other hand, in this embodiment, since the substrate 15 having a high dielectric constant is brought into contact with the surface of the chip 13, the measurement can be performed under substantially the same conditions as those of the resin-sealed chip 13.
【００１５】さらに、このことを図５の模式図を用いて
詳細に説明する。半導体集積回路が形成されたチップ１
３上に配線２１が形成されており、さらにそれらの上に
高誘電率の基板１５が接している。このとき、配線２１
間にチップ１３を介して生じる容量をＣ1、チップ１３
と高誘電率の基板１５との間に挟まれた配線２１間に生
じる容量Ｃ2、配線２１間に高誘電率の基板１５を介し
て生じる容量をＣ3とすると、半導体集積回路の微細化
に伴って、配線２１間の距離が短くなる。もしこの配線
２１が信号線であれば、信号線に配線２１間の容量Ｃが
付加される。すなわち、 Ｃ＝Ｃ1＋Ｃ2＋Ｃ3 となる。ここで、チップ１３を樹脂封止する前と後で
は、容量Ｃ3だけその測定値が異なる。Ｃ3が変動するこ
とで、信号の遅延関係が逆転したりする。この場合、測
定時に不良品だったものが、組立後に良品となったり、
その逆になったりすることもある。Further, this will be described in detail with reference to the schematic view of FIG. Chip 1 on which a semiconductor integrated circuit is formed
A wiring 21 is formed on the substrate 3, and a substrate 15 having a high dielectric constant is in contact therewith. At this time, the wiring 21
Capacitance generated through the chip 13 between C 1 and the chip 13
If the capacitance C 2 generated between the wiring 21 sandwiched between the high dielectric constant substrate 15 and the high dielectric constant is C 3 and the capacitance generated between the wiring 21 via the high dielectric constant substrate 15 is C 3 , miniaturization of the semiconductor integrated circuit is assumed. Accordingly, the distance between the wirings 21 becomes shorter. If the wiring 21 is a signal line, the capacitance C between the wirings 21 is added to the signal line. That is, C = C 1 + C 2 + C 3 . Here, before and after the chip 13 is resin-sealed, the measured values differ by the capacitance C 3 . When C 3 fluctuates, the delay relationship of signals is reversed. In this case, what was defective at the time of measurement becomes good after assembly,
The opposite may occur.
【００１６】ここで、この高誘電率の基板１５の当接
は、自重によるものでもよいし、ばね（図示せず）によ
り適度な圧力になるように調整されたものでもよい。高
誘電率の基板１５の誘電率は、封止樹脂の材料のシリカ
とエポキシ樹脂の混合体の誘電率に合わせると完成品の
電気特性に近づけることが可能となり、プローブ検査の
精度が向上する。すなわち、通常の封止用の樹脂は誘電
率が４.２であり、エポキシ樹脂とシリカとを重量比で
１６：８４の割合で混合した樹脂組成物を用いて高誘電
率の基板１５を形成することにより、樹脂封止後のチッ
プを測定するのとほぼ同じ状態での測定が実現できる。
ここで、エポキシ樹脂の誘電率は４.０、シリカの誘電
率は４.５である。また、ここで完成品の電気特性と
は、半導体装置に当初要求されるスペックをいい、たと
えば、メモリー装置であるならば、アクセスタイムとか
誤動作しないためのタイミングマージンのような特性を
指す。Here, the contact of the high dielectric constant substrate 15 may be due to its own weight or may be adjusted by a spring (not shown) so as to have an appropriate pressure. If the permittivity of the substrate 15 having a high permittivity is matched with the permittivity of a mixture of silica and epoxy resin, which are materials for the sealing resin, it becomes possible to approximate the electrical characteristics of the finished product, and the accuracy of probe inspection is improved. That is, a normal sealing resin has a dielectric constant of 4.2, and the high dielectric constant substrate 15 is formed using a resin composition in which an epoxy resin and silica are mixed at a weight ratio of 16:84. By doing so, the measurement can be realized in almost the same state as that of the chip after resin sealing.
Here, the dielectric constant of epoxy resin is 4.0 and the dielectric constant of silica is 4.5. The electrical characteristics of the finished product refer to the specifications initially required for the semiconductor device, for example, in the case of a memory device, such as the access time and the timing margin for preventing malfunction.
【００１７】ただし、本発明における高誘電率の基板１
５は、封止樹脂と同じ誘電率のものに限定されるもので
はなく、他の高誘電率の材料であってもよい。However, the high dielectric constant substrate 1 of the present invention
The material 5 is not limited to the one having the same dielectric constant as that of the sealing resin, and may be another material having a high dielectric constant.
【００１８】本発明の半導体集積回路装置の検査方法
は、ウェーハのアライメント後、プローブ針１４をチッ
プ１３に立て、高誘電率の基板１５をチップ１５の上面
に当接した後、電気特性を測定検査する。ウェーハの、
半導体集積回路が形成されたチップ１３の上面に、高誘
電率の基板１５を当接することで、チップ１３を樹脂封
止したときと同じ状態にすることができる。In the method for inspecting a semiconductor integrated circuit device according to the present invention, after the wafer is aligned, the probe needle 14 is erected on the chip 13 and the substrate 15 having a high dielectric constant is brought into contact with the upper surface of the chip 15, and then the electrical characteristics are measured. inspect. Of wafer,
By bringing the high-dielectric constant substrate 15 into contact with the upper surface of the chip 13 on which the semiconductor integrated circuit is formed, the same state as when the chip 13 is resin-sealed can be obtained.
【００１９】なお、高誘電率の基板１５は、本発明の半
導体集積回路装置の検査装置のウェーハアライメントを
行なうウェーハプローバ（図示せず）に固定して、チッ
プ１３に当接するようにしてもよいし、ウェーハプロー
バとは別の独立した装置に取り付けてもよい。すなわ
ち、高誘電率の基板１５は、チップ１３の上部にあっ
て、測定時にチップ１３の上面に接するようにしておけ
ばよい。このため連続してチップ１３を測定する場合に
は、ウェーハプローバに取り付けて固定しておく方が、
検査装置のスループットを向上させることができる。The substrate 15 having a high dielectric constant may be fixed to a wafer prober (not shown) for performing wafer alignment of the inspection device for the semiconductor integrated circuit device of the present invention so as to abut the chip 13. However, it may be attached to an independent device other than the wafer prober. That is, the high-dielectric-constant substrate 15 may be on the upper part of the chip 13 and contact the upper surface of the chip 13 at the time of measurement. For this reason, when measuring the chip 13 continuously, it is better to mount and fix it on the wafer prober.
The throughput of the inspection device can be improved.
【００２０】図６は、本発明のプローブカードの使用状
態図であり、図６に示すように、プローブ針１４がプロ
ーブカード１６に設けられ、このプローブカード１６に
板ばね１７が取り付けられ、さらに、この板ばね１７に
支持部材１８を介して高誘電率の基板１５が固定されて
いる。プローブカード１６と高誘電率の基板１５は、チ
ップ１３に対する当接が板ばね１７により適度な圧力に
なるよう固定する。この圧力は、チップ１３に接触させ
た場合に、その圧力によってチップ１３に形成された半
導体装置の電気的特性が変動しなければよい。特にチッ
プ１３に形成された半導体装置の大きさに依存してい
る。FIG. 6 is a diagram showing the use state of the probe card of the present invention. As shown in FIG. 6, the probe needle 14 is provided on the probe card 16, and the leaf spring 17 is attached to the probe card 16. A substrate 15 having a high dielectric constant is fixed to the leaf spring 17 via a supporting member 18. The probe card 16 and the substrate 15 having a high dielectric constant are fixed by a leaf spring 17 so that the contact with the chip 13 is moderate. It is sufficient that this pressure does not change the electrical characteristics of the semiconductor device formed on the chip 13 when the pressure is brought into contact with the chip 13. In particular, it depends on the size of the semiconductor device formed on the chip 13.
【００２１】プローブ針１４の先端と高誘電率の基板１
５との下の面はチップ１３の表面の高さに合わされてい
る。The tip of the probe needle 14 and the substrate 1 having a high dielectric constant
The lower surface of 5 and the lower surface are aligned with the height of the surface of the chip 13.
【００２２】なお、プローブカード１６の場合も、高誘
電率の基板１５の誘電率は封止樹脂の材料のシリカとエ
ポキシ樹脂の混合体の誘電率に合わせると、プローブ検
査で完成品の電気特性に近づけることが可能となること
は言うまでもない。Also in the case of the probe card 16, if the permittivity of the substrate 15 having a high permittivity is matched with the permittivity of the mixture of silica and epoxy resin, which is the material of the sealing resin, the electrical characteristics of the finished product by probe inspection. It goes without saying that it will be possible to approach.
【００２３】図７に本発明の半導体集積回路装置の検査
方法にかかる第２の実施例の断面構成図である。従来の
半導体集積回路装置のチップは、プローブ針を立てるパ
ッド電極がチップの周辺部分に設けられている。昨今、
パッド電極をチップの中央部に設けたいわゆるＬＯＣ
（Lead On Chip）構造の半導体集積回路装置が用いられ
てきている。このような半導体集積回路装置に本発明の
検査方法を用いる場合の実施例について説明する。FIG. 7 is a sectional view of the second embodiment of the method for inspecting a semiconductor integrated circuit device according to the present invention. In a chip of a conventional semiconductor integrated circuit device, a pad electrode for raising a probe needle is provided in a peripheral portion of the chip. These days
A so-called LOC in which a pad electrode is provided in the center of the chip
Semiconductor integrated circuit devices having a (Lead On Chip) structure have been used. An example of using the inspection method of the present invention for such a semiconductor integrated circuit device will be described.
【００２４】チップ１３のほぼ中央部付近にパッド電極
が形成されている。パッド電極には、プローブ針１４が
立てられている。ただし、プローブ針１４はチップ１３
の中央部に立てなければならないので、容量を樹脂封止
後の状態にするための高誘電率の基板１５と支持部材１
８は、そのパッド電極が接触する中央部付近に、プロー
ブ針１４よりやや大きめのくり抜き穴が設けられてい
る。さらに、そのプローブ針１４は板ばね１７によって
固定してある。なお、チップの周辺部分にプローブ針１
４を立てずに、プローブ針１４がチップ１３の中央部の
みに立てる場合には、板ばね１７のかわりに、プローブ
カード１６にそのプローブ針１４を固定してもよい。A pad electrode is formed near the center of the chip 13. A probe needle 14 is erected on the pad electrode. However, the probe needle 14 is the tip 13
Since it has to stand in the center of the substrate, the high dielectric constant substrate 15 and the supporting member 1 for keeping the capacitance in the state after resin sealing.
8 is provided with a hole slightly larger than the probe needle 14 near the central portion where the pad electrode contacts. Further, the probe needle 14 is fixed by a leaf spring 17. In addition, the probe needle 1 is
When the probe needle 14 is raised only in the central portion of the chip 13 without raising 4, the probe needle 14 may be fixed to the probe card 16 instead of the leaf spring 17.
【００２５】このような構成によりＬＯＣ構造をもつチ
ップであっても、上述の第１の実施例と同じ効果が得ら
れることは言うまでもない。さらに、連続してチップを
測定する際、従来は長期間の使用中にプローブ針の相対
的な位置ずれが発生して保守調整をしていたが、このよ
うな構成にすることで、長期間、多数個の検査を行って
も相対的な位置ずれを生じることがない。It is needless to say that even the chip having the LOC structure with such a structure can obtain the same effect as that of the first embodiment. In addition, when measuring chips continuously, in the past, relative displacement of the probe needle occurred during long-term use and maintenance adjustments were made. Even if a large number of inspections are performed, no relative displacement occurs.
【００２６】[0026]
【発明の効果】以上のように、本発明の半導体集積回路
装置の検査装置、およびそのプローブカード、ならびに
半導体集積回路装置の検査方法によれば、ウェーハ段階
のプローブ検査で封止樹脂による半導体集積回路装置間
の容量結合を実現することが可能となり、チップを樹脂
封止すると電気特性が変化するという問題を解決するこ
とができ、そのために完成品の電気特性変化による歩留
まり低下を防止でき、高性能な半導体集積回路装置を製
造することが可能となる。また、長期間にわたりプロー
ブカードの保守調整が不要にできる。As described above, according to the inspection device for a semiconductor integrated circuit device, the probe card therefor, and the inspection method for a semiconductor integrated circuit device according to the present invention, the semiconductor integration by the sealing resin is performed in the probe inspection at the wafer stage. It is possible to realize capacitive coupling between circuit devices, and it is possible to solve the problem that the electrical characteristics change when the chip is resin-sealed. Therefore, it is possible to prevent the yield reduction due to the change in the electrical characteristics of the finished product. It is possible to manufacture a high-performance semiconductor integrated circuit device. In addition, maintenance and adjustment of the probe card can be eliminated over a long period of time.
【図１】本発明の半導体集積回路装置の検査装置の構成
図FIG. 1 is a configuration diagram of an inspection device for a semiconductor integrated circuit device of the present invention.
【図２】本発明の半導体集積回路装置の検査装置に用い
る高誘電率の基板の斜視図FIG. 2 is a perspective view of a substrate having a high dielectric constant used in an inspection apparatus for a semiconductor integrated circuit device according to the present invention.
【図３】本発明の半導体集積回路装置の検査装置の第１
の実施例の要部断面図FIG. 3 is a first inspection device for a semiconductor integrated circuit device according to the present invention.
Sectional view of the main part of the embodiment
【図４】チップと高誘電率の基板との間に生じる容量を
説明する断面図FIG. 4 is a cross-sectional view illustrating a capacitance generated between a chip and a substrate having a high dielectric constant.
【図５】チップと高誘電率の基板との間に生じる容量を
説明する断面図FIG. 5 is a cross-sectional view illustrating a capacitance generated between a chip and a substrate having a high dielectric constant.
【図６】本発明のプローブカードの使用状態図FIG. 6 is a diagram showing a usage state of the probe card of the present invention.
【図７】本発明の半導体集積回路装置の検査装置の第２
の実施例の要部断面図FIG. 7 is a second inspection device for a semiconductor integrated circuit device according to the present invention.
Sectional view of the main part of the embodiment
【図８】従来例を説明するための部分断面図FIG. 8 is a partial cross-sectional view for explaining a conventional example.
１３ ウェーハのチップ １４ プローブ針 １５ 高誘電率の基板 １６ プローブカード １７ 板ばね １８ 支持部材 13 Wafer Chip 14 Probe Needle 15 High Dielectric Constant Substrate 16 Probe Card 17 Leaf Spring 18 Supporting Member
Claims (8)
積回路が形成されたチップの上面に当接する高誘電率の
基板を備えた半導体集積回路装置の検査装置。1. An inspection apparatus for a semiconductor integrated circuit device, comprising a substrate having a high dielectric constant that abuts an upper surface of a chip on which a semiconductor integrated circuit is formed on a wafer during probe inspection.
ある請求項１記載の半導体集積回路装置の検査装置。2. The inspection device for a semiconductor integrated circuit device according to claim 1, wherein the substrate having a high dielectric constant has the same dielectric constant as that of the sealing resin.
付けられた請求項１または請求項２記載の半導体集積回
路装置の検査装置。3. The inspection device for a semiconductor integrated circuit device according to claim 1, wherein the substrate having a high dielectric constant is attached to the wafer prober.
チップの上面に高誘電率の基板を当接してプローブ検査
する半導体集積回路装置の検査方法。4. A method for inspecting a semiconductor integrated circuit device, wherein a high dielectric constant substrate is brought into contact with an upper surface of a chip on which a semiconductor integrated circuit is formed on a wafer to perform a probe inspection.
基板を用いる請求項４記載の半導体集積回路装置の検査
方法。5. The method for inspecting a semiconductor integrated circuit device according to claim 4, wherein the substrate having a high dielectric constant is the same as the sealing resin.
積回路が形成されたチップの上面に当接する高誘電率の
基板が取り付けられたプローブカード。6. A probe card having a substrate of high dielectric constant attached to the upper surface of a chip of a wafer on which a semiconductor integrated circuit is formed during probe inspection.
ある請求項６記載のプローブカード。7. The probe card according to claim 6, wherein the substrate having a high dielectric constant has the same dielectric constant as that of the sealing resin.
積回路が形成されたチップの上面に当接する高誘電率の
基板に、プローブ針を貫通させて固定したプローブカー
ド。8. A probe card in which a probe needle is pierced and fixed to a substrate having a high dielectric constant, which is in contact with an upper surface of a chip on which a semiconductor integrated circuit is formed, during a probe test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4271266A JPH05215776A (en) | 1991-10-09 | 1992-10-09 | Inspector and probe card thereof for semiconductor integrated circuit device and inspection method thereof |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26151091 | 1991-10-09 | ||
| JP3-261510 | 1991-10-09 | ||
| JP4271266A JPH05215776A (en) | 1991-10-09 | 1992-10-09 | Inspector and probe card thereof for semiconductor integrated circuit device and inspection method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05215776A true JPH05215776A (en) | 1993-08-24 |
Family
ID=26545110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4271266A Pending JPH05215776A (en) | 1991-10-09 | 1992-10-09 | Inspector and probe card thereof for semiconductor integrated circuit device and inspection method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05215776A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9304160B1 (en) | 2012-05-08 | 2016-04-05 | Kla-Tencor Corporation | Defect inspection apparatus, system, and method |
-
1992
- 1992-10-09 JP JP4271266A patent/JPH05215776A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9304160B1 (en) | 2012-05-08 | 2016-04-05 | Kla-Tencor Corporation | Defect inspection apparatus, system, and method |
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