JPH05211291A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the substrate bias voltage by providing a voltage generating circuit to supply the substrate bias current to a semiconductor substrate and a semiconductor region of a conductive type which is opposite to the semiconductor substrate, respectively. CONSTITUTION:A ring oscillator OSC is formed by a CMOS inverter comprises an N channel MOSFET Q3 and P channel MOSFETs Q4 to Q6. Therefore, the P channel MOSFETs Q4 to Q6 are responsible for the formation of the rising output signal of a high level for each of the inserters. These P channel MOSFETs Q4 to Q6 are to be formed in an N type well region, and are biased by a power source voltage Vcc. As a result, even if the substrate bias voltage -VBB is varied, its conductance gm becomes constant. In this way, the high-level rising of the output signal of each inverter becomes constant irrespective of the variation of the substrate bias voltage -VBB.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device composed of a MOSFET (insulation gate type field effect transistor).

[0002]

2. Description of the Related Art A substrate bias voltage generating circuit for supplying a bias voltage VBB to a substrate of a MOS-IC chip is
Generally, it is composed of an oscillation circuit, an amplifier for amplifying the output signal of this oscillation circuit, and a pump circuit for forming a DC bias voltage from the output signal of this amplifier,
These are mounted on an IC chip.

The substrate bias voltage generating circuit described above has a conventional N
It is provided to apply the bias voltage VBB to the P-type substrate of the channel type MOS memory IC, and by applying this bias voltage VBB, the threshold voltage Vth control of the N-channel MOSFET and the high speed operation by decreasing the junction capacitance are realized. Etc.

Conventionally, the above-mentioned oscillation circuit has an odd number of stages of inverters.
A ring oscillator is used in which data are cascade-connected in a ring shape. These inverters are composed of an N-channel type load MOSFET and an N-channel type drive MOSF.
An NMOS inverter composed of ET and ET has been used.

However, the substrate of the load MOSFET and the drive MOSFET that constitute the NMOS inverter is
Since the substrate bias voltage VBB is applied, when the substrate bias voltage VBB fluctuates, the threshold voltage Vth of the load MOSFET and the driving MOSFET fluctuates due to the substrate effect, which causes the load MOSFET and the driving MOSFET to change. Conductance gm varies. As a result, the rising speed of the inverter output signal changes due to the change in the conductance gm of the load MOSFET.

On the other hand, the falling speed of the inverter output signal fluctuates due to the fluctuation of the conductance gm of the driving MOSFET. That is, as shown in FIG. 1, in each inverter, when the conductance gm of the load MOSFET increases, the rising speed increases as indicated by the dotted line,
On the contrary, when the conductance gm becomes smaller, the rise becomes slower as indicated by the alternate long and short dash line.

On the other hand, when the conductance gm of the driving MOSFET becomes large, the falling speed becomes fast as shown by the dotted line,
On the contrary, when the conductance gm becomes small, the falling edge becomes slow as indicated by the alternate long and short dash line. Therefore, the fluctuations of the rising and falling speeds of the inverter output signal both cause the fluctuations of the oscillation frequency of the ring oscillator constituted by these inverters, which stabilizes the oscillation frequency and thus the substrate. This is a problem in stabilizing the bias voltage.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device which stabilizes the substrate bias voltage VBB.

[0009]

SUMMARY OF THE INVENTION The purpose is to provide multiple CMOs.
In a semiconductor integrated circuit device having a substrate bias voltage generating circuit including an S inverter and a pump circuit, the substrate bias voltage generating circuit supplies a first substrate bias voltage to a semiconductor substrate. When,
The present invention can be achieved by a semiconductor integrated circuit device including the semiconductor substrate and a second substrate bias voltage generating circuit for supplying a second substrate bias voltage to the semiconductor region of the opposite conductivity type.

[0010]

A first substrate bias voltage generating circuit for supplying a first substrate bias voltage to a semiconductor substrate, and a second substrate bias voltage generating circuit for supplying a second substrate bias voltage to a semiconductor region having a conductivity type opposite to that of the semiconductor substrate. By including a circuit, a stable substrate bias voltage is supplied to the semiconductor substrate and a semiconductor region of a conductivity type opposite to that of the semiconductor substrate, thereby stabilizing the threshold voltage of each MOSFET and reducing the junction capacitance to achieve high speed. It can be activated.

[0011]

Embodiments of the semiconductor integrated circuit device according to the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 2 shows a negative bias voltage -V applied to a P-type substrate.
It is a circuit diagram which shows one Example of the substrate bias voltage generation circuit for supplying BB.

The MOSFETs Q ₁ to Q ₁₃ and the MOS capacitors C ₁ to C ₃ are mounted on a semiconductor integrated circuit device requiring a substrate bias voltage by a known CMOS (complementary metal insulator semiconductor) integrated circuit technology. In this embodiment, in order to stabilize the substrate bias voltage, a CMOS circuit constitutes the substrate bias voltage generating circuit.

N-channel MOSFETs Q ₁ to Q
₃ and P channel MOSFETs Q ₄ to Q _{6 form} three CMOS inverters. These inverters
The ring oscillator OS
C is constructed. Although not particularly limited in this embodiment, the N-channel MOSFET is formed on the P substrate, and the P-channel MOSFET is formed in the N-type well separated from the P-type substrate.

The ring oscillator OSC has a P channel M as a resistance means in order to lower the oscillation frequency.
OSFETs Q ₇ and Q ₈ are inverters (Q ₁ and Q ₄ ), respectively.
It is inserted between the (Q _2, Q ₅₎ and (Q _2, Q ₅₎ and (Q _3, Q _6). The inverter - MOS capacitance C _1, C ₂ are respectively provided to the input terminal of the data (Q _2, Q ₅₎ and (Q _3, Q _6).

Each ring oscillator OSC has a CM.
In order to limit the through current in the OS inverter, the N-channel MOSFET Q is connected to the ground potential side in this embodiment.
A constant current source ₁₃ is provided in common for each of the above inverters. Therefore, for example, the power supply voltage Vcc is applied to the gate of the MOSFET Q ₁₃ .

The oscillation output signal of the ring oscillator OSC is a P-channel MOSFET Q ₁₀ and an N-channel MOSFET Q provided between the power supply voltage Vcc and the ground potential.
_It is transmitted to the next pump circuit PUMP through the inverter constituted by ₉ . The above inverters Q ₉ and Q ₁₀ are
It functions as an amplifier AMP.

The pump circuit PUMP receives the oscillation output signal from the AMP and receives a negative substrate bias voltage -VBB.
To form. That is, the output terminal of the amplifier AMP is connected to one end of the MOS capacitor C ₃ . This MO
Between the other end of the S capacitance C ₃ and the ground potential, an N channel MO
A MOS diode composed of SFET Q ₁₁ is provided.

A MOS diode composed of an N-channel MOSFET Q ₁₂ is provided between the other end of the MOS capacitor C ₃ and the P-type substrate. The MOS diode - de Q _11, as the output level of the amplifier AMP is turned on when a high level as the power supply voltage Vcc, its gate - DOO is connected to the MOS capacitor C ₃ side. Further, the MOS diode - de Q _12, as the output level of the amplifier AMP is turned on when a low level such as the ground potential, its gate - DOO is connected to the P substrate. The operation of this pump circuit PUMP will be described below. Amplifier AM
When the output signal of P is at high level, MOS diode Q
₁₁ is turned on, and the MOS capacitor C ₃ is charged. Next, when the output signal of the amplifier AMP is at the low level, the MO
Since the other end of the S capacitor C ₃ becomes a negative level of about Vcc-VthQ _11, MOS diode - de Q ₁₁ is turned off, MOS diode -
Do Q ₁₂ turns on. Therefore, charge is dispersed in the parasitic capacitance Cp between the substrate and the ground potential of the circuit. Since these operations are repeated according to the oscillation frequency of the ring oscillator OSC, a negative bias voltage -VBB can be supplied to the substrate.

In this embodiment, the CMOS oscillator constitutes a ring oscillator. Therefore, the P-channel MOSFETs Q ₄ to Q ₆ are responsible for forming the high level rising output signal of each inverter. These P-channel MOSFETs Q ₄ to Q
₆ is formed in the N-type well region and is biased by the power supply voltage Vcc. Therefore, even if the substrate bias voltage −VBB changes, the conductance gm becomes constant. As a result, the rise of the output signal in each inverter to the high level becomes constant regardless of the fluctuation of the substrate bias voltage -VBB as shown by the solid line in FIG.

The falling output signals of the respective inverters to the low level are N-channel MOSFETs Q ₁ to Q _3.
As described above, when the conductance gm becomes large due to the influence of the substrate bias voltage −VBB as described above, the falling speed is fast as shown by the dotted line in the figure, and conversely the conductance gm is large. As is smaller, the falling speed becomes slower as shown by the alternate long and short dash line in FIG.

From the above, the rising speed in each inverter becomes constant irrespective of the fluctuation of the substrate bias voltage -VBB, so that the frequency of the ring oscillator OSC is stabilized, and consequently the substrate bias voltage -VBB. Stabilization can be achieved. The fluctuation of the substrate bias voltage -VBB is caused by the increase or decrease of the leak current to the substrate. Further, in this embodiment, P-channel MOSFETs Q ₇ and Q _{8 are} used as resistance means for adjusting the oscillation frequency.
As in the case of the MOSFETs Q ₄ to Q ₆ , the gm thereof is not affected by the fluctuation of the substrate bias voltage −V BB, which helps stabilize the oscillation frequency. Further, in this embodiment, since the CMOS inverter is used, when the input signal is stable at the high level or the low level, the direct current is not consumed, so that the power consumption can be reduced. Further, in this embodiment, in order to further reduce the power consumption, a constant current MOSF is used.
ETQ ₁₃ is provided. The gate of the MOSFET Q ₁₃ - because DOO to the power supply voltage Vcc is applied, by flowing the drain current in a saturation region, performs a current limiting operation. That is, when the input signals of the respective inverters change, a relatively large through current flowing through the P-channel MOSFET Q ₄ etc. and the P-channel MOSFET Q ₁ etc. can be limited by providing the MOSFET Q ₁₃ , so that it becomes even lower. Power consumption can be reduced. Further, since the CMOS inverter is used as the amplifier, the amplitude of the pulse signal supplied to the pump circuit PUMP can be increased up to the power supply voltage Vcc level. Moreover, the output high level (Vcc-Vth), like an amplifier using N-channel load MOSFET,
It also has the advantage that it is not subject to variations in the substrate bias voltage -VBB. Therefore, a large level of the substrate bias voltage -VBB can be obtained without using a special bootstrap circuit.
Can be formed. As described above, a stable and large substrate bias voltage -VBB is obtained. Therefore, the threshold voltage of the N-channel MOSFET of the semiconductor integrated circuit device equipped with the substrate bias voltage generating circuit according to this embodiment is stabilized and the junction capacitance is increased. It is possible to realize high-speed operation by reducing the number of times, and it is possible to realize stable operation that can withstand the undershoot of the input waveform.

In FIG. 4, the power supply voltage Vcc is applied to the N-type well region.
A circuit diagram of an embodiment of the substrate bias voltage generating circuit for supplying the positive bias voltage + VBB is shown. This embodiment circuit is a P-channel MOSFET.
Substrate bias voltage + VBB for Q ₄ 'or Q ₆ ' and Q ₁₀ '
Is applied, and the ground potential is applied to the substrate of the N-channel MOSFETs Q ₁ ′ to Q ₃ ′. Except for this point, the ring oscillator OSC and the amplifier AMP of the circuit of this embodiment are the same as those of the circuit of FIG. Pump circuit PU
MP is a positive substrate bias voltage + V above the power supply voltage Vcc
To form the BB, MOS diode - with de Q ₁₁ 'is provided in the power source voltage Vcc side, the output level of the amplifier AMP is to be turned on when a low level.
The MOS diode - de Q ₁₂ ', the output level of the amplifier AMP is to be turned on when the high level.
In the operation of the pump circuit PUMP, when the output signal of the amplifier AMP is at low level, the MOS diode Q ₁₁ ′ turns on and the MOS capacitor C ₃ is charged. And amplifier A
When the output signal of MP is at high level, the MOS capacitance C
Due to the bootstrap effect of ₃ , a high level higher than the power supply voltage Vcc level is formed, and the parasitic capacitance between the N-type well and the substrate (ground potential) through the MOS diode Q ₁₂ 'which is turned on at this time. Since it is transmitted to Cw, the substrate bias voltage + VBB can be formed. In this embodiment, since the conductance of the N-channel MOSFET is constant regardless of the positive substrate bias voltage + VBB, the oscillation frequency of the ring oscillator OSC is stabilized and the substrate bias voltage + VBB is stabilized in the same manner as described above. You can Further, in this embodiment, the power consumption can be reduced by the CMOS circuit and the power consumption can be reduced by limiting the through current of the MOS inverter by the constant current MOS Q ₁₃ ′ in the same manner as described above.

FIG. 5 is a circuit diagram of a substrate bias voltage generating circuit showing another embodiment. This embodiment circuit shows a modified example of FIG. 2, and the ring oscillator
A constant current source by a P-channel MOSFET Q ₁₄ is also provided on the power supply voltage Vcc side of the OSC. The ground potential is applied to the gate of the MOSFET Q ₁₄ . In this way, the ground potential and the power supply voltage Vcc
Since MOSFETs Q ₁₃ and Q ₁₄ as constant current sources are provided on both sides, the output amplitude of the ring oscillator can be further reduced, so that power consumption can be reduced. Further, as another modification, in the circuit of FIG.
Constant current MOSF by P channel on power supply voltage Vcc side
ET may be provided. Further, the MOSFETs Q ₇ and Q _{8 serving} as resistance means are N-channel MOSFETs.
It may be one using T or another resistance means. Then, these MOSFETs Q ₇ , Q ₈ and M
The OS capacities C ₁ and C ₂ may be omitted. However, when a comparatively low oscillation frequency is formed by an inverter with a small number of stages, the above resistance means and MOS capacitance are required. As the pump circuit PUMP in the embodiments of FIGS. 2 and 4 and 5, the N-channel MOSFET Q is used.
_The reason why the MOS diode composed of ₁₁ and Q ₁₂ is used is that its response is higher than that in the case where a P-channel MOSFET is used. If you don't care about this responsiveness,
A MOS diode may be configured using a P-channel MOSFET, or another unidirectional element may be used. Further, the constant current MOSFET may be omitted, and in this case, the amplifier AMP may be omitted.

The substrate bias voltage generating circuit as shown in FIG. 2 and / or FIG. 4 is not particularly limited, but a semiconductor integrated circuit forming a CMOS dynamic RAM (random access memory) as described below. Installed in the device.

Hereinafter, the CMOS dynamic RAM is simply abbreviated as D-RAM.

[Configuration and Operation of D-RAM] D-RAM
The configuration will be described with reference to FIG. A block surrounded by a dotted line shows a D-RAM integrated circuit (hereinafter referred to as an IC). In the above IC, the block surrounded by the chain double-dashed line is a timing pulse generation block, and the block
It is composed of a circuit that generates a signal for controlling the operation of each circuit of the AM.

Next, the operation of each circuit of the D-RAM will be described with reference to the timing chart of FIG.

When the row address signals A _{0 to} Ai are taken into an address buffer (hereinafter referred to as ADB) and latched, the row address signals A _{0 to} Ai are delayed and RAS.
The signal goes low. Here, the reason for delaying the RAS signal from the row address signal A ₀ ~Ai row address signal A ₀ to A as the row address in the memory array
This is to ensure that i is captured. Next, the signal φ _AR delayed from the RAS signal is applied to ADB, and the levels a ₀ , a ₀ , ---- a corresponding to the latched row address signal are given.
i and ai are row / column decoders (hereinafter RC-DCR).
Called. ). The above level a in RC-DCR
_{When 0} , a ₀ , ai, and ai are applied, the RC-DCR remains at the high level only for the selected one, and goes to the low level for the unselected one. Then, when the signal φx delayed from φ _AR is applied to RC-DCR, the selected signal is sent to M-ARY. Where φx is φ
_The reason for delaying after _AR is RC-DC after the operation of ADB is completed.
This is for operating R. In this way, the row address in the M-ARY has ^one of the 2 ^{i + 1} output signals of the RC-DCR at the high level, so that one row address line in the M-ARY corresponding thereto is selected. It is set by

Next, "1" of the memory cell connected to one selected row address line in M-ARY.
Alternatively, information of "0" is amplified by a sense amplifier (hereinafter referred to as SA). The operation of SA starts when φ _PA is applied. After that, the column address signal Ai
When +1 to Aj are taken into ADB and latched, the CAS signal becomes low level later than the column address signals Ai + 1 to Aj. The reason for delaying the CAS signal with respect to the column address signals Ai + 1 to Aj is to reliably capture the column address signal as a column address in the memory array. Next, when the signal φ _AC delayed from the CAS signal is applied to ADB, the levels ai + 1, ai + 1 , ----, aj, corresponding to the column address signal are obtained.
aj is sent to RC-DCR. And RC-DCR
Performs the same operation as above. When the signal φY delayed from φ _AC is applied to RC-DCR, the selected signal is sent to the column switch (hereinafter referred to as C-SW). In this way, the column address in the M-ARY becomes one of the 2j-1 output signals of the RC-DCR at a high level, so that one C-SW is selected and the column connected to this C-SW is selected. It is set by selecting the address line, that is, the data line. In this way, one address in M-ARY is set.

Next, the read and write operations for the addresses set as above will be described. In the read mode, the WE signal becomes high level.

This WE signal is designed so that it becomes high level before the CAS signal becomes low level. Because, when the CAS signal becomes low level, the result is MA
Since one RY address is set, W
This is because the E signal is set to the high level and the read operation is prepared to shorten the read start time.

Further, when φ _{OP of the} CAS system signal is applied to the output amplifier, the output amplifier becomes active, the information of the above-mentioned address is amplified, and it is passed through the data output buffer (hereinafter referred to as DOB). Data output (Do
ut) terminal. Reading is performed in this manner, but the reading operation is completed when the CAS signal becomes high level.

Next, in the write mode, the WE signal becomes low level. When the signal φ _{RW generated} by the low level WE signal and the low level CAS signal becomes high level and is applied to the data input buffer (hereinafter, referred to as DIB), the DIB becomes active and the input data (Din) terminal. Write data from the above
The data is sent to the address set in RY and the write operation is performed.

At this time, the inverted signal of φ _RW , that is, the low-level signal φ _RW is applied to DOB, and control is performed so that data is not read during the write operation.

[Structure and Operation of D-RAM Transistor Circuit] FIG. 8A shows an embodiment of a D-RAM circuit configuration in which the substrate bias voltage generating circuit of the present invention is used. Less than,
The present invention will be described based on examples.

1. Configuration of Memory Cell M-CEL The 1-bit M-CEL is composed of a capacitor C _S for information storage and a P-MOS Q _M for address selection. Information of logic “1” or “0” is stored in the capacitor C _S. It is memorized whether or not there is.

The gate of the P-MOS Q _M is connected to the word line, one of the source / drain is connected to the data line, and the other is connected to the capacitor C _S.

2. Switching operation of the memory cell M-CEL The gate voltage of the P-MOSQ _M , that is, the word voltage is changed from the power supply voltage V _CC to the threshold voltage Vthp (P-MOSQ
P-MOSQ _M turns on when the voltage decreases by (threshold voltage of _M ), and the memory cell M-CEL can be selected.

When an N-MOS is used for the memory cell (not shown), the word voltage is changed from 0V to (Vcc-
When Vthn) (Vthn; threshold voltage of N-MOSQ _M ) is changed, N-MOSQ _M is turned on and a memory cell can be selected.

Therefore, the switching speed of the P-MOSQ _M is only between Vcc and | Vthp |
Since "0" information can be determined, it is considerably faster than the switching speed of N-MOSQ _M. Since the detailed description of the switching operation of the PMOS Q _M is described in Japanese Patent Application No. 54-119403, its description is omitted.

3. Configuration of Sense Amplifier The sense amplifiers SA ₁ and SA ′ ₁ sense the difference in potential change occurring in the folded data lines DL _1-1 and DL _1-1 at the time of address by the timing signals φ _PA and φ _PA (sense amplifier control signal). This is a sense amplifier that expands during the period, and its input / output node is coupled to a pair of folded data lines DL _1-1 and DL _1-1 arranged in parallel.

The sense amplifiers SA ₁ and SA ′ ₁ are connected in parallel, and although both can be considered as one sense amplifier, SA ′ ₁ is composed of an N-MOS, whereas SA _{1 is} Is composed of P-MOS of opposite conductivity type. Each sense amplifier has a pair of cross-connected Fs for performing positive feedback differential amplification operation.
ET and FET connected to the source side thereof to control the positive feedback differential amplification operation.

Since the sense amplifiers SA ₁ and SA ′ ₁ can be considered as one complementary sense amplifier as described above, they may be arranged adjacent to each other, but the arrangement and shape of wirings, transistors, well regions, etc. In consideration of the above, it is possible to arrange them apart from each other (for example, at both ends of M-ARY) as shown in FIG.
That is, the sense amplifier SA composed of P-MOS
₁ and the memory array M-ARY and the sense amplifier SA ' ₁ composed of N-MOS and the precharge circuit PC can be arranged separately, the circuit arrangement in the chip is PM.
The OS part and the N-MOS part can be separated from each other and can be efficiently integrated.

The folded data lines DL _1-1 and DL _1-1 are A
It is formed of a metal such as 1, Au, Mo, Ta, and W.
Since the metal has a very small resistance value, the voltage drop of the data line during operation is small, and no malfunction occurs.

4. Configuration of Precharge Circuit The precharge circuit PC is a pair of N-MOSQ for precharging to about half (V _DP ) of the power supply voltage Vcc.
_It consists of _S2 , Q _S3 and an N-MOS Q _S1 for eliminating the imbalance of the precharge voltage between both data lines, and these N-MOSs are the other N-MOSs as indicated by the symbol * in the figure.
Designed to have a lower threshold voltage than MOS.

The number of memory cells coupled to the folded data lines DL _1-1 , DL _1-1 is made equal in order to improve the detection accuracy. Each memory cell is coupled between one word line WL and one of the folded data lines. Since each word line WL intersects with a pair of data lines, even if the noise component generated in the word line WL is on the data line due to electrostatic coupling, the noise component appears equally in both data lines, and the difference is generated. This is canceled by the dynamic sense amplifiers SA ₁ and SA ′ ₁ .

5. Circuit Operation The circuit operation of FIG. 8A will be described with reference to the operation waveform diagram of FIG. 8B.

When the precharge control signal φ _PC is at the high level (higher than Vcc) before the storage signal of the memory cell is read out, the N-MOSs Q _S2 and Q _S3 become conductive and the folded data lines DL _1-1 and DL. _1-1 stray capacitance C _o , C _o is about 1/2 Vc
Precharged to c. At this time, since the N-MOSQ _{S1 is} also turned on at the same time, even if the precharge voltage due to the N-MOSQ _S2 and Q _S3 becomes unbalanced, the folded data line DL
_1-1 and DL _1-1 are short-circuited and set to the same potential. N-MO
SQ _{S1 to} Q _S3 are Vt as compared with the transistor without * mark so that voltage loss between source and drain does not occur.
h is set low.

On the other hand, the capacitor C _S in the memory cell holds the potential of almost zero volt when the written information is logic "0", and holds the potential of approximately Vcc when the written information is logic "1". The line precharge voltage V _DP is set to the middle of both storage potentials.

Therefore, when the word line control signal φ _x becomes high level and a desired memory cell is addressed, the potential V _DL of one data line coupled to the memory cell is
When the information of "1" is read, it becomes higher than V _DP ,
When "0" information is read, it becomes lower than V _DP . Determining whether the information of the addressed memory cell is "1" or "0" by comparing the potential of the data line with the potential of the other data line that maintains the potential of V _DP. You can

The positive feedback differential amplification operation of the sense amplifiers SA ₁ and SA ₂ is started when the FETs Q _S9 and Q _S4 start to conduct by the timing signals (sense amplifier control signals) φ _PA and φ _PA . On the basis of the potential difference, the higher data line potential (V _H ) and the lower data line potential ( _VL ) change toward Vcc and the zero potential V _GND , respectively, and the difference widens. N-MOS Q _S7 , Q _S8 , Q _S9
The sense amplifier SA ' _{1 which} is made up of the above-mentioned element contributes to lower the potential of the data line to the zero potential V _GND , and the P-MOS
The sense amplifier SA ₁ from Q _S4 , Q _S5 , and Q _S6 contributes to raising the potential of the data line to Vcc. Each of the sense amplifiers SA ₁ and SA ′ ₁ operates in the source ground mode.

[0053] Thus (V _L -V _GND) potential sense amplifier SA _'1 of N-MOSQ _S7 of, Q _S8 of the threshold voltage Vt
When it becomes equal to hn, the positive feedback operation of the sense amplifier SA ′ ₁ ends. The P-MOSQ _S5 potential of (Vcc-V _H) the sense amplifier SA _1, the threshold voltage of Q _S6 V
_When it becomes equal to _thp , the positive feedback operation of the sense amplifier SA ₁ ends. Finally, V _L becomes zero potential and V _H becomes Vcc.
Reaches and becomes stable in the low impedance state.

[0054] In addition, the sense amplifier SA ₁ and SA 'be allowed to start operating ₁ at the same time, SA' even if _one is operated start earlier than the SA _1, and the SA ₁ SA 'earlier to start operating from ₁ Either is fine. In terms of read speed, SA ₁ and SA ' ₁
It is faster to operate both at the same time, but since a through current flows, power consumption increases. On the other hand, SA ₁ or S
By making the operation start timing of A ′ ₁ different, there is an advantage that the through current is eliminated and the power consumption is reduced, but the reading speed is slightly inferior to the above.

FIG. 8C shows another embodiment of the circuit configuration of the D-RAM in which the substrate bias voltage generating circuit of the present invention is used. The parts corresponding to those in FIG. The difference from FIG. 8A is that the positive feedback operation control means of SA ′ ₁ is N-
The point is that the MOS Q _S9 and Q _S10 are connected in parallel.

The operation of the sense amplifiers SA ₁ and SA ' ₁ will be described with reference to FIG. 8D. The return data line is about 1 in advance.
It is assumed that the battery is charged to / 2Vcc.

When the FET Q _S10 of the positive feedback operation control means of the sense amplifier SA ′ ₁ is turned on by the sense amplifier control signal φ ₁ , only one of the FET Q _S7 or the FET Q _S8 is turned on and the potential of the lower data line (V _L ) is slightly lowered toward the zero potential V _GND . At this time, the potential (V _H ) of the higher data line is 1 of FET Q _S7 or FET Q _S8 .
Since it is non-conductive, it does not change. The conductance of the FET Q _S10 is designed to be smaller than that of the FET Q _S9 .

Next, by the sense amplifier control signal φ _PA , F
When the ETQ _S9 starts to conduct, the sense amplifier SA ′ ₁ starts the positive feedback operation and changes the potential V _L toward the zero potential V _GND .

That is, the sense amplifier control signal φ ₁ is used to slightly widen the potential difference of the folded data line, and then the sense amplifier control signal φ _PA is applied to sense amplifier SA ′ ₁
If the positive feedback operation is performed, the sense amplifier SA ′ ₁ can amplify even if the potential difference of the folded data line is small. In other words, the sensitivity of the sense amplifier is improved.

Next, in the positive feedback differential amplification operation of the sense amplifier SA ₁ , the FET Q _S4 is operated by the sense amplifier control signal φ _PA or φ.
_It starts when it starts to conduct by ₂ and the potential (V _H ) of the higher data line rises toward Vcc.

The potential of the data line finally reaches zero potential for V _L and reaches Vcc for V _H , and becomes stable in a low impedance state.

FIG. 8E shows another embodiment of the circuit configuration of the D-RAM in which the substrate bias voltage generating circuit of the present invention is used. The parts corresponding to those in FIG. 8A are denoted by the same reference numerals. The difference from FIG. 8A is that the dummy cell DC is provided on the folded data line.
This is the point where the EL is connected. The dummy cell D-CEL is composed of a series connection circuit of P-MOSQ _D1 and P-MOSQ _D2. The gate of P-MOSQ _D1 is a dummy word line, one of source / drain is a data line, and the other is P-M.
It is connected to one of the source and drain of OSQ _D2 ,
The other is grounded.

The dummy cell D-CEL does not require the capacitance C _DS for storing the reference potential. This is because the data line is precharged with the reference potential. Dummy cell D-CE
L is made under the same manufacturing conditions and the same design constants as the memory cell M-CEL.

The dummy cell D-CEL has a function of canceling out various noises generated in the folded data line at the time of writing and reading memory information.

[Time-series Operation of D-RAM Transistor Circuit] The time-series operation of the D-RAM transistor circuit will be described with reference to FIG. 8A. 1. Read-out signal amount For reading information, P-MOSQ _M is turned on to connect C _S to the common column data line DL, and what kind of change occurs in the potential of the data line DL depending on the amount of charge accumulated in C _S. It is done by sensing. Data line DL
If the potential previously charged in the stray capacitance C ₀ is half the power supply voltage, that is, 1/2 Vcc, if the information stored in C _S is “1” (potential of Vcc), the data line DL at the time of addressing. Potential (V _DL ) “1” is V
cc · (C _O + 2C _S ) / 2 (C _O + C _S ), and when it is “0” (0V), (V _DL ) “1” is Vcc ·
It becomes C _O / 2 (C _O + C _S ). Here, the difference between the logic "1" and the logic "0", that is, the detected signal amount ΔV _S is ΔV _S = (V _DL ) “1” − (V _DL ) “0” = V _CC · C _S / (C ₀ + C _S ) = (C _S / C _S ) · V _CC / {1+ (C _S / C _O )}.

Since the size of the memory cell is small and the memory matrix has a high integration and a small capacity even if many memory cells are connected to the common data line, C _S << C ₀ , that is, (C
_S / C ₀ ) is almost negligible with respect to 1. Therefore, the above equation is represented by ΔV _S ≈V _CC · (C _S / C ₀ ), and ΔV _S is a very small signal.

2. Read operation precharge period This is exactly the same as the above precharge operation.

The row address signals A ₀ to A _J supplied from the address buffer ADB at the timing of the row address period timing signal (address buffer control signal) φ _AR (see FIG. 7) are decoded by the row / column decoder RC-DCR. , The addressing of the memory cell M-CEL is started at the same time when the word line control signal φ _X rises.

As a result, the folded data lines DL _1-1 , DL
As described above, a voltage difference of approximately ΔV _S occurs between _{1-1 due to} the stored contents of the memory cell.

[0070] sensing timing signal (sense amplifier control signal) by phi _PA N
-At the same time that MOSQ _S9 begins to conduct, the sense amplifier S
A ′ ₁ starts the positive feedback operation, and ΔV _S generated at the address
The detection signal of is amplified. The sense amplifier S by the amplifying operation simultaneously with or amplification after starting operation timing signal phi _PA
A ₁ starts the positive feedback operation and changes the level of logic "1" to V _CC.
Recover to.

The column address signals Ai + 1 to Aj sent from the address buffer ADB in synchronization with the data output operation timing signal (address buffer control signal) φ _AC are decoded by the row / column decoder RC-DCR, and then the timing signal ( Column switch control signal) φ _Y stores the memory information of the memory cell M-CEL at the column address via the column switch C-SW ₁ and the common input / output line CDL ₁ ,
It is transmitted to CDL ₁ .

Next, the output signal / data output buffer OA & DOB is operated by the timing signal (data output buffer and output amplifier control signal) φ _OP , and the read storage information is sent to the output terminal Dout of the chip. Note that this OA & DOB is made inoperative by a timing signal (data output buffer control signal) φ _RW during writing.

3. Write operation Row addressing period Precharge, addressing, and sensing operation are exactly the same as the read operation described above. Therefore, regardless of the logical value of the input write information D _1n , the stored information of the memory cell to be originally written is read to the folded data lines DL _1-1 , DL _1-1 . Since this read information is to be ignored by the write operation to be described later, it can be considered that the row address is selected in the operations up to this point.

Similar to the read operation during the write period, the folded data lines DL _1-1 and DL _1-1 located in the selected column in synchronization with the timing signal (column switch control signal) φ _Y are the column switches C-S.
The common input / output lines CDL ₁ and CDL ₁ are coupled via W ₁ .

Next, the complementary write input signals d _1n and d _1n supplied from the data input buffer DIB in synchronization with the timing signal (data input buffer control signal) φ _RW are transferred to the memory cell M via the column switch C-SW _1. Written to CEL. At this time, the sense amplifier SA is also operating, but the output impedance of the data input buffer DIB is low. Therefore, the information appearing on the folded data lines DL _1-1 and DL _1-1 is determined by the information on the input D _1n .

4. Refresh Operation In the refresh operation, the lost information stored in the memory cell M-CEL is read to the shared column common data line DL, and the read information is set to the level restored by the sense amplifiers SA ₁ and SA ′ ₁ and the memory cell is restored again. This is done by writing to M-CEL. Therefore, the refresh operation is the same as the operation in the row addressing or sensing period described in the read operation. However, in this case, the column switch C-SW ₁ is made inoperative, and all columns are refreshed simultaneously and in each row order.

[2-mat type 64K-D-RAM circuit configuration] FIG. 9A shows memory cells of about 64K bits each having 128 columns (rows) × 256 rows (columns) = 32.76.
Two memory cell matrices (memory arrays M-ARY ₁ , M-A) having a storage capacity of 8 bits (32 Kbits)
3 shows a D-RAM circuit configuration diagram divided into RY ₂ ) and arranged. The main blocks in this figure are drawn according to the actual geometrical arrangement.

Each memory array M-ARY ₁ , M-ARY ₂
The row-related address selection line (word line WL) of 2 ⁷ = 128 obtained on the basis of the row address signals A _{O to} A _6.
Deco Street - de output signals, each Roudeko - Da (Kenwa - de driver) is applied from the _{R-DCR 1, R-DCR} 2.

The column decoder C-DCR provides 128 decoding output signals based on the column address signals A _{9 to} A ₁₅ . This column selection decode output signal is common to the left and right memory arrays and the adjacent upper and lower columns in each memory array, that is, to a total of four columns.

Address signals A ₇ and A ₈ are assigned to select any one of these four columns. For example, A ₇ is assigned to left / right selection, and A ₈ is assigned to up / down selection.

The φ _yij signal generating circuit φ _yij -SG decodes into four combinations based on the address signals A ₇ and A _8.
And their output signals φy ₀₀ , φy ₀₁ , φy ₁₀ , φy ₁₁
Switch the column is a column switch selectors _{CSW-S 1, CSW-S} 2 based on. Thus, the decoder for selecting the column of the memory array is the column decoder C-DCR and the column switch selector C.
It is divided into two stages, SW-S ₁ and CSW-S ₂ . The purpose of dividing the decoder into two stages is, first of all, to prevent useless blank portions from occurring in the IC chip. That is, the vertical array interval (pitch) of the NOR gates having a relatively large area that carries the pair of left and right output signal lines of the column decoder C-DCR is adjusted to the column array pitch of the memory cells. That is, by dividing the decoder into two stages, the number of transistors forming the NOR gate can be reduced and the occupied area can be reduced.

The second aim of dividing the decoder into two stages is to reduce the number of NOR gates connected to one address signal line, thereby reducing the load of one address signal line and switching speed. To improve.

The address buffer ADB has eight multiplexed external address signals A _{0 to} A ₇ ; A respectively.
_{8 to} A ₁₅ are eight complementary pair address signals (a ₀ , a ₀ ) to (a ₇ , a ₇ ): (a ₈ , a ₈ ) to (a ₁₅ ,
a ₁₅ ) and send it to the decoder circuit at timings φ _AR and φ _AC that match the operation in the IC chip.

[2 Mat System 64K-D-RAM Circuit Operation] The circuit operation of the address setting process in the 2-mat system 64K-D-RAM will be described with reference to FIGS. 9A and 9B.

First, a row address buffer control signal φ
_{When AR} rises to the high level, seven types of complementary paired row address signals (a ₀ , a ₀ ) to (a ₆ , a ₆ ) corresponding to the row address signals A _{0 to} A ₆ are generated in the address buffer ADB.
From the row decoder R via the row address line R-ADL
-DCR ₁ and R-DCR ₂ are applied.

Next, when the word line control signal φ _X rises to the high level, the row decoders R-DCR ₁ and R-
DCR ₂ becomes active and each memory array M-AR
One of each of the word lines WL of Y ₁ and M-ARY ₂ is selected and set to the high level.

Next, when the column-system address buffer control signal φ _AC rises to the high level, seven types of complementary paired column address signals (a ₉ , a ₉ ) corresponding to the column address signals A ₉ -A ₁₅ are generated. (A ₁₅ , a ₁₅ ) is applied from the address buffer ADB to the column decoder C-DCR via the column address line C-ADL.

As a result, the column decoder C-DCR 12
One of the eight pairs of output signal lines has a high level, and this high level signal causes the column switch selector CSW-S ₁ ,
It is applied to CSW-S ₂ .

Next, when the column switch control signal φ _Y rises to the high level, the φ _y1j signal generating circuit φ _y1j -SG becomes operable.

On the other hand, the complementary pair signals (a ₇ , a ₇ ) already corresponding to the address signal A ₇ are the address buffer control signals φ.
_{When AR} goes high, the address signal A ₈
Complementary pair signals (a ₈ and a ₈ ) corresponding to are respectively generated by φ when the address buffer control signal φ _AC becomes high level.
It is applied to the _y1j signal generating circuit φ _y1j −SG. Therefore, when the column switch control signal φ _Y goes high, the φ _y1j signal generating circuit φ _y1j -SG sends a signal to the column switch selectors CSW-S ₁ and CSW-S ₂ almost at the same time.

In this way, the column switch C-SW
₁ , a pair of 512 transistor pairs in total in C-SW ₂ is selected, and a pair of data lines D in the memory array is selected.
L is connected to the common data line CDL.

[2-mat D-RAM IC Layout Pattern] A so-called 2-mat D-RAM IC layout pattern in which the memory array is divided into two in one IC chip will be described with reference to FIG.

First, the two memory arrays M-ARY ₁ and M-ART ₂ formed by a plurality of memory cells are arranged in the IC chip so as to be separated from each other.

I between this M-ARY ₁ and M-ARY ₂
A common column decoder C-DCR is arranged in the center of the C chip.

Column switch C for M-ARY ₁
SW ₁ is arranged between M-ARY ₁ and C-DCR.

[0096] On the other hand, the column switches CSW ₂ for M-ARY ₂ is disposed between the M-ARY ₂ and C-DCR.

The sense amplifiers SA ₁ and SA ₂ are provided at the left end portion and the right end portion of the IC chip respectively in order to prevent malfunction due to noise, for example, a signal applied to the C-DCR and to facilitate wiring layout. It is arranged.

On the upper left side of the IC chip, a data input buffer DIB and a read / write signal generation circuit R / WS.
G, RAS signal generation circuit RAS-SG and RAS system signal generation circuit SG ₁ are arranged. Then, close to these circuits, the RAS signal application pads P- RAS , WE
Signal application pad P- WE , data signal application pad P-D
in is placed.

On the other hand, on the upper right side of the IC chip, a data output buffer DOB and a CAS signal generating circuit CAS-SG are provided.
And a CAS signal generation circuit SG ₂ are arranged.

Then, in proximity to these circuits, the V _SS voltage supply pad P-V _SS and the CAS signal application pad P- CA are provided.
S , a data signal extraction pad P-Dout and an address signal A ₆ supply pad P-A ₆ are arranged.

A main amplifier MA is arranged between the RAS system signal generation circuit SG ₁ and the CAS system signal generation circuit SG ₂ .

A V _BB generating circuit V _BB -G is arranged above a circuit having a large occupied area such as the RAS related signal generating circuit SG ₁ , the CAS related signal generating circuit SG ₂ or the main amplifier MA. This is because V _BB -G generates minority carriers, and this minority carrier causes M-ARY ₁ , M.
There is a risk that the memory cells that make up -ARY ₂ will suffer unwanted information inversion. Therefore, in order to prevent this, the V _BB generation circuit V _BB -G has the above-mentioned M-ARY ₁ ,
It is arranged as far away as possible from M-ARY ₂ .

[0103] The row decoder R-DCR ₁ for M-ARY ₁ at the bottom left of the IC chip is disposed. Address signal supply pads P-A ₀ , P-A ₁ , P-A ₂ and V _CC voltage supply pad P-V _CC are arranged in proximity to R-DCR ₁ .

On the other hand, on the lower right side of the IC chip, M-A
A row decoder R-DCR ₂ for RY ₂ is arranged. Then, the address signal applied pad P-A ₃ close to the row decoder _{R-DCR 2, P-A} 4, P-A 5,
P-A ₇ is arranged.

An address buffer ADB is arranged between R-DCR ₁ and R-DCR ₂ .

[Layout Pattern Diagram of Power Supply Line] A partial layout pattern diagram centering on the memory array M-ARY and the sense amplifiers SA ₁ and SA ′ ₁ in the 64-Kbit D-RAM will be described with reference to FIG. 11A. .. M-ARY and SA ₁ are formed in separate N-channel well regions surrounded by alternate long and short dash lines. In addition,
Since the M-ARY and SA ₁ etc. are line-symmetrical with respect to the column decoder C-DCR, M-ARY and SA ₂ , SA ′ ₂ etc. in the right well region are omitted.

Since the power supply voltage Vcc is supplied to the N-channel well, the power supply line Vcc-L is formed as shown in FIG. 7A.

In FIG. 11A, assuming that M-ARY _1-1 is one row, a power supply line is formed every 32 rows of M-ARY.

Since the well voltage becomes more nonuniform as the distance between the power supply lines becomes larger, the power supply lines are connected to each M-
The ARY may be formed for each row, but since the chip area becomes large, it may be formed for every 8 rows, every 16 rows, every 32 rows, every 64 rows, etc. so that each M-ARY has an equal interval. preferable.

In order to make the well voltage uniform, the power supply line is made of Al, Au, which has almost no voltage loss.
It is made of metal such as M ₀ and Ta. When forming a power supply line made of the above metal in the well, A
It is preferable to arrange the data lines in parallel with the data lines so as not to short-circuit with the data lines formed by l.

The reason why the N-channel well region is separated by the memory array M-ARY and the sense amplifier SA ₁ is as follows.

[0112] Voltage drop between the positive feedback operation control means of the power supply line and the sense amplifier SA in the _first well region in the sense amplifier SA ₁ (not shown) occurs, sense amplifiers SA away from the power supply line As the voltage drop increases by ₁ , the voltage drop becomes noise. If the memory array M-ARY and the sense amplifier SA ₁ are formed in the N-type well region, the well potential is lowered by the voltage drop, and the P-MOSQ of the memory cell is formed.
_This lowers the threshold voltage V _TH of _M (not shown). Then, the P-MOS Q _M is easily turned on, which causes a malfunction.

Memory array M-ARY and sense amplifier S
By independently forming the N-channel well regions forming A ₁ , the noise generated in the sense amplifier SA ₁ does not affect the memory operation.

FIG. 11B shows a memory array M-ARY and a sense amplifier SA _{1 in} a 64 K-bit D-RAM.
SA 'shows a layout pattern diagram of a portion around the _1.

Portions corresponding to those in FIG. 11A are designated by the same reference numerals.

The difference from FIG. 11A is that the memory array M-ARY and the sense amplifier SA ₁ are provided in the same well region.
Is the point of forming.

In terms of chip area, there is an advantage that it is smaller than the chip area according to the layout of FIG. 11A. However, as described above, there is a drawback that the noise generated in the sense amplifier SA ₁ easily affects the memory operation.

[0118]

According to the present invention, a first substrate bias voltage generating circuit for supplying a first substrate bias voltage to a semiconductor substrate, and a second substrate bias voltage to a semiconductor region of a conductivity type opposite to that of the semiconductor substrate are provided. By having a second substrate bias voltage generating circuit for supplying, a stable substrate bias voltage is supplied to the semiconductor substrate and a semiconductor region of a conductivity type opposite to that of the semiconductor substrate, thereby stabilizing the threshold voltage of each MOSFET. It is possible to achieve high-speed operation by increasing the number of devices and reducing the junction capacitance.

[Brief description of drawings]

FIG. 1 is an output waveform diagram of an inverter in a conventional ring oscillator.

FIG. 2 is a circuit diagram showing an embodiment of a substrate bias voltage generating circuit according to the present invention.

FIG. 3 is an inverter output waveform diagram for explaining the operation.

FIG. 4 is a circuit diagram showing another embodiment of the substrate bias voltage generating circuit according to the present invention.

FIG. 5 is a circuit diagram showing another embodiment of the substrate bias voltage generating circuit according to the present invention.

FIG. 6 is a D-RAM block diagram.

FIG. 7 is a timing diagram of a D-RAM.

FIG. 8A is a D-RAM block diagram of one embodiment of the present invention.

FIG. 8B is a D-RAM timing diagram of one embodiment of the present invention.

FIG. 8C is a D-RAM block diagram of another embodiment of the present invention.

FIG. 8D is a D-RAM timing diagram for another embodiment of the present invention.

FIG. 8E is a D-RAM block diagram of another embodiment of the present invention.

FIG. 9A is a circuit configuration diagram of a 2-mat type 64KD-RAM.

FIG. 9B is a 2-MAT type 64KD-RAM timing diagram.

FIG. 10 is a layout pattern diagram of a 2-mat type D-RAM IC.

FIG. 11A is another two-mat type D-.
It is a RAMIC layout pattern figure.

FIG. 11B shows another 2-mat type D-.
It is a RAMIC layout pattern figure.

[Explanation of symbols]

_{SA 1, SA '1, SA} 2, SA' 2 ... sense amplifier PC ... precharge circuit CDL, CDL ... common data line M-CEL ... memory cells D-CEL ... dummy MA ... main amplifier V _CC-L ... well Power Supply line V _SS-L ... Ground voltage supply line DL, DL ... Data line WL ... Word line WE ... Write enable signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/108 // H01L 29/78

Claims (3)

[Claims] 1. A semiconductor integrated circuit device having a substrate bias voltage generating circuit including a plurality of CMOS inverters and a pump circuit, wherein the substrate bias voltage generating circuit supplies a first substrate bias voltage to a semiconductor substrate. A first substrate bias voltage generation circuit and a second substrate bias voltage supply circuit for supplying a second substrate bias voltage to a semiconductor region having a conductivity type opposite to that of the semiconductor substrate.
A semiconductor integrated circuit device comprising a substrate bias voltage generating circuit. 2. The semiconductor integrated circuit device according to claim 1,
A dynamic RAM in which the peripheral circuit is composed of a CMOS circuit and the memory array portion is formed in the well region.
A semiconductor integrated circuit device characterized by: 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor region having a conductivity type opposite to that of the semiconductor substrate is a well region.