JPH05210645A - Parallel processing system and compiling method therefor - Google Patents

Abstract

PURPOSE:To handle data of a large scale at a comparatively high speed by constituting the system so that data defined or referred to by only a subsystem can be secured in a built-in extension storage device in the subsystem. CONSTITUTION:A parallel computer system is constituted by preparing plural subsystems consisting of main storage devices 2, 4, and at least one set of instruction processors 8-11 connected to its main storage devices 2, 4 and for executing an instruction, connecting each of them by a shared extension storage device 3, and also, connecting built-in extension storage devices 1, 5 as secondary storage of the main storage devices 2, 4. In a compiler for such a parallel system, with regard to a declaration for arranging data in the built-in extension storage devices 1, 5 or the shared extension storage device 3, the same description is contained in a source program, a range of a subprogram defined or referred to its data is analyzed, and whether its data is secured in the built-in extension storage device 3 or the shared extension storage devices 1, 5 is determined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a loosely coupled multiprocessor system and a compiling method therefor.

[0002]

2. Description of the Related Art In recent years, with the advent of supercomputers, the need for scientific and technological calculation processing has increased, and the demand for larger scales and higher speeds is unavoidable. For example, Hitachi's supercomputer HITAC S-8
In the computer system 20, the computer system is provided with an extended storage device (built-in extended storage device) having a larger capacity than that of the main storage which operates at the same clock in synchronization with the main storage and the instruction processor.
For example, Proc. Of IEEE International Conf. On Comp
See uter Design 1984, pp.227-231.

The extended storage device functions as an auxiliary storage for the main storage which has been conventionally performed by the DISK.
It enables data transfer to and from the main memory much faster than The expanded memory has an address space independent of the main memory. This data transfer is performed in units of 4 KB in order to speed up a large amount of data transfer between the expanded memory and the main memory.
By dividing the data in the expansion storage device, reading the data into the main storage device, performing arithmetic processing, and writing the result to the expansion storage device again, a large-scale operation exceeding the capacity of the main storage device is achieved. It is possible to process data.

In addition to speeding up one instruction processor, parallel processing for simultaneously operating a plurality of instruction processors is becoming popular. 1 to realize this parallel processing
As one configuration, there is provided a system in which a plurality of subsystems each including a main storage device and one or more instruction processors sharing the main storage device are prepared, and the subsystems are connected by a shared expansion storage device. JP-A-63-305451, JP-A-63-316251, JP-A-62-204361 and JP-A-55-18720
Is disclosed in. Further, Japanese Patent Laid-Open No. 2-77867 discloses a system in which built-in expanded storage devices in respective subsystems are directly connected and handled as shared storage. in this case,
The two internal extended storage devices are distinguished by a uniquely attached internal storage device number ESID.

In the following, the internal expansion storage device and the shared expansion storage device will be compared. The data transfer destination of the built-in expansion storage device is only the main memory or instruction processor in each subsystem, but since the shared expansion storage device is connected to multiple subsystems, multiple sets of data transfer lines are required. The data width of the data transfer line with the system becomes narrower. Further, since the shared extended storage device is accessed by a plurality of subsystems, access competition from each subsystem occurs, and it is difficult to secure the data throughput for each subsystem. In order to suppress this access conflict as much as possible, in Japanese Patent Laid-Open No. 63-305451, the shared extended storage device is divided into the number of subsystems, and when data is written to the extended storage, copying is performed in the extended storage. Data can be read from the subsystem at the same time. In addition, the internal expansion storage device is in each subsystem and can operate at the same clock as the main storage device or instruction processor, while the latter shared expansion storage device ensures flexibility in system configuration. To do so, it operates on a separate clock independent of each subsystem. Therefore, an asynchronous control circuit is required between the shared extended storage device and each subsystem. JP-A-1-99141
Then, a high data transfer throughput is secured by providing a queue in this asynchronous control processing unit. In addition,
Although it is not described as a shared extended storage device, an example in which a shared memory is provided for a subsystem is disclosed in Japanese Patent Laid-Open No. 78361/1988.

[0006]

Therefore, in order to speed up large-scale scientific and technological calculation processing by a parallel processing system in which a plurality of instruction processors operate simultaneously, not only the shared expansion storage device but also the built-in expansion storage device Must be secured in each subsystem and large-capacity data must be distributed to two types of extended storage devices as needed. Further, in such a parallel processing system, a plurality of storage devices (main storage device, built-in expansion storage device, shared expansion storage device) will be used. The user needs to consider which storage device to store the data in consideration of the system configuration.
It is considered desirable to be able to handle two types of extended storage devices, which are secondary storage devices, without making a distinction.

[0007]

In order to solve the above problems, the present invention provides a subsystem comprising a main memory and at least one instruction processor connected to the main memory for executing instructions. A parallel computer system is prepared in which a plurality of them are prepared, they are connected by a shared extended storage device, and further, an internal extended storage device is connected as a secondary storage of a main storage device in each subsystem. In a compiler for such a parallel system, the same description is included in the source program for the declaration of allocating data in the internal expansion storage device or the shared expansion storage device, and the range of the subprogram that defines or refers to that data is included. To determine whether to secure the data in the built-in extended storage device or the shared extended storage device.

[0008]

In the above parallel computer, the data held in each built-in extended storage device can be accessed faster than the shared extended storage device, and since it is accessed only from that subsystem, other subsystems Since there is no access conflict from, it is possible to expect even faster access. Further, by holding the data accessed from the plurality of subsystems in the shared expansion storage device, it becomes possible to exchange data between the subsystems, and parallel processing using the plurality of subsystems becomes possible.

[0009]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a parallel computer system according to an embodiment of the present invention. In the figure, 1 and 5 are internal expanded storage devices # 1, # 2, 2 and 4 are main storage devices # 1, #.
2 and 3 are shared extended storage devices, 6 and 7 are system controllers # 1, # 2, 8 to 11 are instruction processors # 1, # 2, # 3, # 4, 12 and 13 are input / output processors, 14 and Reference numeral 16 is a unique DASD, and 15 is a shared DASD. Instruction processor # 1 8
And instruction processor # 29 is system controller #
It is a processor subsystem that forms a tightly coupled multiprocessor configuration in which the main storage device # 12, the built-in expansion storage device # 11, and the input / output processor # 112 are shared via the I / O processor 14. Similarly, the instruction processor # 3 10 and the instruction processor # 411 have a tightly coupled multiprocessor configuration in which the main storage device # 2 4, the internal expansion storage device # 2 5, and the input / output processor # 2 13 are shared via the system controller # 2 7. It is another processor subsystem that is forming. One more of these two processor subsystems
A loosely coupled multiprocessor system is configured via a shared extended storage device 3 which is a kind of extended storage device.

The two subsystems and the shared expansion memory operate with separate independent clocks. Therefore, it is possible to operate them separately.

In order to distinguish a plurality of extended storage devices,
A number is uniquely assigned to each extended storage device, and this extended storage device number ESID is added to a part of an instruction to access the extended storage device.

In this embodiment, two processor subsystems are used.
However, it is possible to connect more processor subsystems to the shared expansion storage device 3.

FIG. 9 shows an example of an instruction for executing data transfer between the main storage device and the extended storage device.

FIG. 9A shows an example of the instruction format of the data transfer instruction. In the figure, an instruction code (OP) indicates that this instruction is an instruction for executing data transfer between the main storage device and the extended storage device. Operands (R1) and (R2) indicate register numbers. Operands (R1) and (R
The contents of the register designated in 2) are shown. Register (R1)
A main memory address is prepared in advance. The register (R2) holds the number of transferred blocks during the execution of the instruction. Further, in the main storage area of the address indicated by the register ((R2) +1), the main storage address holding the extended storage control parameter information is prepared in advance.
The extended storage control parameter on the main storage holds a number ESID for distinguishing a plurality of extended storages, a block address on the extended storage, and a transfer block length.
Here, the address of each extended storage is specified on a 4 KB boundary, and 4 KB is used as a unit for access. ESID
Is statically assigned to each extended memory, and it is possible to determine whether the partner of data transfer with the main memory is the built-in extended memory or the shared extended memory by using this ESID.

Built-in expanded memory 1 represented by the instruction of FIG.
Data transfer between the main memory 2 and the shared memory 3 and the main memory 2
Differences in data transfer operation between the main memory 2 and the instruction processor 8 will be described with reference to FIGS.

10 to 12 show the detailed structure of the instruction processor (# 1) 8, the detailed structure of the system controller (# 1) 6 and the detailed structure of the shared expansion storage device 3 shown in FIG. 1, respectively. There is.

In FIG. 10, 801 is an instruction buffer, and 80
2 is an instruction register, 803 is an instruction decoder, 804 is an operand access circuit, 805 is a register group, 806 is a computing unit, 807 is a vector operand access circuit, 8
Reference numeral 08 denotes a vector register, and 809 denotes a vector arithmetic unit group.

In FIG. 11, reference numeral 601 denotes a built-in extended storage control,
602 is main memory control, 610 and 611 are AND circuits, 6
12 is a comparison circuit, 613 is a register for holding the ESID, 614 is a + m counter, 615 is an address generation circuit, 620, 623 and 624 are AND circuits, 612 and 6
22 is a NOT circuit, 625 and 626 are comparison circuits, 62
Reference numerals 7 and 628 are registers for holding ESID, 629 is a priority circuit, 630 is a + m counter, 631 is an address generation circuit, 632 is a + m ′ counter, 633 is an address generation circuit, and 634 and 635 are selectors.

In FIG. 12, 301 is a memory, 302 is a shared extended storage control, 310 is a priority circuit, 31
1, 312 are AND circuits, 313 and 314 are comparison circuits,
315 is a register holding the ESID, 316, 318
Is a + m 'counter, 317 and 319 are address generation circuits, and 320 and 321 are selectors.

The internal extended storage control 601 (FIG. 11) and the shared extended storage 302 (FIG. 12) have registers 613 and
315, and the extended storage number ESID is uniquely set in advance during system configuration. here,
It is assumed that ESID # 1 is set in the register 613 and ESID # 0 is set in the register 315 in advance.
The main memory control 602 (FIG. 11) includes registers 627 and 62.
8 is set, and the number ESID of the extension storage connected in advance is set when the system is configured. Here, the ESID # 0 is stored in the register 627 and the register 628 is stored.
Is set to ESID # 1.

Data is transferred between the built-in expanded memory 1 and the main memory 2 in continuous 4 KB units. This continuous 4KB unit data transfer is m bytes (1 to several tens)
The line L5 is used for the data transfer path. Similarly, data is transferred between the shared extended storage 3 and the main storage 2 in units of continuous 4 KB. This 4 in succession
Data transfer in KB units is divided into m'bytes (1 to several tens) and the line L6 is used as a data transfer path.
Since the shared extended memory 3 is accessed by a plurality of subsystems, the width of the data line with one subsystem cannot be wide. Therefore, in general m>
m ′, and the built-in storage can secure the throughput.

First, the instruction processor 8 will be described with reference to FIG.
The data access method from is shown. The scalar data accesses the main memory 2 via the operand access circuit 804. For vector data, the vector memory access circuit 807 is used to access the main memory 2. Scalar data is accessed in units of 8/4 bytes by load / store type instructions processed by the instruction processor. As for vector data, vector data consisting of 1 to several 100 elements is accessed by a vector load / vector store system instruction.

Next, the data transfer between the expanded memory and the main memory will be described. As an example, data transfer from the built-in expanded memory 1 to the main memory 2 is used. Here, the instruction processor 8, the internal expanded storage control 601, and the main storage control 602 will be described in this order.

The operation of the instruction processor 8 will be described with reference to FIG. The data transfer instruction shown in FIG. 9 is set in the instruction register 802 via the instruction buffer 801.
The instruction code portion is decoded by the instruction decoder 803.
The decrypted data transfer command is sent to the required main memory control 602, built-in extended storage control 601, and shared extended storage control 302 via line L1. Also, the instruction register 802
The register group 805 is accessed by designating two register numbers in the operand part of the data transfer instruction in the above.
The main memory address is designated in the register (R1), and the main memory control 602 is executed via the operand access circuit 804.
Sent to. The main storage address holding the extended storage control parameter is secured in the register ((R2) +1). Prior to the data transfer processing, this extended storage control parameter is fetched from the main storage and the extended storage device number ESI
D, extended storage block address, and transfer block length are divided and sent to the main storage control 602, built-in extended storage control 601, and shared extended storage control 302 using lines L2 to L4, respectively.

The operation of the internal extended storage control 601 of the data transfer source will be described with reference to FIG. Built-in extended memory control 6
01 indicates a register 61 when the system is configured.
ESID # 1 is set to 3. Instruction processor 8
Extended storage device number ESI which is the information sent from
The comparison circuit 612, the address generation circuit 615, and the + m counter 614 receive D, the extended storage block address, and the transfer block length. In the comparison circuit 612,
ESID of preset register 613
# 1 is compared with the ESID sent from the instruction processor 8. In this example, a match is confirmed and the result is ANDed
Send to circuit 611. The AND circuit 611 checks whether the instruction from the instruction processor 8 is read or written. In the address generation circuit 615, the extended storage block address sent from the instruction processor 8 is used as an initial value,
Addresses in the built-in expanded memory are sequentially generated. This address is generated every m bytes, and the transfer data is sent in units of m Byte to the main memory control 602 via the line L5. +
The m counter 614 sequentially counts the transfer data amount,
When the data transfer of the transfer block length sent from the instruction processor 8 is completed, the address generation circuit 615 is instructed to end the address generation. This built-in extended memory 1
Does not need access control because it is not accessed by other subsystems.

The operation of the main memory control 602 of the data transfer destination will be described. The main memory control 602 includes
The ESID of the extended storage device to be connected is held in advance. In this example, the shared extended storage number ESID0 is set in the register 627, and the built-in extended storage number ESID1 is set in the register 628. The extended storage device number ESID, the extended storage block address, and the transfer block length, which are the information sent from the instruction processor 8, are accepted by the comparison circuits 625 to 626, the address generation circuits 631 to 633, the + m counter 630, and the + m ′ counter 632. Be done. Comparing circuits 625 and 626 include preset registers 627 through 628.
And the ESID sent from the instruction processor 8 are compared. In this example, the comparison circuit 626 confirms the match and sends the result to the AND circuit 624. AND circuit 6
At 24, it is checked whether the instruction from the instruction processor 8 is read or write. The result is sent to the priority circuit 629. In the priority circuit 629,
Controls contention for access requests to various main memories 1. The address generation circuit 631 uses the main memory address sent from the instruction processor 8 as an initial value, and sequentially generates addresses on the main memory. This address is generated every m bytes, and the transfer data is sent in m Byte units from the built-in extended storage control 601 via the line L5. + M
The counter 630 sequentially counts the transfer data amount, and when the data transfer of the transfer block length sent from the instruction processor 8 is completed, instructs the address generation circuit 631 to end the address generation. Similar processing is performed by the address generation circuit 633 and the + m ′ counter 632. The difference is that the address generation and count-up processing in mByte units are performed in m'Byte units. The transfer data width between the main memory control 602 and the shared extended memory control 302 is also m'byte.

The output of the AND circuit 620 indicates that the ESID designated by the instruction is not connected to the main memory 8. The result is returned to the instruction processor 8 and the transfer instruction ends.

This completes the data transfer process from the internal expansion storage 1 to the main storage 2.

Finally, the operation of the shared extended storage control 302 will be described with reference to FIG. 12 for comparison with the internal extended storage control 610. The shared extended storage control 302 has access requests from a plurality of subsystems. Here, the instruction processor 8
A process for an access request from the user will be described. The same applies to access processing from other subsystems.

In the shared extended storage control 302, ESID # 0 is set in the register 315 in advance during system configuration. The extended storage device number ESID, the extended storage block address, and the transfer block length, which are the information sent from the instruction processor 8, are received by the comparison circuit 313, the address generation circuit 317, and the + m ′ counter 316. The comparison circuit 313 compares the ESID # 0 of the register 315 set in advance with the ESID sent from the instruction processor 8. AND the result
Send to circuit 311. The AND circuit 311 checks whether the instruction from the instruction processor 8 is read or written. The result is sent to the priority circuit 310,
Controls contention with access requests from multiple subsystems. In the address generation circuit 317, the instruction processor 8
The expanded storage block address sent from the device is used as an initial value to sequentially generate addresses on the internal expanded storage. This address is generated every m'byte, and the transfer data is m '
Byte units are sent to the main memory control 602 via the line L6. The + m 'counter 316 sequentially counts the transfer data amount, and when the transfer of the transfer block length data sent from the instruction processor 8 is completed, the address generation circuit 3
Instructing 17 to end the address generation. The address generation circuit 319 and the + m ′ counter 318 perform the same processing in response to access requests from other subsystems.

From the internal expansion memory 1 to the main memory 2 shown above
It is understood that the built-in extended storage 1 can be accessed faster than the shared extended storage 3 by the data transfer processing to the shared extended storage 3 and the access processing method of the shared extended storage 3. Therefore, a system having both the built-in expanded memory 1 and the shared expanded memory 3 is realized, and data accessed only within the subsystem is stored in the built-in expanded memory 1 and data shared between subsystems is stored in the shared expanded memory 3. As described above, by using the extended storage properly, high-speed large-scale calculation can be realized.

In order to execute a large-scale scientific and technological calculation process on this parallel computer system, data or programs (object programs) are distributed and arranged in each storage device. In the processor subsystem including the instruction processor # 18, the object program and data to be processed by this processor subsystem are stored in the main storage device # 1 2 in the internal expansion storage device 1 # 1.
Data that cannot be stored in # 1 and is accessed only within the processor subsystem is held. The same applies to the other processor subsystem. The shared extended storage device 3 stores data accessed by both processor subsystems and is used when data is transferred between the processor subsystems.

Execution of large-scale scientific and technological calculation processing on this parallel computer system will be described using an example.

As an example, the simultaneous linear equations obtained by differentiating the three-dimensional heat diffusion equation (Poisson's equation) are R / B SOR (Red / Black Successive O) which is one of the parallel solution methods.
(Ver-Relaxation) method. This R / B
The SOR method is described in "Numerical Simulation in Engineering" by Murata, Oguni, Miyoshi, and Koyanagi. FIG. 5 shows a three-dimensional lattice division area obtained by the difference. Here, the region is divided into two in the X-axis direction, and the right half is executed by one processor subsystem and the left half is executed by another processor subsystem. The total number of grid points is X-axis, Y-axis, Z
If the axial directions are 2000, 1000, and 1000, each processor subsystem requires a data area of 8 GB, and data cannot be held only by the main storage device. Therefore, the data is secured in the extended storage device.
Each R / B SOR method requires information on adjacent grid points in order to calculate each grid point. Therefore, it is necessary to hold the data of the yz planes of UB1 and UB2 in the drawing, which are boundaries at the time of division, in the shared extended storage device. This data area is represented as UB1 and UB2. This is the data area to be passed between the processor subsystems. Since the other areas are accessed only within the subsystems, they are held in the respective built-in extended storage devices. This data area is UA1 and UA2 respectively
And

FIG. 6 shows an outline of the parallel operation procedure. Here, a parent task is executed by one processor subsystem, and a child task is executed by the other processor subsystem. First, the parent task starts execution, and this parent task activates the child task (70). Hereinafter, the parent task and the child task perform the same processing. First, shared DASD 15 (Figure 1)
The data is fetched from the device into the built-in extended storage device (built-in ES) (71). Next, the instruction processor in the processor subsystem is used to perform arithmetic processing of the area in charge. At this time, if there are a plurality of instruction processors in the processor subsystem, main memory sharing type parallel processing is performed (72 to 7).
3). Each instruction processor performs the following processing. First, built-in E
Data is read from S into the main memory (MS) (74).
At this time, one processing unit (the number of lattice points to be handled) is determined by the program according to the MS capacity and the number of instruction processors in the processor subsystem. Next, arithmetic processing is performed on the area in charge (75). Finally from MS to built-in ES
The calculation result data is stored in (76). When the calculation of the area in charge of the subsystem is completed, the data is transferred between the processor subsystems via the shared extended storage device (shared ES) (77 to 78). Here, data UB1 and UB2 (FIG. 5), which are boundary regions, and information for convergence determination (not shown, information for enabling convergence determination processing for each processor subsystem, for example, for each processor subsystem) The partial product sum of the residual norm) is passed. At this time, in order to guarantee the order relation of data access on the shared ES, post processing is performed on the shared ES after writing data from the MS to the shared ES, and the shared ES to M
It is necessary to perform a Wait process on the shared ES before reading data to S. Further, a convergence determination process is performed (80),
The processing from (72) to (80) is repeated until the convergence determination condition is satisfied. When the convergence determination condition is satisfied, the result data on the built-in ES is stored in DASD (81), the child task ends the processing (83), and the parent task confirms the end of the child task and then ends the entire processing. (82).

Next, a program description method for arranging data on the extended storage device will be described.

FIG. 7 shows the system configuration viewed from the source program. In the figure, 91 and 92 are main memories, 90 is a shared memory, and 93 to 96 are instruction processors. In this case, an internal extended memory device (internal E) on the source program is used.
S) or the shared extended storage device (shared ES) has the same data area declaration and is set as the shared storage 90. In order to declare data on this shared memory, here, the ECOMMON declaration (extended COMMON declaration), which is an extension of the COMMON declaration of the Fortran grammar, is used.
Declaration) is defined.

FIG. 8 shows an example of the ECOMMON declaration in the source program for each of the parent task and the child task. Here, UA1, UB1, UA2, UB2 shown in FIG.
, Is declared in the ECOMMON statement in order to secure each area in the shared memory 90. Also, in the figure, 105 or 115
The array WK declared by the COMMON statement is an array area secured in the main memory and is used as a work area when the data in the shared memory 90 is fetched in the main memory.

At this time, a method of determining whether the data declared by ECOMMON is to be stored in the built-in extended storage device (built-in ES) or the shared extended storage device (shared ES) with the compiler will be described with reference to FIGS. 2 to 4. explain.

FIG. 2 is a functional block diagram showing the configuration of the compiler according to the first embodiment of the present invention. In the figure, 30 is a compiler, 31 is an ECOMMON name extraction unit, 32 is an ECOMMON name allocation destination ES determination unit, 33 is an object program generation unit, 34 is a source program group for parent task or child task, and 35 is ECOMMON name table, 36 is a source program after the allocation ES is determined, and 37 is an object program for each task. The compiler 30 inputs the task source program 34 for each task, and finally outputs the task object program 37.

In the present invention, the new function ECOMMON name extraction unit 31 and the ECOMMON name allocation destination ES determination unit 32 are part of the compiler, but this function may be a preprocessor that is executed before the compiler independent of the compiler. ..

First, the ECOMMON name extraction unit 31 inputs each task source program 34 and generates an ECOMMON name table 35. ECOMMON name table 35
It is a table showing which task accesses the data area secured on the shared storage for each ECOMMON name. Next, the ECOMMON name allocation destination ES determination unit 32 inputs the source program 34 for each task and the ECOMMON name table 35 and outputs the source program 36 after the allocation destination ES is determined. Finally, the object program generation unit 33 inputs the source program 36 after the allocation destination ES is determined and inputs the object program 37 for each task.
Is output. Since the object program generation 33 is known as a compilation technique, it is omitted here.

Details of the new function will be described.

The processing of the ECOMMON name extraction unit 31 will be described with reference to FIG.

First, the source program 34 for each task
Read one source program from (Fig. 2) (42),
Below, the sentence S in the source program is analyzed, and the sentence S
It is checked whether it is an ECOMMON declaration statement (45), and if so, the ECOMMON name is registered in the table 35 (FIG. 2) (4
8). If not, check whether the statement S is an executable statement that accesses the variable declared by ECOMMON (46), and if
If so, mark the access task name field of the corresponding ECOMMON name registered in the table (4
7). As a result, the data in the target ECOMMON name is registered to be accessed from the target task. The above processing is continued until there is no source program to read.

Next, the processing of the ECOMMON name assignment destination ES determination section 32 will be described with reference to FIG.

First, the source program 34 for each task
Read one source program from (Fig. 2) (51),
Extract the ECOMMON declaration statement (54), check the row of the corresponding ECOMMON name from the ECOMMON name table 35 (Fig. 2), and if the ECOMMON name is accessed by multiple tasks, make the ECOMMON a shared ES. Allocation (5
7) If the ECOMMON name is accessed by only one task, it is assigned to the built-in ES of the subsystem that executes the accessed task (58). The above processing is continued until there is no source program to read.

As described above, by the processing of the ECOMMON name extraction unit 31 (FIG. 3) and the ECOMMON name allocation destination ES determination unit 32 (FIG. 4), it is determined whether the ECOMMON declared data is allocated to the built-in ES or the shared ES. be able to.

[0050]

According to the present invention, data defined or referenced only in the subsystem is secured in the internal expansion storage device in the subsystem, so that large-scale data can be handled at a relatively high speed. Further, by securing the data shared between the subsystems in the shared expansion storage device, the data can be transferred between the subsystems. Further, by making it possible to make the user's program description the same with respect to the arrangement of data in the built-in extended storage device or the shared extended storage device, the user can make the built-in extended storage device and the shared extended storage device Since it is not necessary to distinguish the devices, the program description becomes simple.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a parallel computer system.

FIG. 2 is a flowchart of the compiler.

FIG. 3 is a flowchart of an ECOMMON name extraction processing unit.

FIG. 4 is a flowchart of an ECOMMON name sum allocation destination ES determination processing unit.

FIG. 5 is a diagram showing an example of a three-dimensional lattice division area.

FIG. 6 is a flowchart example of a parallel operation processing procedure.

FIG. 7 is a system configuration diagram assumed by the program.

FIG. 8 is a diagram showing an example of an ECOMMON declaration part in a program.

FIG. 9 is a diagram showing a data transfer instruction format between main memory and extended memory.

FIG. 10 is a detailed configuration diagram of an instruction processor.

FIG. 11 is a detailed configuration diagram of a system controller unit.

FIG. 12 is a detailed configuration diagram of a shared extended storage device.

[Explanation of symbols]

1, 5 ... Built-in extended storage device, 2, 4 ... Main storage device, 3 ...
Shared extended storage device, 6, 7 ... System controller, 8
... 11 ... Instruction processor, 12, 13 ... Input / output processor,
14, 16 ... DASD, 15 ... Shared DASD, 30 ... Compiler configuration, 31 ... ECOMMON name extraction unit, 32 ... EC
OMMON name assignment destination ES determination unit, 33 ... Object program generation unit, 34 ... Source program for each task, 35 ... ECOMMON name table, 36 ... Source program for each task after determination of ECOMMON name assignment destination ES,
37 ... Object program for each task, 302 ... Shared extended storage control, 601 ... Built-in extended storage control, 602 ...
Main memory control.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuka Kitai 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tadayuki Sakakibara 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory

Claims (3)

[Claims] 1. A plurality of subsystems each comprising a main memory device and at least one instruction executing means connected to the main memory device for executing an instruction; and a shared shared among the subsystems, comprising a random access memory. A parallel processing system having an expansion storage device and a built-in expansion storage device which is composed of a random access memory and is connected as a secondary storage of the main storage device in each subsystem. 2. In the subsystem, a subprogram obtained by dividing one program for each subsystem is stored in the main storage device, and data required by the subprogram is stored in the built-in expansion storage device, The instruction executing means reads the subprogram from the main storage device, decodes it, and reads data from the built-in expansion storage device according to the decoded contents, or writes it in the shared expansion storage device by another subsystem. A data read operation or an arithmetic process, or write the result data to the internal expansion storage device, or write the result data required by another subsystem to the shared expansion storage device. 1. A program execution method in the parallel processing system of 1. 3. A method of compiling a source program to be executed by the parallel processing system, wherein a declaration for allocating data in the internal expansion storage device or shared expansion storage device is described in the same format. Claims comprising the step of analyzing a range that defines or refers to the data declared in, and using the analysis result to determine whether to allocate the data to the internal expansion storage device or the shared expansion storage device. A compiling method for the parallel processing system according to item 2.