JPH05210539A - Abnormality monitor timer controller - Google Patents

Abstract

PURPOSE:To improve the reliability by providing plural addresses to be accessed, to confirm the soundness of a program, and to easily confirm which address is not accessed owing to abnormal operation. CONSTITUTION:The abnormality monitor timer controller consists of a clear signal generating circuit 11, a power-ON reset circuit 12, an abnormality monitor timer circuit 13, a CPU 14, and an address decoder unit circuit 15, which consists of address decoder circuits 15-1, 15-2...15-n corresponding to plural access detecting means. Then access to plural addresses (AD1, AD2...ADn) which is repeated at a specific period is detected by an address decoder unit circuit 15 and the clear signal generating circuit 11 detects abnormality according to the time-up time of the abnormality monitor timer circuit and plural access detection signals A1, A2...An outputted by the address decoder unit circuit 15 and outputs alarm signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality monitoring timer controller, and more particularly to an abnormality monitoring timer controller such as a watchdog timer.

[0002]

2. Description of the Related Art FIG. 4 is a functional block diagram of a conventional abnormality monitoring timer control device disclosed in, for example, Japanese Patent Application Laid-Open No. 1-237852, in which 51 is an abnormality monitoring timer.
52 is a power-on reset means, 53 is a program executing means, 54 is an access detecting means, and 55 is a clear signal generating means.

FIG. 5 is an electric circuit diagram of a conventional abnormality monitoring timer control device. In the figure, 56 is a watchdog timer, 57 is a CPU, 58 is an address decoder, and 59.
Is a power-on reset circuit, and 60 is a reset signal output circuit.

FIG. 6 is a timing chart of each signal.

Next, the operation will be described.

When the power is turned on, the power-on reset means 52 outputs the power-on reset signal P until the initial processing of the program is completed, and the clear signal generation means 55 outputs the clear signal in response to the power-on reset signal P. Send C to the abnormality monitoring timer 51. Therefore, the warning signal W is not output for a predetermined time after the power is turned on.

During normal operation, the program executing means 53
Will sequentially execute the program. However, due to the operation of the program executing means, there is a specific address that is always accessed within a certain period of time in this program.

The access detection means 54 detects the access to this specific address and sends the access detection signal A to the clear signal generation means 55. Therefore, the access detection signal A is periodically generated within a certain period, the clear signal C is regularly sent to the abnormality monitoring timer 51, and the abnormality monitoring timer 51 is periodically reset, so that an alarm is issued. No signal W is emitted.

On the other hand, when the program execution means 53 is not operating normally, the access detection signal A is not output from the access detection means 54. Therefore, the abnormality monitoring timer 51 is not cleared and the time is up, and the predetermined time is exceeded. The alarm signal W will be emitted after a lapse of time.

[0010]

Since the conventional abnormality monitoring timer control device is constructed as described above, when a program in loops in a processing routine including a specific address, a serious failure occurs without an alarm signal being generated. There is a possibility that it will develop, and when the program scale becomes large, it cannot be said that the entire program is normally executed only by accessing a specific address, and it is insufficient as a reset condition for the abnormality monitoring timer. There was a point.

The present invention has been made to solve the above-mentioned problems, and improves the reliability by making a plurality of addresses to be accessed, and makes it possible to confirm the soundness of the program, and It is an object of the present invention to provide an abnormality monitoring timer control device capable of easily confirming which of a plurality of addresses has not been accessed when an alarm signal is issued for an operation.

[0012]

An abnormality monitoring timer control apparatus according to the invention of claim 1 detects an access of a specific address repeated at a predetermined cycle and outputs an access detection signal, and an abnormality monitoring. In the abnormality monitoring timer control device comprising an alarm signal output means for detecting an abnormality and outputting an alarm signal based on the time-up time of the timer circuit and the repetition cycle of the access detection signal, the access detection means has a predetermined cycle. Is a composite access detection means for detecting access to each of a plurality of addresses repeated and outputting an access detection signal, and the alarm signal output means is a time-out time of the abnormality monitoring timer circuit and a plurality of accesses output by the composite access detection means. Based on the detection signal, it detects the abnormality and outputs a warning signal Than it is.

According to another aspect of the present invention, there is provided an abnormality monitoring timer control device, wherein access detecting means detects an access to a specific address repeated at a predetermined cycle and outputs an access detection signal, and the time-up time of the abnormality monitoring timer circuit. And an alarm signal output means for detecting an abnormality and outputting an alarm signal based on the repetition cycle of the access detection signal, wherein the access detection means is a plurality of addresses repeated at a predetermined cycle. Of the access detection signals and outputs an access detection signal. The alarm signal output means is based on the time-up time of the abnormality monitoring timer circuit and the plurality of access detection signals output by the composite access detection means. It is a composite access warning signal output means for detecting an abnormality and outputting a warning signal. Whether access address is detected and has a respective identification means for identifying.

[0014]

In the abnormality monitoring timer control device according to the present invention, the composite access detecting means detects the access to each of a plurality of addresses repeated at a predetermined cycle, and detects the time-up time of the abnormality monitoring timer circuit and the composite access detection. Based on the plurality of access detection signals output from the means, the composite access alarm signal output means detects an abnormality and outputs an alarm signal.

According to another aspect of the present invention, the abnormality monitoring timer control device detects the access of a plurality of addresses which is repeated at a predetermined cycle by the composite access detecting means, and detects the time-up time of the abnormality monitoring timer circuit and the composite access detection. An abnormality is detected by the composite access alarm signal output means based on the plurality of access detection signals output by the means,
An alarm signal is output, and it is further discriminated by the discriminating means whether or not access to each of the plurality of addresses has been detected.

[0016]

【Example】

Example 1. Embodiment 1 of the abnormality monitoring timer control device of the present invention will be described below with reference to the drawings.

FIG. 1 is a functional block diagram of the abnormality monitoring timer control device of this embodiment.
-2, ... 1-n are access detecting means for a plurality of addresses.

Reference numeral 2 is a clear signal generating means, 3 is a power-on reset means, 4 is an abnormality monitoring timer means, and 5 is a program executing means.

FIG. 2 is a block diagram showing the configuration of this abnormality monitoring timer control device, and 11 is a clear signal generating circuit, which corresponds to the clear signal generating means 2. The clear signal generation circuit 11 is composed of an access detection signal latch circuit 11a, an RS flip-flop 11b, and a 2-input AND circuit 11c.

A power-on reset circuit 12 corresponds to the power-on reset means 3. An abnormality monitoring timer circuit 13 corresponds to the abnormality monitoring timer means 4. Reference numeral 14 is a CPU, and the program executing means 5
Corresponding to.

Reference numeral 15 is an address decoder unit circuit, which is the access detecting means 1-1, 1-2, ... 1-
address decoder circuits 15-1, 1 corresponding to n
5-2, ..., 15-n. A specific address (AD1, AD2, ... ADn) of the main task of the main program that is repeatedly accessed in a predetermined cycle is designated in each of the plurality of address decoder circuits, and the address output from the CPU 14 is specified. The specific address signal is identified from the signals and the access detection signals A1, A2, ... An are output.

Next, the clear signal generating circuit 1 shown in FIG.
The circuit configuration of No. 1 is shown in detail in FIG.

In this figure, the RS flip-flop 1
1-1, RS flip-flop 11-2, ... RS flip-flop 11-n, 3-input AND circuit 11x, monostable multivibrator circuit 11y, inverter circuit 1
The access detection signal latch circuit 11a is configured by 1z.

The output terminal q of the RS flip-flop 11-1 forming the access detection signal latch circuit 11a is
The light emitting diode LED1 is connected and lights up when the access detection signal A1 is fetched by the RS flip-flop 11-1 to display that the access detection signal A1 is fetched.

Further, the light emitting diode LED2 is connected to the output terminal q of the RS flip-flop 11-2, and when the access detection signal A2 is taken into the RS flip-flop 11-2, it is turned on and the access detection signal A2 is output. Display that it has been captured.

Similarly, the RS flip-flop 11-
A light emitting diode LEDn is connected to the output terminal q of n, and is turned on when the access detection signal An is captured by the RS flip-flop 11-n, which indicates that the access detection signal An is captured.

In the configuration described above, the clear signal generation circuit 11 and the abnormality monitoring timer circuit 13 correspond to the composite access warning signal output means, and the address decoder unit circuit 15 and the address decoder circuits 15-1 and 15-.
2, ... 15-n correspond to the composite access detection means,
Further, light emitting diodes LED1, LED2, ... LE
Dn corresponds to the identification means.

Next, the operation will be described with reference to FIGS. 2 and 3.

First, the address signal (AD
1, AD2, ... ADn) are output, the address decoder circuits 15-1, 15-2 ,.
This address signal is identified, and the access detection signals A1, A2, ... An of the'L 'level are respectively detected by the RS flip-flops 11-1, 1 of the access detection signal latch circuit 11a.
Output to the set input terminals S of 1-2, ... 11-n.

Here, the RS flip-flops 11-1, 11-2, ... 11-n in FIG. 3 are reset by the power-on reset signal P when the power is turned on, and the RS flip-flops 11-1, 11 are shown. -2, ...
The output terminal Q of 11-n is at the'L 'level. On the other hand, since the output terminal q is at the'H 'level, all the light emitting diodes LED1, LED2, ..., LEDn are turned off.

Access detection signals A1, A2, ... An
Are taken into the RS flip-flops 11-1, 11-2, ... 11-n of the access detection signal latch circuit 11a, respectively, the RS flip-flops 11-1, 11-
2, ... 11-n output terminals q change to'L 'level, and light emitting diodes LED1, LED2 ,.
Dn will light up respectively. When the light emitting diode is off, the access detection signal is not output from the corresponding address decoder circuit and is not captured by the corresponding RS flip-flop.

Upon receiving the access detection signal, the RS flip-flop changes the signal output from the output terminal Q to the "H" level. RS flip-flops 11-1, 1
When the signals A1F, A2F, ... AnF output from the output terminals Q of 1-2, ... 11-n are all at the'H 'level, the output of the 3-input AND circuit 11x is from the'L' level. It changes to the H ′ level and is input to the monostable multivibrator circuit 11y, and a signal having a predetermined pulse width is output from the monostable multivibrator circuit 11y.

This signal is inverted by the inverter circuit 11z and given to the second reset input terminal R2 of the RS flip-flops 11-1, 11-2, ... 11-n as the composite access detection signal A.

As a result, the RS flip-flop 11-
, 11-2, ..., 11-n are reset, and signals A1F, A2F ,.
Changes from'H 'level to'L' level again and returns to the initial state.

The access detection signals A1, A2, ...
The An once changes from the “H” level to the “L” level and then returns to the “H” level again, but the output terminals Q of the RS flip-flops 11-1, 11-2, ... 11-n. Signals output from A1F, A2F, ... AnF
Indicates that the composite access detection signal A is the second reset input terminal R
Since the state up to that point is retained until it is given to step 2, it is possible to visually confirm whether the light emitting diode is lit during this period, and thereby identify which address has not been accessed. I can.

Therefore, when the CPU 14 abnormally operates and is stopped by the alarm signal W, by checking the lighting state of the light emitting diodes LED1, LED2, ... It can be easily confirmed. On the other hand, since the RS flip-flop 11b is reset when the power is turned on, the output terminal Q is at the “L” level, the clear signal C is maintained at the “L” level, and the alarm signal W is output when the power is turned on. It will not be output.

All access detection signals A1 and A
2, ... An is RS flip-flop 11-1, 11
When the composite access detection signal A is output to the RS flip-flop 1
The output terminal Q of 1b changes to the “H” level, and the composite access detection signal A is given to one input terminal of the 2-input AND circuit 11c.
The'L 'level clear signal is output to the output terminal of c. After that, when the composite access detection signal A disappears and the output of the inverter circuit 11z returns to the “H” level, 2
Since the input terminals of the input AND circuit 11c are both at the "H" level, the output terminal of the 2-input AND circuit 11c is at the "H" level.
Change to a level.

After that, each access detection signal A1, A2,
Each time all of An is output, an'L 'level clear signal is output, and the abnormality monitoring timer circuit 13 is cleared each time.

The address decoder circuits 15-1, 1
By configuring the address specified by 5-2, ..., 15-n to be changed by a switch, etc., it becomes possible to arbitrarily change and specify the address after the completion of the program. It is possible to reduce the restrictions of.

Further, in the above embodiment, the light emitting diodes are connected to the RS flip-flops 11-1, 11-2, ... 11-n so that it can be discriminated whether or not the access detection signal is fetched. However, the check terminal may be used, and in this case, a cheaper abnormality monitoring timer control device can be provided.

[0041]

As described above, according to the first aspect of the present invention, the composite access detection means detects the access to each of a plurality of addresses which is repeated at a predetermined cycle, and detects the time-up time of the abnormality monitoring timer circuit. Since the abnormality is detected based on the plurality of access detection signals output by the composite access detection means and the alarm signal is output, the access of one address is detected and the alarm signal is output based on the detected access. An abnormality monitoring timer control device with improved reliability can be obtained.

According to the second aspect of the present invention, the composite access detection means detects each access of a plurality of addresses repeated at a predetermined cycle, and outputs the time-up time of the abnormality monitoring timer circuit and the composite access detection means. An abnormality is detected based on a plurality of access detection signals, an alarm signal is output, and further, since it is configured to be able to identify which address access was not detected by the identification means, reliability is improved and It is possible to easily confirm which address access was not detected, and it is possible to easily infer a problem in the program and a problem in the system.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an abnormality monitoring timer control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an abnormality monitoring timer control device according to the first embodiment of the present invention.

FIG. 3 is an electric circuit diagram showing a circuit configuration of a clear signal generation circuit.

FIG. 4 is a principle diagram of a conventional abnormality monitoring timer control device.

FIG. 5 is a block diagram of a conventional abnormality monitoring timer control device.

FIG. 6 is a timing chart for explaining the operation of the conventional abnormality monitoring timer control device.

[Explanation of symbols]

1-1, 1-2, ... 1-n access detection means 11 clear signal generation circuit (composite access alarm signal output means) 13 abnormality monitoring timer circuit (composite access warning signal output means) 15 address decoder unit circuit (composite Access detection means 15-1, 15-2, ... 15-n Address decoder circuit (composite access detection means) LED1, LED2, ... LEDn Light emitting diode (identification means)

Claims (2)

[Claims] 1. An access detection means for detecting an access to a specific address repeated at a predetermined cycle and outputting an access detection signal, and an abnormality based on a time-up time of an abnormality monitoring timer circuit and a repetition cycle of the access detection signal. In the abnormality monitoring timer control device having an alarm signal output means for detecting an alarm signal and outputting an alarm signal, the access detection means detects a plurality of accesses to a plurality of addresses repeated in a predetermined cycle and outputs an access detection signal. The alarm signal output means is a detecting means, and the composite access alarm detects an abnormality and outputs an alarm signal based on the time-up time of the abnormality monitoring timer circuit and a plurality of access detection signals output by the composite access detecting means. An abnormality monitoring timer control device characterized by being a signal output means. 2. An abnormality is detected based on access detection means for detecting an access to a specific address repeated at a predetermined cycle and outputting an access detection signal, and a time-up time of an abnormality monitoring timer circuit and a repetition cycle of the access detection signal. In the abnormality monitoring timer control device having an alarm signal output means for detecting an error and outputting an alarm signal, the access detecting means detects a plurality of accesses of a plurality of addresses repeated in a predetermined cycle and outputs an access detection signal. The alarm signal output means is a detecting means, and the composite access alarm detects an abnormality and outputs an alarm signal based on the time-up time of the abnormality monitoring timer circuit and a plurality of access detection signals output by the composite access detecting means. It is a signal output means, and further confirms whether access to the plurality of addresses has been detected. An abnormality monitoring timer control device having identification means for identifying each.