JPH05209930A - Semiconductor test device - Google Patents

Abstract

PURPOSE:To provide a semiconductor test device which may carry out a test with a high degree of reliability. CONSTITUTION:A voltage monitor for monitoring an operation voltage applied to a semiconductor device to be tested is provided so as to carry out control such that an input signal produced from a signal generating part is delivered to the semiconductor device to be tested only when the operation voltage applied to the semiconductor device to be tested from a power voltage supply part is higher than a predetermined voltage which is necessary for normal operation. When the operation voltage applied to the semiconductor device to be tested becomes abnormally low, the voltage monitor part forcively cuts off the delivery of the input signal, thereby it is possible to prevent occurrence of abnormal operation such as latch-up or the like of the semiconductor device to be tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test device, and more particularly to a technique effectively used for a burn-in test (high temperature lining test) device for a CMOS (complementary MOS) integrated circuit device.

[0002]

2. Description of the Related Art In a semiconductor device, a burn-in test (or aging) is performed as an effective means for extracting an initial failure mode. Regarding the burn-in test, there is, for example, page 727 of "Microcomputer Handbook" published by Ohmsha, Ltd. on December 25, 1960.

[0003]

In a conventional burn-in test apparatus, a power supply voltage supply unit for supplying power to a semiconductor device under test and a signal generator for supplying an input signal for operating an internal circuit of the semiconductor device. Composed of parts. The power supply voltage supply section is given a maximum voltage in consideration of the breakdown voltage of the semiconductor device under test. On the other hand, the signal supply unit mainly outputs the signal using the TTL circuit. Therefore, the device is provided with a sequence control function, and after the power supply voltage is supplied to the semiconductor device under test, the operation voltage is supplied to the signal generating portion with a certain time difference to start the operation.

In this configuration, the load seen from the power supply voltage supply section changes greatly depending on the number of semiconductor devices under test, the power supply rises slowly, or the power supply waveform is distorted due to a momentary interruption in the device. Therefore, the power supply voltage may be lower than the input signal from the signal generator. In the semiconductor device under test, when the power supply voltage becomes lower than the input signal, undesired latch-up due to a parasitic thyristor or the like occurs and the semiconductor device under test is destroyed. In particular, a CMOS integrated circuit necessarily has a parasitic thyristor because of its structure, and the latch-up is likely to occur due to the miniaturization of elements in recent years. Therefore, the operating voltage and the input signal are strictly controlled. Is what you need.

An object of the present invention is to provide a semiconductor test apparatus which enables a test with high reliability.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a voltage monitor unit for monitoring the operating voltage applied to the semiconductor device under test is provided, and a signal is generated only when the operating voltage applied from the power supply voltage supply unit to the semiconductor device under test is equal to or higher than a predetermined voltage required for normal operation. The input signal generated by the unit is controlled to be supplied to the semiconductor device under test.

[0007]

According to the above means, when the operating voltage of the semiconductor device under test becomes abnormally low by the voltage monitor, the supply of the input signal is forcibly stopped to cause an abnormal operation such as latch-up in the semiconductor device under test. It is possible to prevent the occurrence of.

[0008]

1 is a block diagram of an embodiment of a burn-in test device (or an aging device) according to the present invention. The power supply voltage supply unit includes a plurality of power supply voltage circuits VG1 to VGn. These power supply voltage circuits V
G1 to VGn are operating voltages of the semiconductor device under test (usually,
In the burn-in test, the voltage value can be set according to the maximum rated voltage. Therefore, the power supply voltage circuits VG1 to VGn composed of these plural power supply voltage circuits VG1 to VGn form the same output voltage when a large number of devices under test of the same type are simultaneously subjected to the burn-in test. To be done. When a plurality of types of semiconductor devices having different operating voltages are simultaneously subjected to the burn-in test, the output voltages of the respective power supply voltage circuits VG1 to VGn are set according to the operating voltage of the semiconductor device under test.

The product mounting section is provided with the above-mentioned power supply voltage circuits VG1.
It is composed of a high temperature furnace in which product mounting boards 1 to n corresponding to VGn are housed. The product mounting boards 1 to n do not mean that each of them is physically one mounting board, but the number of semiconductor devices under test determined in advance according to the current supply capability of the power supply voltage circuits VG1 to VGn. It is composed of one or a plurality of mounting boards corresponding to.
That is, the semiconductor device under test has different current consumption depending on its type. Therefore, when performing a burn-in test on a semiconductor device under test with low current consumption, a relatively large number of semiconductor devices under test are mounted on the product mounting board, and when performing a burn-in test on a semiconductor device under test with high current consumption. A relatively small number of semiconductor devices under test are mounted on the product mounting board.

The signal generating section is composed of signal generating circuits SG1 to SGn corresponding to the product mounting boards 1 to n. This signal generator is operated by a unique power supply voltage. Although not particularly limited, the input signal to the semiconductor device under test mounted on the product mounting board is TT
It is made a constant signal such as L level. This is different from the case where the operating voltage of the semiconductor device under test is set near its maximum operating voltage as described above.

As described above, when the power supply voltage supplied to the semiconductor device under test and the power supply for forming the input signal are different, the semiconductor device under test mounted on the product mounting board 1 viewed from the power supply voltage circuit VG1 and the like. There is a risk that the power supply voltage may drop significantly relative to the input signal level due to a large change in the power supply startup, etc. due to the load or load depending on the number and type of products, or a voltage drop or fluctuation due to an instantaneous interruption in the burn-in device. ..
When such a phenomenon occurs, in the internal circuit of the semiconductor device under test, there is a problem that latch-up occurs due to the parasitic thyristor and element breakdown occurs.

In this embodiment, the voltage monitor circuits VM1 to VMn are provided in a one-to-one correspondence with the product mounting boards 1 to n of the product mounting portion in order to prevent the occurrence of the above-mentioned latch-up. It is provided. Product mounting board 1
If there is a margin, the voltage monitor circuits VM1 to VMn are provided on the corresponding product mounting boards 1 to n. As a result, the voltage monitor circuits VM1 to VMn can monitor the operating voltage of each mounting board, so that the connection path between the product mounting board and the power supply voltage supply unit can be used in addition to the voltage drop and the instantaneous interruption in the voltage / voltage circuit VG. It is also possible to accurately detect a voltage drop due to a disconnection or a contact failure at.

The output signals C1 to Cn of the voltage monitor circuits VM1 to VMn are the signal generation circuits SG1 to SG1 of the signal generator.
Input to SGn. The signals C1 to Cn control the output of the signals generated in the signal generation circuits SG1 to SGn. That is, it is determined that the operating voltage on the product mounting boards 1 to n is the desired operating voltage.
1-VMn, the input signals S1-Sn to the semiconductor device under test are permitted by the signal C, and when the operating voltages V1-Vn sufficiently rise or temporarily decrease, the individual operating voltages The input signals S1 to Sn to the semiconductor device under test are stopped according to V1 to Vn, and are forced to a low level like the ground potential of the circuit. As a result, in each of the product mounting boards 1 to n, when the operating voltage of the semiconductor device under test is substantially insufficient, all the input signals are forcibly set to the low level, and latch-up is prevented in advance. be able to.

FIG. 2 shows a circuit diagram of an embodiment of the voltage monitor circuit. The operating voltage V1 of the semiconductor device under test mounted on the product mounting board 1 or the like is divided by the resistors R1 and R2. This divided voltage V1 ′ is the voltage comparison circuit VC
Is supplied to one of the inputs (+). The reference voltage VREF is supplied to the other (-) input of the voltage comparison circuit VC. The reference voltage VREF is set in correspondence with the divided voltage V1 ′ of the operating voltage V1 immediately before it is inverted with respect to the input signal level. The voltage comparison circuit VC has a divided voltage V
When 1 ′ becomes lower than the reference voltage VREF, the output signal C1
Is set to a low level to inhibit signal output of the signal generating circuit SG1 and the like as described below.

FIG. 3 shows a circuit diagram of an embodiment of the signal generator. The signals S11 to S1m formed by the signal generating circuit SG1 represented by the black box are output through AND gate circuits G1 to Gm. The AND gate circuits G1 to Gm have a signal output enable signal SE formed by a flip-flop FF.
Is supplied. In the flip-flop FF, the output signal C1 formed by the voltage monitor circuit VM1 is supplied to the set input S. The output signal of the inverter circuit N receiving the signal C1 is supplied to the reset input R of the flip-flop FF. As a result, when the signal C1 is at the high level, the flip-flop FF is set and the signal output enable signal SE at the high level is output from the output terminal Q.
Is output. On the other hand, when the signal C1 is low level, the flip-flop FF is reset and the low level signal output enable signal SE is output from the output terminal Q.

The output signal Cn of the voltage monitor circuit VMn of the product mounting board n corresponding to the other power supply voltage circuit VGn,
Similarly to the above, the signal is transmitted to the flip-flop corresponding to the signal generating circuit SGn, and the output signal thereof controls the similar output gate circuit.

FIG. 4 shows an operation waveform diagram for explaining the present invention. When the power supply circuit VG1 starts operating, the operating voltage V1 rises. When the divided voltage V1 ′ of the operating voltage V1 reaches the reference voltage VREF, the signal S
E changes from low level to high level. As a result, the AND gate circuits G1 to Gm as described above open the gates, so that the signals S11 to S1m already generated by the signal generating circuit SG1 are the signals S for the burn-in test.
B1 to SBm are mounted on the product mounting board 1 and supplied to the semiconductor device under test.

As described above, the operating voltage is temporarily reduced due to the rise of the power supply, the sudden change of the load, the momentary interruption in the burn-in test device, etc., and the divided voltage V1 'is less than the reference voltage VREF. At this time, the signal SE goes low, closing the gates of the AND gate circuits G1 to Gm, and the signals SB1 to SBm for the burn-in test input to the semiconductor device under test are changed to the signal generation circuit SG1.
Are forced to a low level like the ground potential of the circuit irrespective of the signals S11 to S1m formed by. As a result, even if the operating voltage is lowered, the signal level does not become higher than that. As a result, the semiconductor device under test becomes a CMO.
Latch-up does not occur unlike the S circuit.

In this embodiment, when the burn-in test apparatus has a plurality of power supply voltage circuits VG1 to VGn, a voltage monitor circuit is provided corresponding to each of them to control the output of the corresponding signal generating circuit. Circuits VG1 to VG
It is possible to capture a subtle change in the load n (semiconductor device under test) depending on the situation, and it is possible to perform a highly reliable burn-in test of the semiconductor device.

The operational effects obtained from the above embodiment are as follows. That is, (1) a voltage monitor circuit for monitoring the operating voltage applied to the semiconductor device under test is provided, and when the operating voltage applied to the semiconductor device under test from the power supply voltage supply unit is equal to or higher than a predetermined voltage required for normal operation. By controlling the input signal generated by the signal generator to be supplied to the semiconductor device under test, the level of the input signal becomes higher than the operating voltage, causing abnormal operation such as latch-up. It is possible to obtain the effect that the above can be prevented.

(2) When it is composed of a plurality of power supply voltage circuits and a product mounting board and a signal generating circuit corresponding thereto,
Since the voltage is monitored corresponding to each and the signal input to the semiconductor device under test is controlled, it is possible to capture subtle fluctuations according to the status of the load (semiconductor device under test) in each power supply voltage circuit. As a result, it is possible to perform the burn-in test of the semiconductor device with high reliability.

(3) By providing a circuit for performing voltage monitoring in the product mounting section (furnace), the operating voltage supplied to the semiconductor device under test can be more accurately monitored.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the voltage monitor may monitor the operating voltage with a voltage comparator having a hysteresis characteristic. By utilizing such a hysteresis characteristic, it is possible to stably supply the burn-in test signal.

The function of selectively supplying the burn-in test signal to the semiconductor device under test may be provided on the product mounting board. In this case, the voltage monitor and the circuit for selectively supplying the signal can be connected in the product mounting section. The circuit for performing the voltage monitoring may be mounted on the power supply voltage circuit VG or the signal generation circuit SG. The present invention can be widely used as a semiconductor test device.

[0025]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a voltage monitor unit for monitoring the operating voltage applied to the semiconductor device under test is provided, and a signal is generated only when the operating voltage applied from the power supply voltage supply unit to the semiconductor device under test is equal to or higher than a predetermined voltage required for normal operation. By controlling the input signal generated by the section to be supplied to the semiconductor device under test, the occurrence of abnormal operation such as latch-up due to the level of the input signal becoming higher than the operating voltage can be prevented. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a burn-in test apparatus according to the present invention.

FIG. 2 is a circuit diagram showing an embodiment of a voltage monitor provided in the burn-in test device.

FIG. 3 is a circuit diagram showing an embodiment of a signal generator provided in the burn-in test device.

FIG. 4 is a waveform diagram for explaining an example of the operation of the burn-in test apparatus according to the present invention.

[Explanation of symbols]

VG1 to VGn ... Power supply voltage circuit, V1 to Vn ... Operating voltage, VM1 to VMn ... Voltage monitor circuit, C1 to Cn ... Monitor output signal, SG1 to SGn ... Signal generating circuit, S1.
Sn ... Input signal, S11-S1m ... Output signal of signal generation circuit, SB11-SB1m ... Burn-in test signal,
FF ... Flip-flop, N ... Inverter circuit, G1 ...
Gm ... AND gate circuit.

Claims (3)

[Claims] 1. A power supply voltage supply section for supplying an operating voltage to a semiconductor device under test, a product mounting section on which the semiconductor device under test is mounted, and inputs necessary for operation of an internal circuit of the semiconductor device under test. A signal generator that generates a signal and an operating voltage applied to the semiconductor device under test are monitored, and the signal generator is generated only when the operating voltage is equal to or higher than a predetermined voltage required for normal operation of the semiconductor device under test. And a voltage monitor unit for controlling the input signal generated by the device to be supplied to the semiconductor device under test. 2. The product mounting section has a function of bringing a device under test to a desired high temperature, and the voltage monitor section is provided in the product mounting section. 1. Semiconductor test equipment. 3. The signal generating section is provided with an output gate function for selectively outputting the generated signal to the device under test according to the voltage monitor output signal formed by the voltage monitoring section. The semiconductor test apparatus according to claim 1 or 2, which is characterized.