JPH0520870A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce chip area by reducing the number of data output buses. CONSTITUTION:Output data from a data amplifier 1 is transmitted on a single data output bus DO to one input terminal of a data output circuit 4. Data is transmitted on the data output bus DO to the other input terminal of the data output circuit 4 through an inverting circuit IV2. Prior to transmission of data, an intermediate potential Vmd is fed from an intermediate potential generating circuit 3 on the data output bus DO.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, the present invention relates to a semiconductor integrated circuit such as a semiconductor memory which is composed of a MOS field effect transistor and has a large capacity and a high speed.

[0002]

2. Description of the Related Art In recent years, as semiconductor memory has been required to have a large capacity, the area occupied by one memory cell has been reduced to increase the capacity without increasing the chip area. Not only the size of itself, but also the size of the peripheral circuit has become a problem due to the addition of various functions such as a test mode.

On the other hand, there is an increasing demand for high-speed access, and in particular, there are some which are provided with a means for speeding up the level inversion of output data.

FIG. 5 shows an example of a conventional semiconductor integrated circuit of this type.

This semiconductor integrated circuit is activated by an activation signal DE, amplifies a potential difference between a pair of first and second data input / output buses I01 and I02, and has complementary levels corresponding to the potential difference. A data amplifier 1a for outputting data, first and second data output buses D01, D02 for transmitting the output data of the data amplifier 1a, and a predetermined pulse upon detecting that the address value of the address signal AD has changed After the control signal OSP of the one-shot pulse of the width is output, the address change detection circuit 2 which outputs the activation signal DE of the one-shot pulse of the predetermined pulse width and the data output buses D01 and D02 are conducted by the control signal OSP. Transistor Q1 that sets the state and makes its level uniform
And the data output bus D activated by the output control signal OE
The data output circuit 4 outputs the output data OUT having a level corresponding to the level difference between 01 and D02.

Next, the operation of this semiconductor integrated circuit will be described. FIG. 6 is a timing waveform diagram of signals at various parts for explaining the operation of the semiconductor integrated circuit.

When the address value of the address signal AD from the outside changes, first of all, a one-shot pulse control signal OS is generated.
P is generated, and the transistor Q1 causes the data output bus D
01 and D02 are short-circuited.

At this time, since the activation signal DE is at the low level, the data amplifier 1a is not activated.
The data output bus D0 which has been high level of the power supply potential Vcc level and low level of the ground potential level (0V) so far.
The levels of 1 and D02 are made uniform and become approximately Vcc / 2.

The address value of the address signal AD changes, and data is read from the memory cell or the like having this address value.
It is transmitted to the data input / output buses I01 and I02. At the timing of this side, the control signal OSP becomes low level, the transistor Q1 is turned off, and the activation signal DE becomes high level, whereby the data input / output bus I0 by the data amplifier 1a.
The potential difference between I1 and I02 is amplified to the power supply potential Vcc level and the ground potential level and the data output buses D01 and D02 are amplified.
Be transmitted to.

After this, the output control signal OE becomes high level, the data output circuit 4 is activated, and the data output bus D0.
Output data OUT is output at a level corresponding to the levels of 1, D02, for example, D01 is a high level, D02 is a low level, and vice versa. The output data OUT is usually output in parallel for a plurality of bits.

In this way, the data output buses D01 and D0
Before transmitting the output data of the data amplifier 1a to 2, the levels of these data output buses DO1 and DO2 are made uniform and set to an intermediate level of high level and low level. After that, the output data of the data amplifier 1a is output as data. Bus D
By transmitting to O1 and DO2, it changes from the intermediate level to the high level and the low level. Therefore, the operation speed should be faster than when changing from the high level to the low level and from the low level to the high level suddenly. You can

In this semiconductor integrated circuit, in recent years, this function improvement or complexity (for example, a test mode, more bits than the number of output bits are internally determined, correctness is determined, and then compressed to the number of output bits for testing. Mode, that is, a function that shortens the test time of the chip)
As a result, the number of data buses running inside the chip is increasing regardless of the number of output bits.

[0013]

The above-described conventional semiconductor integrated circuit is provided with two data output buses D01 and D02 for each bit of output data in order to increase the speed, and to make these levels uniform. Data amplifier 1a
The number of data buses running inside the chip is increasing due to the improved functions and complexity, and the disadvantage is that the chip area increases due to these data buses. It was

An object of the present invention is to provide a semiconductor integrated circuit which can reduce the chip area without impairing the speeding up of the operation.

[0015]

A semiconductor integrated circuit of the present invention is activated by an activation signal to amplify a potential difference between a pair of first and second data input / output buses, and a level corresponding to the difference potential. A data amplifier for outputting the data of, and a data output bus for transmitting the output data of the data amplifier,
An intermediate potential generation circuit that generates an intermediate potential at an intermediate level between the high level and the low level of the data transmitted through the data output bus, and an intermediate potential from the intermediate potential generation circuit that is conducted by a control signal and is connected to the data output bus. A transistor to be supplied, a control circuit for generating the activation signal and the control signal, each of which has an active level for a predetermined period at a predetermined timing, a first inverting circuit for inverting the level of the control signal, and the first inverting circuit. A second inverting circuit that is activated by the output signal of the inverting circuit and inverts the level of the data of the data output bus, and a signal of a level corresponding to the output data of the second inverting circuit and the level of the data of the data output bus And a data output circuit for outputting.

[0016]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, the first and second data input / output buses I01, I01, which are activated by the activation signal DE and form a pair,
A data amplifier 1 that amplifies a difference potential between I02 and outputs data of a level corresponding to the difference potential, a data output bus DO that transmits output data of the data amplifier 1, and a data that transmits the data output bus DO High level (power supply potential Vcc level) and low level (ground potential level,
0V) intermediate level intermediate potential Vmd (Vcc / 2)
Detecting a change in the address value of the address signal AD, an intermediate potential generating circuit 3 for generating a signal, a transistor Q1 which is conductive by the control signal OSP and supplies the intermediate potential Vmd from the intermediate potential generating circuit 3 to the data output bus DO. Then, after outputting the control signal OSP of the one-shot pulse having a predetermined pulse width, the address change detection circuit 2 which outputs the activation signal DE of the one-shot pulse of the predetermined pulse width and the level of the control signal OSP are inverted. First inversion circuit IV1
And a second signal which is activated by the output signal of the first inversion circuit IV1 and inverts the level of the data on the data output bus DO.
And the data output circuit 4 for outputting the output data OUT of the level corresponding to the levels of the output data of the second inversion circuit IV2 and the data of the data output bus DO.

Next, the operation of this embodiment will be described.
FIG. 2 is a timing waveform chart of signals of respective parts for explaining the operation of this embodiment.

The data amplifier 1 is activated by the activation signal DE, amplifies the potential difference between the data input / output buses I01 and I02, and outputs one data. This data is transmitted to one input terminal of the data output circuit 4 by one data output bus DO.

The inverting circuit IV2 inverts the level of the data on the data output bus DO and transmits it to the other input terminal of the data output circuit 4. When the address transition detection circuit outputs the control signal OSP in the same manner as in the conventional example, the transistor Q1 becomes conductive and the intermediate potential Vm is applied to the data output bus DO.
d (Vcc / 2) is supplied, and the data output bus DO becomes the intermediate potential (Vcc / 2). Further, the control signal OSP is transmitted to the inverting circuit IG2 via the inverting circuit IV1 to deactivate the inverting circuit IV2 to prevent a through current from flowing. The output data (DOn) of the inversion circuit IV2 receives the level of the data output bus DO until the control signal OSP is transmitted via the inversion circuit IV1 and receives the intermediate potential (Vn).
It is cc / 2).

When the control signal CSP becomes low level, the transistor Q1 becomes non-conductive, the activation signal DE is output, and the output data of the data amplifier 1 is transmitted to the data output bus DO, the inverting circuit IV2 is also activated. Therefore, the output data of the data amplifier 1 is transferred from the inverting circuit IV2 to the other input terminal of the data output circuit 4 at substantially the same timing as when it is transmitted to one input terminal of the data output circuit 4 via the data output bus DO. The data is also transmitted. That is, even with one data output bus DO, it is possible to obtain almost the same operating speed as in the conventional example using two data output buses, and the number of data output buses can be reduced by half.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the RAS control circuit 5 controls the data amplifier 1, the transistor Q1, and the inverting circuit IV.
2 is controlled.

In this embodiment, as shown in FIG. 4, when the external RAS system control signal RAS is at a high level in standby, the levels of the data input / output buses I01 and I02 are equalized to a high level. The control circuit 5 is usually
When the RAS system control signal RAS from the outside is at a high level for making the transistor Q1 conductive and the active level is at a low level, the one-shot pulse control signal OSPa of a low level for making the transistor Q1 non-conductive for a predetermined period is output and , And outputs the activation signal DE which becomes the activation level (high level) in synchronization with the low level of the control signal OSPa. The basic operation and effect are similar to those of the first embodiment.

[0026]

As described above, according to the present invention, the output data of the data amplifier is transmitted to one input end of the data output circuit by one data output bus, and the data is output to the other input end of the data output circuit. By transmitting the data of the output bus through the inverting circuit and supplying the intermediate potential from the intermediate potential generation circuit to the data output bus before transmitting the data to make it the intermediate potential, the data output The number of data output buses can be halved and the chip area can be reduced at almost the same operating speed as the conventional example having two buses.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a timing waveform chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a block diagram showing an example of a conventional semiconductor integrated circuit.

FIG. 6 is a timing waveform chart of signals of respective parts for explaining the operation of the semiconductor integrated circuit shown in FIG.

[Explanation of symbols]

1,1a data amplifier 2 Address change detection circuit 3 Intermediate potential generation circuit 4 Data output circuit 5 RAS control circuit DO, D01, D02 data output bus I01, I02 data input / output bus IV1, IV2 inversion circuit Q1 transistor

Claims (3)

[Claims] 1. A first pair which is activated by an activation signal to form a pair.
And a data amplifier that amplifies a potential difference between the second data input / output bus and outputs data of a level corresponding to the potential difference, a data output bus that transmits output data of the data amplifier, and a data output bus. An intermediate potential generation circuit that generates an intermediate potential at an intermediate level between the high level and the low level of data to be transmitted, and a transistor that is turned on by a control signal and supplies the intermediate potential from the intermediate potential generation circuit to the data output bus, A control circuit for generating the activation signal and the control signal, each of which has an active level for a predetermined period at a predetermined timing, a first inverting circuit for inverting the level of the control signal, and an output signal of the first inverting circuit. A second inverting circuit that is activated by the above-mentioned data inverting circuit and inverts the level of the data on the data output bus, and the output data of the second inverting circuit and the data. The semiconductor integrated circuit and having a data output circuit for outputting a signal of a level corresponding to the level of the force data bus. 2. The control circuit detects that the address value of the address signal has changed and outputs a control signal of a one-shot pulse having a predetermined pulse width, and then an activation signal of a one-shot pulse having a predetermined pulse width. 2. The semiconductor integrated circuit according to claim 1, which is an address change detection circuit that outputs 3. The control circuit is normally at a first level for turning on a transistor and at a second level for turning off the transistor for a predetermined period when an external RAS system control signal becomes an active level. R that outputs a shot pulse control signal and outputs an activation signal that becomes an activation level in synchronization with the second level of this control signal
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an AS control circuit.