JPH05206400A - Semiconductor memory device and manufacture of the same - Google Patents

Abstract

PURPOSE:To increase the area of a capacitor by forming irregularities shaped in lateral stripes in part of the side of a storage node electrode. CONSTITUTION:After forming a storage node contact 8, a resist is applied, and exposed to light by optical lithography with a mask of a pattern which is rather smaller than that of the storage node electrode. If monochromatic light such as of an excimer laser beam is used as the light source for the exposure, the light incident upon the photoresist and the reflected light from the ground interfere with each other, generating a standing wave in the resist. Thus, the light intensity within the resist periodically varies in the depth direction. Accordingly, on the side of the photoresist pattern R irregularities are formed in lateral stripes. If an LPD film 9 is deposited on it, the pattern shape of the resist is transferred, and the irregularities shaped in lateral stripes are transferred to the side of the LPD film as a pattern transfer film if a storage node electrode is formed after removal of the resist. A polycrystalline silicon film is deposited, and an electrode 10 is formed after arsenic doping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a capacitor structure in a DRAM or the like.

[0002]

2. Description of the Related Art In recent years, the so-called MOS type semiconductor memory device (DRAM) has been highly integrated and has a large capacity rapidly due to the progress of semiconductor technology, especially the fine processing technology.

With the increase in the degree of integration, the area of the capacitor for storing information (charge) is reduced, and as a result, the memory contents are erroneously read out, or the memory contents are destroyed by α rays or the like. Is a problem.

As one of methods for solving such a problem and achieving high integration and large capacity, a MOS capacitor is laminated on a memory cell region and one electrode of the capacitor and a semiconductor substrate are formed. A memory cell structure called a stacked memory cell, in which one electrode of the formed switching transistor is electrically connected to substantially expand the occupied area of the capacitor and increase the capacitance of the MOS capacitor. Is proposed.

In such a structure, the storage node electrode can be expanded to above the element isolation region, and
Since the thickness of the storage node electrode can be increased and the side wall thereof can be used as a capacitor, the capacitance of the capacitor can be increased to several times or more that of the planar structure. Further, the diffusion layer in the storage node portion is only the diffusion layer region under the storage node electrode, and the area of the diffusion layer that collects the charges generated by α rays is extremely small, and the cell is resistant to soft error. It has a structure.

However, even in the DRAM having such a stacked memory cell structure, the area occupied by the memory cell is reduced and the flat portion of the storage node electrode is reduced as the miniaturization of the element progresses with the high integration. The area is becoming smaller and smaller, and it is becoming difficult to secure a sufficient capacitor capacity.

Therefore, in order to secure the amount of accumulated charge, the side surface of the storage node electrode should be used effectively.
The film thickness must be at least about 1 μm. It is difficult to finely process such a thick storage node electrode, which causes a short circuit between storage node electrodes. Further, the thick storage node electrode imposes a heavy burden on the fine processing of the wiring thereon. Furthermore, the doping of impurities by ion implantation or the like becomes insufficient, and it is difficult to form a good contact with the substrate or the pad.

Further, various capacitor structures have been recently proposed to reduce this step, but in any case, it is an object to ensure a sufficient capacitor capacity as the degree of integration increases.

[0009]

As described above, even in a DRAM having a stacked memory cell structure, the area occupied by the memory cell is further reduced as the device is further miniaturized due to higher integration, and the accumulated charge is reduced. In order to secure the amount, the film thickness of the storage node electrode must be increased, which causes a problem that contact characteristics are deteriorated.

The present invention has been made in view of the above circumstances, and when the area occupied by a memory cell is further reduced,
An object of the present invention is to provide a memory cell structure having good contact characteristics and capable of ensuring a sufficient capacitor capacity.

[0011]

Therefore, the first D of the present invention is provided.
In the RAM, horizontal stripe-shaped undulations are formed on at least a part of the side surface of the storage node electrode.

Preferably, the storage node electrode is
It is formed outside the contact surface with the source / drain region so as to project substantially perpendicularly to the contact surface and with a curved surface.

In the second method of the present invention, a standing wave is formed by interfering the incident wave and the reflected wave of the light passing through the resist by using the photolithography method, and a horizontal stripe-shaped undulation is formed on the side surface of the resist. The storage node electrode having the horizontal stripe-shaped undulations on the side surface is formed by patterning the horizontal stripe-shaped undulations to the electrode material.

Further, in the third method of the present invention, a film having a glass transition temperature is used as a transfer film, and polycrystalline silicon is used as an etching stopper when forming a storage node contact with respect to this film. In the step of oxidizing the crystalline silicon film, at the same time, the transfer film is put in a molten state to have a rounded edge, and a storage node electrode is formed so as to cover the edge to obtain a storage node electrode having a curved side wall portion, After that, the transfer film is removed, and both sides of the side wall are used as capacitors.

More preferably, after forming the first polycrystalline silicon film, a film having a glass transition temperature is formed and used as a pattern transfer film, and the first polycrystalline film is used as an etching stopper for this film. An inversion pattern of the storage node contact is formed by using silicon, the transfer film is melted, the edges are rounded, and a second polycrystalline silicon film is formed so as to cover the edge, and then the transfer film is formed. Is removed by etching to obtain a storage node electrode having a curved side wall, and both sides of this side wall are used as capacitors.

In the fourth method of the present invention, two kinds of films are alternately laminated, openings are formed in these multi-layered films, and the two kinds of films are etched under different etching rates.
After forming a storage node contact having unevenness on the side wall and forming an electrode material in this storage node contact, the multilayer film is removed and pattern transfer is performed to form a storage node electrode having a protruding portion having unevenness on the side wall. Is forming.

[0017]

According to the first structure described above, since horizontal stripe-shaped undulations are formed on a part of the side surface of the storage node electrode,
This undulation can increase the capacitor area. Therefore, the capacitance can be increased without increasing the area occupied by the capacitor. Moreover, storage
Since the surface area of the storage node electrode can be increased without increasing the film thickness of the storage electrode, the processing becomes easy and a highly reliable DRAM can be obtained.

Further, if the storage node electrode is projected to the outside of the contact surface with the source / drain region so as to be substantially perpendicular to the contact surface and has a curved surface, the storage is further improved. The surface area of the node electrode can be increased.

Further, according to the second method, a standing wave is formed by interfering the incident wave and the reflected wave of the light passing through the resist by using the photolithography method, and the lateral stripe-shaped undulations are formed in the resist. By forming on the side surface and transferring this shape, it is possible to form a storage node electrode having lateral stripe-shaped undulations on the side surface. Therefore, the electrode material has a single-layer structure and is easy to manufacture. In addition, the undulation period can be controlled by the wavelength of light and the dielectric constant of the resist pattern, and the undulation can be controlled by the reflectance on the upper and lower surfaces of the resist, the light absorption rate in the resist and the sensitivity of the resist. Can be controlled.

Further, according to the third method, the polycrystalline silicon film used as the etching stopper is oxidized at the same time as B
Since a film having a glass transition temperature such as a PSG film is melted to form a storage node electrode with a rounded edge to form a curved protruding piece at the peripheral edge of the storage node electrode, the number of steps is increased. Without increasing the storage node electrode surface area.

Preferably, after forming the first polycrystalline silicon film, B is used as an etching stopper to form an inverted pattern of the storage node contact.
A film having a glass transition temperature, such as a PSG film, is patterned, and then a heat treatment is performed to melt and round the edges, and then a second polycrystalline silicon film is formed. If the first polycrystalline silicon film is used as the storage node electrode and the second polycrystalline silicon film is used as the curved protruding piece at the peripheral portion of the storage node electrode, the storage node electrode can be easily formed without increasing the number of steps. The surface area of the can be increased.

According to the fourth aspect of the present invention, two types of films are alternately laminated and a multilayer film is etched under conditions such that the etching rates of the two types of films are different to form a storage node contact having unevenness on the side wall. Then, after forming the electrode material in the storage node contact, the multilayer film is removed and pattern transfer is performed to form the storage node electrode having the protrusion having the unevenness on the side wall. The surface area of the electrode can be increased.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings.

Embodiment 1 FIG. 1 is a sectional view showing two bits adjacent to each other in the bit line direction of a DRAM having a stacked memory cell structure according to a first embodiment of the present invention, FIGS. c) is the manufacturing process diagram.

In this DRAM, a MOSFET is formed in a region surrounded by an element isolation insulating film 2 of a p-type silicon substrate 1, and a storage node electrode 10 is connected to one of source and drain regions of this MOSFET. A capacitor is laminated, which is characterized in that horizontal stripe-shaped undulations are formed on the side surfaces of the storage node electrode 10 to increase the capacitor area. Other parts are the same as those of the conventional DRAM having the stacked memory cell structure.

That is, in the MOSFET, the gate electrode 5 is formed in the region surrounded by the element isolation insulating film 2 of the p-type silicon substrate 1 through the gate insulating film 4, and the source is self-aligned with the gate electrode 5. -It is configured by forming the n-type diffusion layers 6a and 6b to be the drain diffusion layers.

A storage node electrode 10 is formed through storage node contact 8 on 6b of these n-type diffusion layers 6a and 6b connected to the capacitor, and bit line 14 is formed on 6a through a bit line contact.
Is formed. A p-type diffusion layer 3 for punch-through stopper is formed on the bottom of the element isolation insulating film 2.
In this structure, the capacitance corresponding to the sum of the undulations of the side surface of the storage node electrode can be obtained from the side wall portion thereof.

Next, a method of manufacturing this DRAM will be described with reference to the drawings.

First, as shown in FIG. 2 (a), the specific resistance is 5Ω.
An element isolation insulating film 2 of a 700 nm-thickness silicon oxide layer is formed on a cm-type p-type silicon substrate 1 by a normal LOCOS method. By the oxidation step at this time, the p-type diffusion layer 16 for punch through stopper is formed. After that, if necessary, ion implantation for threshold control is performed on the element region. Then, a silicon oxide layer having a film thickness of 10 nm and a polycrystalline silicon layer having a film thickness of 300 nm are formed by a thermal oxidation method, and these are patterned by a photolithography method and a reactive ion etching method to obtain a gate insulating film 4 and a gate insulating film. Forming the electrode 5. Then, As ions are ion-implanted by using the gate electrode 5 as a mask, and the n--type diffusion layer 6 is formed.
A source / drain region consisting of a and 6b is formed to form a MOSFET as a switching transistor. The depth of this diffusion layer is, for example, about 150 nm.
After that, an interlayer insulating film 7 made of a flat silicon oxide film is formed on the entire surface. This may be formed, for example, by depositing phosphorous glass and then melting it by a thermal process, or by depositing a thick silicon oxide film or the like and then scraping the silicon oxide film from the upper side by a lapping method. It may be selected as appropriate. Further, as the pattern of the gate electrode becomes finer as the integration becomes higher, even if it is deposited by a method with good step coverage such as an insulating film LPCVD method having a film thickness of ½ or more of the space between the gate electrodes, it is considerably flattened. Is possible. This flattening is important in the sense that the film thickness of the resist is constant when forming the capacitor.

Further, a silicon nitride film 7s is deposited as an etching stopper for etching the LPD film for transferring the horizontal stripe pattern of the resist.

Then, after forming the storage node contact 8, a resist is applied and exposure is performed by photolithography using a mask having a pattern slightly smaller than the pattern of the storage node electrode. When monochromatic light such as an excimer laser is used as a light source used for this exposure, incident light to the photoresist interferes with reflected light from the underlayer, and a standing wave is generated in the resist. Therefore, the light intensity in the resist periodically changes in the depth direction, so that the side surface of the photoresist pattern R is made to have horizontal stripe-shaped undulations as shown in FIG. When the LPD film 9 is deposited on this upper layer, it is not formed on the resist pattern, so that the pattern shape of this resist is transferred. Alternatively, a film may be deposited by vapor deposition or sputtering and then etched back. After that, if the resist is removed to form the storage node electrode, horizontal stripe-shaped undulations are transferred to the side surface of the LPD film as the pattern transfer film.

Then, as shown in FIG. 2B, as the storage node electrode, for example, a polycrystalline silicon film having a thickness of 50-4 is used.
Then, the storage node electrode 10 is formed by depositing it to a thickness of 00 nm, doping it with arsenic or phosphorus, and patterning it by photolithography and reactive ion etching.

Here, the LPD film becomes a silicon oxide film by heating and can be used as it is as an interlayer insulating film. However, since the side surface of the storage node electrode is used as a capacitor here, it is removed by etching using ammonium fluoride. I am trying to do it. At this time, the silicon nitride film 7s is used as an etching stopper.

After the LPD film 9 is removed by etching in this manner, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 11. .. After that, a polycrystalline silicon film is deposited on the entire surface, arsenic or phosphorus is doped therein, and then the plate electrode 12 is formed by photolithography and dry etching (FIG. 2 (c)).

Next, a CVD oxide film is deposited on the entire surface as an interlayer insulating film, a bit line contact is formed by photolithography and reactive ion etching, and a bit line 14 using an aluminum film or molybdenum polycide is formed. In this way, the DRAM shown in FIG. 1 is completed.

According to the above structure, since lateral stripe-shaped undulations are formed on the side surfaces of the storage node electrode, as a result, a large capacitor capacitance can be realized with a small occupied area.

Next, the principle of standing wave generation for forming the horizontal stripe-shaped undulations will be described.

In FIG. 3A, monochromatic light enters the photoresist from the atmosphere, passes through the resist pattern and the underlying silicon oxide film, is reflected by the silicon substrate, and passes through the resist again. And, in reality, it shows how the light is reflected () at the interface between the resist and the atmosphere. Repeat ~ like this. (b)
Shows the intensity ε2 of the incident wave and the intensity ε3 of the reflected wave. The phase shifts when reflected on the surface of the silicon substrate. When the incident wave and the reflected wave having different phases are added together, a standing wave is generated in the resist film as shown in (c). The standing wave has a maximum intensity node and a minimum intensity node, and occurs periodically through the membrane. This periodic light intensity distribution appears as horizontal stripe-shaped undulations of the resist pattern. This is because the solubility of the resist in the developing solution is proportional to the intensity distribution of exposure. In this way, a resist pattern having lateral stripes on the side surface can be obtained.

Although the storage node electrode pattern is formed to be larger than the resist pattern used to form the undulations due to standing waves in the above embodiment, the method for processing the storage node electrode is shown in FIG.
After depositing a resist on the entire surface as shown in, exposing the entire surface,
By controlling the exposure amount so that only the storage node contact is unexposed, only the resist buried in the storage node contact can be left. Then, dry etching is performed in this state to remove unnecessary portions of polycrystalline silicon, whereby the storage node electrode can be formed in a self-aligned manner with respect to the storage node contact.

Second Embodiment Next, a second embodiment of the present invention will be described.

In the above-mentioned embodiment, when the wavelength of the stepper used for exposure is shortened, the period of unevenness formed by the standing wave is λ / 4n, and therefore the period of unevenness is also shortened. Then, the thickness of the storage node electrode fills the irregularities, and the irregularities on the surface not facing the resist pattern disappear. Therefore, in order to further increase the surface area of the storage node electrode, the deposition conditions of polycrystalline silicon as the storage node electrode material are controlled to form irregularities on the surface of the polycrystalline silicon.

FIGS. 5A to 5E are process diagrams.

First, similar to the first embodiment, the MOSFET is
A resist pattern 8 having lateral stripe-shaped undulations of a standing wave is formed on the side surface after the formation of the gate electrode. Prior to this, the gate electrode 5 and the side wall are covered with a silicon nitride film or the like to form a storage node contact for the gate electrode. It is characterized in that the bit line contact is not required to be aligned with the gate electrode, and unevenness is formed on the surface of the polycrystalline silicon film as the storage node electrode 10.

First, a silicon oxide film to be the gate insulating film 4 is formed on the p-type silicon substrate 1 and the gate electrode 5 is formed.
After forming a polycrystalline silicon film to be the above and a silicon nitride film 5s to be the insulating film on the gate, patterning these,
A MOSF serving as a switching transistor is formed by forming a source / drain region consisting of n-type diffusion layers 6a and 6b.
Form ET. Then, the surface is further lightly oxidized to form a silicon oxide film 7a, and the silicon nitride film 7s is used as an etching stopper for etching the LPD film for transferring the lateral stripe pattern of the resist as in the first embodiment.
Deposit.

After that, a resist is applied and exposure is performed by photolithography using a mask. A monochromatic light such as an excimer laser is used as a light source used for this exposure, and the incident light to the photoresist interferes with the reflected light from the underlayer so that a standing wave is generated in the resist. As shown in Fig. 5 (a), the side surface should be wavy with horizontal stripes. Then, the LPD film 9 is deposited.

Then, when the resist is removed, lateral stripe-shaped undulations are transferred to the side surface of the LPD film as the pattern transfer film. Then, the thin silicon nitride and silicon oxide under the resist pattern are etched by RIE to form a storage node contact 8 and a storage node electrode is formed in this contact.

As shown in FIG. 5B, the storage node electrode is, for example, a polycrystalline silicon film having a thickness of 50-4.
Then, the storage node electrode 10 is formed by depositing it to a thickness of 00 nm, doping it with arsenic or phosphorus, and patterning it by photolithography and reactive ion etching. At this time, the deposition temperature of the polycrystalline silicon film is set to 550 ° C.
Asperity is formed on the surface of the storage node electrode (IEDM 1990).

Furthermore, the LPD film 9 is removed by etching using ammonium fluoride. At this time, the silicon nitride film 7s is used as an etching stopper.

After the LPD film 9 is removed by etching in this way, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 11. .. After that, a polycrystalline silicon film is deposited on the entire surface, and arsenic or phosphorus is doped therein, and then the plate electrode 12 is formed by photolithography and dry etching. Then, a protective silicon oxide film 16 is formed on the surface of the plate electrode by surface oxidation (FIG. 5 (c)).

Thereafter, as in the first embodiment, a BPSG film 13S is deposited on the entire surface as an interlayer insulating film, and a bit line contact is formed by photolithography and reactive ion etching. By using the polycrystalline silicon film 17 as an etching stopper when forming the bit line contact, it is possible to prevent the bit line contact from short-circuiting with the gate or plate electrode.

Then, the polycrystalline silicon film 17 is further etched by using the underlying silicon nitride film 7s as a stopper,
The remaining polycrystalline silicon film 17 is oxidized by thermal oxidation to be converted into a silicon oxide film 20 to firmly protect the plate electrode. By this heat treatment, the BPSG film is melted and the corners are rounded. Then, the silicon oxide film and the silicon nitride film are removed to form a contact.

Then, a bit line such as an aluminum film or molybdenum polycide is formed to complete the DRAM.

With this method, it is possible to prevent the capacitance of the capacitor from decreasing and further miniaturize it.

In the first and second embodiments, the undulations of the resist pattern sidewalls formed by the standing wave are temporarily removed by LPD.
Transfer to a film to form a storage node electrode,
Although the capacitor insulating film is formed after removing the D film, the LPD film may be used as an insulating film as it is when the capacitor area is sufficient. It is also possible to directly obtain a storage node electrode having horizontal stripe-shaped undulations by directly filling the groove with an electrode material without using a medium for transferring the undulations of the resist pattern side wall formed by a standing wave. is there. In this case, a groove may be formed in which both side walls are surrounded by a cylindrical wall having horizontal stripe undulations, and a conductor film may be formed in this groove by the LPD method or the like.

Third Embodiment Next, a third embodiment of the present invention will be described.

In this method, instead of using a standing wave, the transfer mask is melted at the same time as the oxidation of the polycrystalline silicon film used as the etching stopper to form a rounded edge and the arm curved surface is transferred to the storage node electrode surface. However, it is characterized in that the area of the capacitor is increased.

FIGS. 6 (a) to 6 (c) are views showing a part of the manufacturing process. In the second embodiment, the surface and the side surface of the gate electrode 5 are covered with the silicon nitride films 5s and 7a,
After the silicon oxide film 7b and the silicon nitride film 7s are formed on the surface, a polycrystalline silicon film 21 is formed as an etching stopper, and a BPSG film 23 is formed on the polycrystalline silicon film 21, and the storage node is formed as shown in FIG. 6 (a). The contact 8 is formed.

After that, the polycrystalline silicon film 21 in the contact 8 is removed by etching, and then 85 in a water vapor atmosphere.
A heat treatment is performed at 0 to 900 ° C. to oxidize the polycrystalline silicon film 21 as an etching stopper and to etch the silicon oxide film 20.
To protect the plate electrode. By this heat treatment, the BPSG film is melted and the corners are rounded. Then, the silicon oxide film and the silicon nitride film are removed,
A contact is formed.

The BPSG film 2 thus curved in a round shape
If the storage node electrode 10 is formed on the surface of FIG.
As shown in (b), the curved shape is transferred to the storage node electrode.

Then, as shown in FIG. 6C, after the BPSG film 23 is removed by etching, a silicon nitride film is deposited on the entire surface by LPCVD to a thickness of about 10 nm and is oxidized in a steam atmosphere at 950 ° C. for about 30 minutes. The capacitor insulating film 11 is formed. After that, a polycrystalline silicon film is deposited on the entire surface, and arsenic or phosphorus is doped therein, and then the plate electrode 12 is formed by photolithography and dry etching. Then, by surface oxidation, a protective silicon oxide film 16 is formed on the surface of the plate electrode.

Thereafter, similarly to the second embodiment, an interlayer insulating film is deposited on the entire surface, and a bit line contact is formed by photolithography and reactive ion etching.

Then, a bit line such as an aluminum film or molybdenum polycide is formed to complete the DRAM.

Also in the DRAM thus formed, the surface area of the storage node electrode can be increased and the capacitance of the capacitor can be increased.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described.

In this method, the curvature direction of the storage node electrode is reversed from that of the third embodiment. As in the third embodiment, the transfer mask is melted to form a rounded edge, and the arm curved surface is transferred to the surface of the storage node electrode. However, it is characterized in that the area of the capacitor is increased.

FIGS. 7A to 7C are views showing a part of the manufacturing process thereof. In the third embodiment, the surface and the side surface of the gate electrode 5 are covered with the silicon nitride films 5s and 7a, and the surface is covered. Silicon oxide film 7b and silicon nitride film 7
However, the silicon nitride film covering the side wall of the gate electrode is used as it is instead of the thin silicon nitride film. Then, this silicon nitride film 27 is patterned to form a storage node contact. Then, after depositing the first polycrystalline silicon film 10a which will be the lower part of the storage node electrode, the BPSG film 33 is deposited, and the first polycrystalline silicon film 10a is deposited.
Patterning is performed using the polycrystalline silicon film 10a of the above as an etching stopper to form a BP in the storage node contact region.
The SG film 33 is left (FIG. 7 (a)).
As shown in (b), a second polycrystalline silicon film 10b to be the upper part of the storage node electrode is deposited.

Then, as shown in FIG. 7C, the polycrystalline silicon film 10 on the flat portion is removed by the whole surface reactive ion etching, and the BPSG film 33 is further etched to obtain the curved storage node electrode 10. And Example 3
Similarly to the capacitor insulating film 11 and the plate electrode 12
To form a capacitor. Reference numeral 16 is a silicon oxide film for protecting the plate electrode.

After that, the same processes as in Examples 2 and 3 were performed.
DRAM is completed.

Embodiment 5 Next, a fifth embodiment of the present invention will be described.

FIGS. 8A to 8C are a part of the process chart.

In this example, the transfer mask of the storage node electrode is formed of the BPSG film 37a and the CVD silicon oxide film 37.
It is characterized in that the storage node electrode 40 is formed in a fin shape by forming a multilayer structure in which b and b are alternately stacked, and etching is performed under conditions such that etching rates are different from each other to form unevenness on the side wall.

Also in this method, as in the third embodiment, the silicon nitride films 5s and 7a are formed on the surface and the side surface of the gate electrode 5.
Then, after forming a silicon oxide film 7b and a silicon nitride film 7s on the surface, a polycrystalline silicon film 21 as an etching stopper is formed, and a BPSG film 37a and a CVD silicon oxide film 37b are alternately formed as an upper layer on this film. It has a multi-layered structure in which layers are laminated, and wet etching is performed under conditions such that the etching rates are different from each other to form holes having unevenness on the side wall in the storage node contact region (FIG. 8A). Alternatively, the contact hole may be opened by RIE using the polycrystalline silicon film as a stopper, and then may be laterally etched by wet etching.

Then, the polycrystalline silicon film 21 in the contact 8 is removed by etching, and then the polycrystalline silicon film 10 as a storage node electrode is formed (FIG. 8B).
).

After this, similarly, the BPSG films 37a and C are similarly formed.
After removing the VD silicon oxide film 37b by etching, LP
A silicon nitride film is deposited to a thickness of about 10 nm by the CVD method and is oxidized in a steam atmosphere at 950 ° C. for about 30 minutes to form a capacitor insulating film 11. After that, a polycrystalline silicon film is deposited on the entire surface, and arsenic or phosphorus is doped therein, and then the plate electrode 12 is formed by photolithography and dry etching. Then, by surface oxidation, a protective silicon oxide film 1 is formed on the plate electrode surface.
6 is formed.

In this way, a storage node electrode having a single layer structure and a fin shape can be easily formed.

In the above embodiment, a multilayer structure film in which two layers of the BPSG film 37a and the CVD silicon oxide film 37b are alternately laminated is used when forming the mask for transferring the storage node electrode. Any laminate of the above films can be appropriately changed.

[0077]

As described above, according to the semiconductor memory device of the present invention, it is easy to manufacture and a sufficient capacitor capacity can be secured even when the area occupied by the memory cell is further reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a DRAM having a stacked memory cell structure according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of the DRAM.

FIG. 3 is a diagram showing the principle of standing wave generation.

FIG. 4 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of the DRAM of the second embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a DRAM according to a third embodiment of the present invention.

FIG. 7 is a manufacturing process diagram of a DRAM according to a fourth embodiment of the present invention.

FIG. 8 is a manufacturing process diagram of a DRAM of a fifth embodiment of the present invention.

[Explanation of symbols]

 1 p-type silicon substrate 2 element isolation insulating film 3 channel stopper 4 gate insulating film 5 gate electrode 6 source / drain region 7 insulating film 7s silicon nitride film 8 storage node contact 10 storage node electrode 11 capacitor insulation Membrane 12 Plate electrode Electrode 14 Bit line

Claims (4)

[Claims] 1. A capacitor comprising a MOSFET and a storage node electrode, a capacitor insulating film, and a plate electrode connected to a source or drain region of the MOSFET through a storage node contact. To form a memory cell by D
In the RAM, the semiconductor memory device is characterized in that the storage node electrode has lateral stripe-shaped undulations on at least a part of its side surface. 2. A MOSFET forming step of forming a MOSFET in a semiconductor substrate, and a storage node electrode and a capacitor insulation connected to a source or drain region of the MOSFET via a storage node contact. A method of manufacturing a semiconductor memory device, comprising: a capacitor forming step of laminating a capacitor including a film and a plate electrode, wherein the storage node electrode forming step applies a resist to the surface of the semiconductor substrate on which a MOSFET is formed. A resist coating step, and a resist pattern forming step of forming a standing wave by causing an incident wave and a reflected wave of light passing through the resist to interfere with each other by using a lithographic method to form a horizontal stripe undulation on the resist side surface. The pattern of the horizontal stripes of the resist pattern is transferred to the electrode material to form the horizontal stripes of the sidewall. Method of forming a semiconductor memory device is characterized in that to include a transfer step of forming a storage node electrode for. 3. A MOSFET forming step of forming a MOSFET in a semiconductor substrate, said MOSF
An insulating film forming step of covering the upper and side walls of the ET gate electrode with an insulating film, and a polycrystalline silicon film forming step of forming a polycrystalline silicon film on the upper layer so as to cover at least the storage node contact region. A first film forming step of forming a first film made of a material having a glass transition temperature on the upper layer, and a first film forming step using the polycrystalline silicon film as an etching stopper.
A part of the film is selectively removed, and then the exposed portion of the polycrystalline silicon film is further etched to form a storage node contact, and a storage node contact forming step, and heating to a glass transition temperature of the first film or higher. A heating step of oxidizing the polycrystalline silicon film to form a silicon oxide film and melting the first film to round an edge; and covering the storage node contact and an upper edge of the first film. To form a storage node electrode so as to reach the storage node electrode, a first film etching step to remove the first film by etching, and a capacitor insulation to form a capacitor insulating film around the storage node electrode. A film forming step, and a plate electrode forming step of forming a plate electrode on the upper layer of the capacitor insulating film Method of manufacturing a semiconductor memory device which comprises a bit line forming step of forming an interlayer insulating film forming step and the interlayer insulating film a bit line contact are formed on the bit lines forming an interphase insulating film. 4. A MOSFET formation process for forming a MOSFET in a semiconductor substrate, and a storage node electrode and a capacitor insulation which are connected to a source or drain region of the MOSFET through a storage node contact. In a method of manufacturing a semiconductor memory device, including a capacitor forming step of laminating a capacitor including a film and a plate electrode, the storage node electrode forming step includes a multilayer film forming step of alternately laminating two kinds of films. A storage node contact forming step including a step of etching the multi-layered film under conditions such that two kinds of films have different etching rates to form a storage node contact having unevenness on a side wall; and an electrode material in the storage node contact. After forming, the multilayer film is removed and the pattern is transferred to form unevenness on the side wall. Method of forming a semiconductor memory device is characterized in that as a step of forming a storage node electrode having a protruding portion having.