JPH05205492A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To speedily and accurately perform an erasing by detecting generation of an overerasing during a memory cell erasing of a nonvolatile semiconductor storage device. CONSTITUTION:After executing an erasing operation, presence or absence of an overerasing is judged by reading memory cell information under the condition in which a word line connected to an X decoder 14 is made nonselective by a control signal OEV from a command port controller 30. That is, if data which are read out are OOH, no overerasing is generated. However, it is other than OOH value, it is judged that an overerasing is generated. By this scheme, it is easily confirmed whether there exists a memory cell which is overerased among all memory cells in a memory cell array 11 or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically erasable nonvolatile semiconductor memory device such as an electrically programmable and erasable read only memory device (EEPROM).
Particularly, it relates to the improvement of the erasing function.

[0002]

2. Description of the Related Art In a conventional electrically erasable non-volatile semiconductor memory device, all memory cells are sufficiently erased as described in JP-A-2-10596 and JP-A-2-10598. Whether or not it is determined whether or not the read operation is performed after the erase operation is performed. For example, in the flash memory described in Japanese Patent Application Laid-Open No. 2-10596, at the present time, the gate voltage of the memory transistor is set lower than the read voltage at the time of normal operation for reading, and it is the most difficult to erase in the memory. Erasing is generally performed while confirming whether or not the memory cells have been sufficiently erased.

In a flash memory or the like which is an electrically erasable non-volatile semiconductor device, generally, when electrically erasing stored information, electrons stored in a floating gate are extracted to a source electrode. , The stored information is erased. At this time, if the erase operation is continued for a relatively long time, more electrons will be extracted than the amount of electrons injected into the floating gate during the write operation. Therefore, when electrical erasing is continued for a relatively long time, the threshold voltage of the memory transistor changes to a negative voltage. Such erasure in which more electrons are extracted than in normal erasure is called excessive erasure.

As described above, various failures occur due to the negative threshold voltage of the memory transistor. For example, in a read operation, since the information stored in the memory cell is read, even if the voltage of the word line, that is, the voltage of the control gate of the memory transistor is set to 0V, even if the memory cell is in the non-selected state, If the threshold voltage of the memory transistor is negative, leak current flows through the non-selected memory transistor. Therefore, the read time is delayed, and erroneous read is caused.

In the write operation using hot carriers, a high voltage for writing applied from the outside is applied to the drain region of the memory transistor in the memory cell via the MOSFET. In such a write operation, under the condition that the threshold voltage of the memory transistor has a negative value, a large amount of current flows, and
The voltage drop in the SFET becomes too large, and the voltage applied to the drain of the memory transistor in the memory cell becomes lower accordingly. Therefore, the time required for writing is increased. The erasing method as described above is adopted in order to prevent excessive erasing which gives various adverse effects.

In the flash EEPROM disclosed in Japanese Patent Laid-Open No. 2-289997, the flash EEPROM itself automatically performs the above-mentioned erasing after entering the erasing mode by the control circuit built in the flash EEPROM. Have done, for example flash EE
The load on the microprocessor or the like for controlling the PROM is reduced. In this flash EEPROM, in order to prevent the problem that erasing does not end when there is an erasing defective memory cell, the control circuit is provided with a counter circuit for counting the number of times of erasing. , Is configured to terminate the erase mode.

[0007]

The conventional electrically erasable non-volatile semiconductor memory device is configured as described above, and it is determined whether or not excessive erasing has occurred during the erasing process for erasing. Since there is no means for inspecting, there is a problem in that even if over-erasing occurs, the erasing ends normally and various adverse effects due to over-erasing may occur.

Further, when a control circuit is provided in the flash memory to automatically perform erasing, it is necessary to provide a counter circuit, which causes a problem that the area occupied by the control circuit becomes large.

The present invention has been made to solve the above problems, and in the electrically erasable nonvolatile semiconductor memory device, all memory cells are sufficiently erased, and It is an object of the present invention to provide a non-volatile semiconductor memory device that can confirm that it has not been overerased.

Further, by providing a means for confirming excessive erasure, in order to prevent the problem that the erasing process does not end when there is an erasing defective memory, the counter circuit provided in the control circuit is conventionally used. The purpose is to reduce the occupied area of the control circuit.

[0011]

A non-volatile semiconductor memory device according to a first invention is a non-volatile semiconductor memory device in which a plurality of electrically erasable memory cells are arranged in an array. After performing the erasing operation, all the word lines are unselected, the reading operation is executed, and the over-erasing verify means for performing the over-erasing verification based on the read result of the reading operation is provided.

In the nonvolatile semiconductor memory device according to the second aspect of the present invention, when the erase mode is automatically executed in response to an erase command from the outside of the device, the overerase verify means causes the plurality of memory cells to be stored in the plurality of memory cells. It is further configured to further include erase control means for outputting a signal for stopping the erase mode when an overerased memory cell is detected.

The nonvolatile semiconductor memory device according to a third aspect of the present invention is further provided with an information output means for outputting at least information for transmitting the status of the over-erase verification in the erase mode to the outside.

A nonvolatile semiconductor memory device according to a fourth aspect of the invention is characterized in that a plurality of bit lines are simultaneously connected to a sense amplifier during the read operation.

[0015]

In the non-volatile semiconductor memory device according to the first aspect of the invention, in the over-erase verification, all word lines are unselected and read after performing the erase operation of the memory cells. Therefore, all memory cells are in the off state,
The data to be read is one fixed value, for example 00
H can be the expected value. However, if a memory cell including at least one over-erased memory transistor exists in the memory cell, a value different from the expected value is read due to the leak current from the memory transistor. From the above, it is possible to easily confirm whether or not the overerased memory cell exists in all the memory cells.

The erase control means in the second invention outputs a signal for stopping the erase mode when there is an overerased memory cell. The non-volatile semiconductor memory device can stop the erase mode according to the signal. For example, conventionally, it is not possible to confirm the presence or absence of overerased memory cells. Although a counter circuit that counts the number of erase operations is provided for the purpose of preventing the problem of not ending, it is not necessary to provide such a counter circuit.

Further, the information output means in the third aspect of the present invention outputs at least the information indicating the status of the over-erase verification to the outside through, for example, the data pin. Then, it is possible to know from the outside whether the erase mode is being executed, the erase mode has ended normally, or whether the erase mode has ended due to over-erase.

Further, in the non-volatile semiconductor memory device according to the fourth aspect of the present invention, in the over-erase verification, all the word lines are unselected after the erase operation of the memory cells is performed, and a plurality of bit lines are simultaneously connected to the sense amplifier. Read out. Therefore, all the memory cells are in the off state, and the read data can have one fixed value, for example, 00H as the expected value. However, if a memory cell including at least one over-erased memory transistor exists in the memory cell, a value different from the expected value is read due to the leak current from the memory transistor. Since a plurality of bit lines are simultaneously connected to the sense amplifier, if all the bit lines are simultaneously connected to the sense amplifier, it is possible to detect the presence / absence of overerasure by one read operation.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. 1 is a block diagram showing an outline of a flash memory device according to a first embodiment of the present invention. In the figure, 10 is a flash EEPROM
M and 12 are address buses for transmitting address data A _{0 to} A ₁₄ , 13 is an address latch for holding address data A _{0 to} A ₁₄ transmitted by the address bus 12, 1
Reference numerals 3 and 14 are X for decoding the address data A _{0 to} A _14.
And a Y decoder, 16 a Y gating circuit connected to the Y decoder 14, 11 a memory cell array connected to the X decoder 13 and the Y gating circuit 16, 20 a bidirectional data bus for transmitting data D _{0 to} D ₇ , Reference numeral 21 is an input / output buffer connected to the bidirectional data bus 20, 22 is input data D _{0 to} D ₇ , and the data D _{0 to} D is stored in the memory cell array 11 via the Y gating circuit 16.
Data latch for outputting ₇ , 23a for input / output buffer 2
1 is a bus for transmitting data D _{0 to} D ₇ to the data latch 22 and the like, 23b is a bus for outputting the data stored in the memory cell array 11 from the Y gating circuit 16, 10
Reference numeral 1 is a sense circuit for detecting the data output through the bus 23b and outputting it to the input / output buffer 21, 30 is a command port controller for receiving external signals / WE, / CE and generating an internal control signal, and 27 is an external signal / A chip / output enable logic circuit that receives CE and / OE to supply an internal control signal to the input / output buffer 21, 24 is an erase voltage generator that generates a voltage for simultaneously erasing the memory cell array 11, and 25 is X and Y. A program voltage generator that supplies a program voltage to the memory cell array 11 via the decoders 13 and 14, and an erase / program verify generator 26 that supplies a verify voltage to the memory cell array 11 when the erase / program verify function is selected. Yes, voltage V _CC to flash EEPROM10 from the outside, V _SS, V _PP is It has been fed.

Erasing and programming of the memory cell array 11 are performed by receiving commands via the data bus 20. When the chip enable signal / CE is "L", the flash EEPROM 10 receives a command via the data bus 20, and this command is transmitted to the command port controller 30 via the input / output buffer 21. When the command port controller 30 receives a command such as program, program verify, erase, erase verify, and read, it operates the flash EEPRO in accordance with the command.
Generate internal control instructions for M to execute. After a specific command is input to the command port controller 30, the write enable signal / WE, the chip enable signal / CE
And output enable signal / OE control command port controller 30 and chip / output enable logic circuit 27 to generate the appropriate internal control signals for operating flash EEPROM 30.

FIG. 2 is a block diagram showing an outline of the command port controller 30 shown in FIG. In the figure,
Reference numeral 30 is a command port controller, 31 is a control logic for giving a write enable signal / WE to an internal circuit of the command port controller 30 based on the chip enable signal / CE, 32 is an external signal / WE, / CE and an output from the state decoder. An address clock generator 33 which receives and outputs a strobe signal STB to the address latch 13.
Is a status clock generator that receives the output CWE of the control logic 31 as input, 35 is a status register that receives the data from the data bus 23a, the output of the status clock generator 33 and the output from the status decoder, and 34a is the status register 35. And a command clock generator that receives the output of the control logic 31 as an input, 34b is a data clock generator that receives the output CWE of the control logic and outputs a strobe signal STB to the data latch 22, and 37 is the data of the data bus 23a and the command clock. Command register 3 with the output of generator 34a as input
Reference numerals 7 and 36 denote status decoders which receive the outputs of the status register 35 and the command register 37 and output control signals to the erase voltage generator 24, the program voltage generator 25, the erase / program verify generator 26, the X decoder 14 and the like. is there. The control signal output from the state decoder 36 is the voltage V _{PP supplied} from the erase voltage generator 24, the program voltage generator 25 and the erase / program verify generator 26 to the X decoder 14, the Y decoder 15 or the memory cell array 1.
1 or the test voltage _derived from the voltage V _PP is applied to the word line through the X decoder 14 during the program test and the erase test. Further, at the time of over-erase verification, the control signal OEV for deselecting all the outputs of the X decoder 14 changes from the state decoder 36 to the X decoder 1.
4 is output.

In this embodiment, the state decoder 36 controls the X decoder 14 by way of example.
It is also possible to deselect all the outputs of the X decoder 14 by using a method of deselecting all the outputs of the address latch 13 without directly controlling the decoder 14.

Next, the erasing process will be described with reference to FIG. In order to start erasing in the erasing mode, first the voltage V
_PP is applied and all bytes are programmed with 00H. Then, the erase count counter is set to 0, and the address to the device is set to the head address. The erase setup command is then written. Then, the erase command is written. As a result, an erase pulse is generated inside the flash EEPROM 10 and the erase operation is executed. Next, an overerase verify command is written, read out, and it is determined whether or not overerase is performed. At this time, since all the word lines are unselected in the X decoder 14, all the memory cells are turned off, and if over-erasing has not occurred,
00H is read as data.

However, when over-erasing occurs due to the erase operation, even the non-selected memory cells are turned on, so that the read data contains "1". Therefore, the read data is data other than 00H.
In this case, the erase mode is terminated because it is determined that there is an erase failure due to the occurrence of excessive erase.

When the erase operation is not over-erased,
If the read data is 00H, the erase verify command is input, the erase verify is executed after a waiting time, and it is determined whether or not the data has been erased. If the data has not been erased, the count number of the counter is increased and erased again, and the same operation as above is performed. If the data has been erased, after judging whether it is the last address or not, if it is not the last address, proceed to the next address,
Input the over-erase verify command and repeat the subsequent operations. If it is the last address, a read command is input to end the erase mode. Further, when the count number of the counter exceeds 1000, it is determined that the erasing is defective and the erasing mode is ended.

As described above, by performing the over-erase verification, it is possible to detect the occurrence of the over-erase due to the erasing immediately after the erasing without performing the subsequent programming, and the completion of the erasing can be judged quickly and completely as compared with the conventional method. can do.

Next, the second embodiment of the present invention will be described with reference to FIG.
It will be described with reference to FIGS. FIG. 4 is a block diagram showing the structure of a flash EEPROM according to the second embodiment of the present invention. Although only one set of the memory cell array, the sense amplifier, the input / output buffer and the like are shown in this figure, it is assumed that eight similar units are provided. In the figure, 40 is a memory cell array M-ARY, Q1 to Q6.
Is a memory transistor, D1 to Dn are data lines connected to the drain regions of the memory transistors Q1 to Q6, W
1, W2 are word lines connected to the control gates of the memory transistors Q1 to Q6, CS is a source line connected to the source regions of the memory transistors Q1 to Q6, and Q.
7 to Q9 are column selection switches configured by using MOSFETs, CD is a common data line connected to the data lines D1 to Dn via the column selection switches Q7 to Q9, 48
Is a data input buffer DIB for connecting the data input from the external input terminal I / O to the common data line CD via the switch transistor Q10, SA is a sense amplifier connected to the common data line CD via the switch transistor Q16, and Q11 To Q15 are MOSFETs forming the sense amplifier SA, N1 and N2 are inverters forming the sense amplifier SA, and 47 is a data output buffer DO for connecting the output of the sense amplifier SA to the input / output terminal I / O.
B and 43 are row address buffers XADB which receive the row address signal AX supplied from the external input terminal and form and output internal complementary row address signals. A row decoder XDCR, 44 for selecting the word lines W1, W2 by receiving the column address signal AY supplied from an external input terminal, forms an internal complementary column address signal and outputs the column address buffer YAD.
B and 42 are column decoders YDCR that output signals for selectively turning on / off the column selection switches Q7 to Q9 in accordance with the internal complementary column address signals output from the column address buffer YADB 44, and 45 is an N channel MOS.
An erase circuit ERC in which an output is connected to the gates of a FET Q18 and a P-channel MOSFET Q17, which is an N-channel MOSF in the write mode and the read mode.
It functions to turn on ETQ18 and output the voltage V _PP to the source line CS. Reference numeral 49 is an internal circuit LOGC for performing an automatic erase control operation. 46 is an external signal / CE,
/ OE, / WE, / EE and voltage V _PP and internal circuit LOG
Timing control circuit CN for generating internal control signals including internal control signals wr, re, etc. in response to a signal from C49.
TR. The signal OEV output from the internal circuit LOGC49 is an overerase verify control signal. The flash EEPROM shown here is characterized by performing automatic erasing especially after entering the erasing mode. The reading and writing operations of this flash EEPROM are the same as those known in the prior art.

First, at the time of reading the data stored in the memory cell, the operation timing signal / sc of the sense amplifier SA is set to "L". As a result, MOSFETQ
14 turns on and MOSFET Q15 turns off. Then, the memory transistor that constitutes the memory cell is
It has a high threshold voltage or a low threshold voltage with respect to the selected level of the word line depending on the stored data. The common data line CD is "H" when the selected memory cell is in the off state, while the common data line CD is "L" when the selected memory cell is in the on state. The sense amplifier SA transmits the information of the memory cell output via the data line CD to the data output buffer DOB47 and outputs it from the input / output terminal I / O.

Next, in the write operation, the control gate of the selected memory cell is connected and the word line W1 or W2 becomes a high voltage according to the voltage V _PP by the row decoder XDCR41. In addition, the data lines D1 to D
The selected data line of n is set to a high voltage according to the information to be written, and electrons are injected into the floating gate of the memory transistor forming the selected memory cell to increase the threshold voltage of the memory transistor.
The data line remains at a low voltage and electrons are not injected into the floating gate of the memory transistor, and the threshold voltage of the memory transistor is low. The memory transistor whose electrons have been injected into the floating gate and whose threshold voltage has become high remains in a non-conductive state even when a selection signal is supplied to the control gate during a read operation. On the other hand, the memory transistor to which the electron injection has not been performed has a low threshold voltage, so that the selection signal is supplied to the word line to bring the memory transistor into a conductive state and a current flows.

Next, the erasing method will be described with reference to FIG. First, the pre-write operation is performed prior to the erase operation. In the memory cell array M-ARY40 before erasing,
Since various information is written, the threshold voltage of the memory transistor is in a mixed state of high and low. Therefore, in order to prevent the threshold voltage of the memory transistors from becoming negative in the batch erasing operation, it is necessary to write to all the memory transistors in advance. The write operation for that is the pre-write operation.

In the erase mode, first, an address is set. That is, the address signal is the internal circuit LOGC4.
The address counter is set so that it is generated from the address counter circuit in 9. In the next step, a write pulse is generated and writing is performed on the memory cell selected by the address signal generated by the address counter circuit. In the next step, the address is incremented by one (address increment), and preparation for writing to the next address is made. In the next step, it is judged whether or not the pre-write has been performed up to the final address. If it is not the final address, the writing is continued by the above procedure, and if it is the final address, the erase operation of the next step is performed.

In the next step, the address is initialized for the erase operation. In the next step, an erase pulse for collective erase is generated and an erase operation is performed.
In the next step, it is checked whether or not over-erase has been performed (over-erase verify). This is performed by performing the read operation in the state where all the word lines are deselected by the control signal OEV generated from the internal circuit LOGC49. Here, if over-erasing has occurred, the erase mode is stopped. If over-erasure has not occurred, proceed to the next step.

In the next step, an erase verify operation is performed. In the erase verify operation, the read operation is performed under a voltage whose operating voltage is lower than the power supply voltage V _CC supplied from the external terminal (for example, operating voltage 3.5 V when the power supply voltage V _CC is 5 V). That is, the address decoder X
The operating voltage is supplied to the DCR41, YDCR42 and the sense amplifier SA, and the power supply voltage V _CC is supplied to the internal control circuit LOGC49 and the timing control circuit CNTR for its operation. If the signal read in the erase verify operation is "0", it is determined that the threshold voltage of the memory transistor is in the erase state below the operating voltage, and the process proceeds to the next step. If the voltage read at this time is "1", the erase operation is executed again and the operation after the erase operation is repeated.

In the next step, the address of the address counter circuit is incremented. Then, in the next step, it is judged whether or not the erase verify has been performed up to the final address. If it is not the final address, the erase verify is continued by the above procedure, and if it is the final address, the erase mode is ended.

Next, the operation of the internal circuit LOGC49 for automatically erasing will be described with reference to FIGS. The operation up to the end of the pre-write operation is conventionally known, so the details are omitted and the operation after application of the erase pulse will be described.

First, the erase pulse / EP becomes "H",
The erase verify signal EV becomes "H". This allows
The counter circuit BCS2 shown in FIG. 6D operates.
The counter circuit BCS2 is used to generate verify internal address signals AXI and AYI.
At this time, the counter circuit BCS1 shown in FIG.
The period in which the output signal OS1 is low is used for the erase verify and overerase verify cycles. This 2
The type cycle is further set by using the output signal OS2 of the counter circuit BCS1 as shown in FIG. That is, as shown in FIG. 7, the signal OS1 is "L",
During the period when the signal OS2 is "H", the overerase verify control signal OEV becomes "H", and the overerase verify cycle starts. Further, the signal OS2N shown in FIG. 5C becomes "H" while the signal OS1 is "L" and the signal OS2 is "L", and the erase verify cycle is started.

Then, in the overerase verify cycle, the overerase verify control signal OEV is "H", and the data of the outputs S _{0 to} S ₇ of the sense amplifier SA are shown in FIG.
Each of them is input to the two 4-input NAND gates in (d),
It is determined whether all the outputs S _{0 to} S ₇ of the sense amplifier SA are “1” (that is, whether all the data in the memory cell are “0”). At this time, the row decoder is deselected by the overerase verify control signal OEV, and the potentials of all word lines are set to 0V. Outputs S _{0 to} S of the sense amplifier SA
_If even one of the data ₇ contains "1", it is considered that over-erasure has occurred, the signal VOUT2 shown in FIG. 5D becomes "H", and the signal OEF becomes "H". Becomes As a result, the signal ER shown in FIG. 5B becomes "H", and the automatic erasing ends. And the sense amplifier SA
If the outputs S _{0 to} S ₇ of the counter circuit BCS1 are all “0”, the signal OEF remains “L” and the output OS of the counter circuit BCS1 is
1 is "H", OS2 is "L", and the over-erase cycle ends. Then, the signal OS2N becomes "H" to start the erase verify cycle.

As described above, by performing the overerase verify and the erase verify in the automatic erase, it is possible to confirm the completion of the erase and the confirmation that the overerase has not occurred. Further, if erasing is incomplete, erasing will be repeated many times, but in this case, overerasing will inevitably occur. Therefore, it is necessary to provide a counter for counting the number of times of erasing, which was conventionally necessary. Without internal control circuit LO
The area occupied by the GC 49 can be reduced.

Next, a third embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the erasing status could not be monitored from the outside.
The purpose of this embodiment is to know the erasing status from the outside. FIG. 9 shows the internal control circuit LOGC shown in FIG.
It is a figure which shows a part of circuit of 49. FIG. 9A shows FIG.
FIG. 9B is a circuit obtained by improving the circuit shown in FIG. 9D.
This is an improved circuit of the circuit of (b). The other structure of the internal control circuit LOGC49 according to this embodiment is similar to that of the second embodiment. FIG. 10 shows a part of the internal circuit of the timing control circuit CNTR. This has the same configuration as the timing control circuit CNTR46 shown in the second embodiment. Next, FIG. 11 shows the data output buffer DOB4 in FIG.
7 is an internal circuit diagram of FIG. FIG. 9A shows a circuit configuration for latching and detecting the signal OEF when the signal OEF outputs "H" and the erasing is stopped when the over-erase verification occurs. Further, in FIG. 11, the data polling control signal / P output from the timing control circuit CNTR46 is shown.
2 shows a circuit configuration for outputting information for transmitting an erasing status via a data pin to the outside when the OLM enters a data polling mode.

Next, the operation of this circuit will be described.
When the external signals / CE, / OE, / EE are "L", the external signal / WE is applied, and the voltage V _PP is applied, the data polling mode is set and the data polling control signal /
The POLM becomes "L". Therefore, as shown in FIG. 10, the signal DO7 becomes "H" and the signal / DO becomes "H",
The complementary signal DO becomes "L". Therefore, FIG.
By the circuit DP surrounded by a dotted line shown in (b), it is output from the input / output terminal I / O7 whether or not it is in the erased state, and the input / output terminal I / O6 outputs whether or not the erase is normal. It

As described above, for example, by setting the data polling mode after erasing and reading the data from the input / output terminal I / O, it is possible to easily determine whether or not the device is an erasing defective device.

Next, a fourth embodiment will be described with reference to FIGS. FIG. 12 is a block diagram showing the outline of a flash memory device according to the fourth embodiment of the present invention. FIG. 13 is a block diagram showing an outline of the command port controller 30 shown in FIG. The difference between the fourth embodiment and the first embodiment is that, as shown in FIG.
The control signal OEV is output to the gating circuit 16 so that all the bit lines are sensed by the sense circuit 101 during overerase verification.
It is connected to.

Next, the operation will be described. FIG. 14 is a flowchart showing the operation of the flash memory device shown in FIG. The difference of the fourth embodiment from the operation of the first embodiment is that the control signal OEV is set to "H" by the state decoder when the over-erase verify command is input after the erase operation is executed. As a result, the X decoder 1
4 is deactivated and all word lines are grounded. On the other hand, since the control signal OEV is also input to the Y gating circuit 16 and the control signal OEV becomes “H”,
"H" is input to all the Y gates and a plurality of bit lines are simultaneously connected to the sense circuit 101. Therefore, if even one memory cell on the bit line connected to the sense circuit 101 is over-erased, a current flows through the memory cell and is detected by the sense circuit 101. in this way,
Occurrence of over-erasure is detected (read data is 00H
Any other value. ) And the erasing mode is canceled as erasing failure.

If the data is 00H in the above step,
Excessive erasure has not occurred, and the process proceeds to the next step to input the erase verify command. Then, after a waiting time, the erase verify is executed to determine whether or not the erase has been performed. If the data has not been erased, the count number of the counter is increased and erased again, and the same operation as above is performed. If the data has been erased, it is judged whether or not it is the last address, and if it is not the last address, the process proceeds to the next address, the erase verify command is input, and the subsequent operation is repeated. If it is the last address, a read command is input to end the erasing. Further, when the count number of the counter exceeds 1000, it is determined that the erasing is defective and the erasing mode is ended.

As described above, in the erasing method of the fourth embodiment, since the overerasing of all the memory cells is judged at once,
It is not necessary to perform the overerase verify for each byte as in the embodiment, and the number of cycles of the overerase verify (or
Verify time) can be shortened.

[0046]

As described above, according to the nonvolatile semiconductor memory device in accordance with the first aspect of the present invention, after the erase operation of the memory cells is performed, all the word lines are deselected and the read operation is performed. As a result, over-erase verification is performed, so that it is possible to easily confirm whether or not there is an over-erased memory cell in all the memory cells. There is an effect that it can be detected immediately after erasing without performing. Further, there is an effect that the completion of the erasing can be judged faster and completely than the conventional one.

According to the second aspect of the nonvolatile semiconductor memory device of the present invention, when there is an overerased memory cell among the memory cells, the erase mode is stopped based on the read result of the read operation. For example, since it is not possible to confirm the existence of overerased memory cells in the related art, the erase mode does not end when there are defective erased memory cells. A counter circuit for counting the number of erase operations has been provided for the purpose of preventing the problem, but it is not necessary to provide such a counter circuit, and there is an effect that the area occupied by the control circuit can be reduced.

Further, according to the third aspect of the present invention, the nonvolatile semiconductor memory device is provided with the information output means for outputting at least the information indicating the status of the overerase verification to the outside, and the erase mode is set. It is possible to know from the outside whether it is in the middle of being executed, the erase mode has ended normally, or whether the erase mode has ended due to over-erase, and it is easy to determine whether or not the device is defective. The effect is that it can be done.

Further, the non-volatile semiconductor memory device according to claim 4 of the present invention is configured such that a plurality of bit lines are simultaneously connected to the sense amplifier during a read operation, and the erase operation of the memory cell is performed in the overerase verify. After that, all the word lines are made non-selected and a plurality of bit lines are simultaneously connected to the sense amplifier for reading. For example, if all bit lines are connected to the sense amplifier at the same time
The presence or absence of over-erase can be detected by one read operation, and it is not necessary to perform the over-erase verification for each byte, and there is an effect that the number of cycles (or the verify time) of the over-erase verify can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a flash memory device according to a first embodiment of the present invention.

2 is a block diagram showing a command port controller which constitutes the flash memory device shown in FIG. 1. FIG.

FIG. 3 is a diagram showing an erase process of a flash memory device according to a first embodiment of the present invention.

FIG. 4 is a flash EEP according to a second embodiment of the present invention.
It is a block diagram which shows the structure of ROM.

5 is a circuit diagram of an internal control circuit LOGC of the flash EEPROM shown in FIG.

6 is a circuit diagram of an internal control circuit LOGC of the flash EEPROM shown in FIG.

FIG. 7 is a flash EEP according to a second embodiment of the present invention.
FIG. 6 is an operation waveform diagram showing a ROM erasing process.

FIG. 8 is a flash EEP according to a second embodiment of the present invention.
It is a figure which shows the erasing process of ROM.

FIG. 9 is a flash EEP according to a third embodiment of the present invention.
It is a circuit diagram showing a part of internal control circuit LOGC of ROM.

FIG. 10 shows a flash EE according to a third embodiment of the present invention.
It is a circuit diagram showing a part of timing control circuit CNTR of PROM.

FIG. 11 is a flash EE according to a third embodiment of the present invention.
It is a circuit diagram which shows a part of data output buffer DOB of PROM.

FIG. 12 is a block diagram showing a configuration of a flash memory device according to a fourth embodiment of the present invention.

13 is a block diagram showing a command port controller which constitutes the flash memory device shown in FIG. 12. FIG.

FIG. 14 is a diagram showing an erase process of a flash memory device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 10 Flash EEPROM 11 Memory Cell Array 14 X Decoder 15 Y Decoder 16 Y Gating Circuit 30 Command Port Controller 36 State Decoder 40 Memory Cell Array M-ARY 41 Row Decoder XDCR 42 Column Decoder YDCR 43 Row Address Buffer XADB 44 Column Address Buffer YADB 46 Timing Control circuit CNTR 47 Data output buffer DOB 48 Data input buffer DIB 49 Internal control circuit LOGC

Claims (4)

[Claims] 1. A non-volatile semiconductor memory device having a plurality of electrically erasable memory cells arranged in an array, wherein all the word lines are deselected and read after performing the erasing operation of the memory cells. A non-volatile semiconductor memory device comprising: an over-erase verify means for executing an operation and performing an over-erase verify based on a read result of the read operation. 2. When the overerased verifying means detects an overerased memory cell among a plurality of the memory cells when the erase mode is automatically executed in response to an erase command from the outside of the device. 2. The nonvolatile semiconductor memory device according to claim 1, further comprising erase control means for outputting a signal for canceling the erase mode. 3. The non-volatile semiconductor memory device according to claim 2, further comprising an information output means for outputting at least information for transmitting the status of the over-erase verification in the erase mode to the outside. 4. The non-volatile semiconductor memory device according to claim 1, wherein a plurality of bit lines are simultaneously connected to a sense amplifier during the read operation.