JPH05205488A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the voltage of a write power supply and a power consumption in a nonvolatile semiconductor storage device capable of data erasing and rewriting. CONSTITUTION:In an EPROM, bit lines BL are connected to a high voltage write power supply VPP through respective bit line selection gate transistors 13 which consist of MOS transistors, a write control gate transistor 12 and a write power supply gate transistor 11. Among the transistors 11 to 13, at least one of the transistors 11 to 13 is arranged so that a back gate voltage is applied to the well which constitutes the back gate so that the back gate becomes a zero bias against the gate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of erasing and rewriting data.

In recent years, it has been required to lower the power supply voltage applied to the bit lines during the writing (programming) operation of the EPROM and the EEPROM.

[0003]

Conventional P 6 ^- form substrate formed E
The principal circuit of PROM is shown. The EPROM cell 51 is composed of an NMOS transistor having a double gate structure of a floating gate and a control gate, and the potential of the floating gate is controlled by the control gate by capacitance coupling.

At the drain of each EPROM cell 51, a power supply gate 52, a write control gate 53 and a bit line selection gate 54 which are enhancement type N channel MOS transistors each having a back gate (P well) grounded. The writing power source is supplied from the high voltage power source VPP (voltage is about 12V) via the. The source of each EPROM cell 51 is grounded.

The bit line selection gate 54 is connected to the bit line decoder 55 via the bit line BL, and the control gate of the EPROM cell 51 is connected to the word line decoder 56 via the word line WL. A power supply switching signal of H level or L level is input to the power supply gate 52 from a control device (not shown), and an input signal of H level or L level (write data) is also input to the write control gate 53 from the control device. Is input via a buffer 57 having a CMOS structure.

The writing operation of this EPROM is performed as follows. For example, when writing data to the EPROM cell 51a, the word line decoder 56 uses the EPRO
Select the word line WL of the M cell 51a, and
A high voltage is applied to the control gate of the cell 51a.
Then, the voltage induced in the floating gate of the EPROM cell 51a becomes a sufficient level to form a channel, and the EPROM cell 51a is turned on.

The bit line decoder 55 selects the bit line selection gate 54a corresponding to the bit line BL of the EPROM cell 51a, and turns on the bit line selection gate 54a. Further, an H-level power supply switching signal is input from the control device to the power supply gate 52, and the power supply gate 52 is turned on. When L level write data is input to the buffer 57 from the control device, the write control gate 53 is turned on, and a high voltage is applied from the high voltage power supply VPP to the drain of the EPROM cell 51a. Then EPROM
A large current flows through the channel of the cell 51a, channel electrons having high energy near the drain pass over the barrier of the gate oxide film, and are injected into the floating gate.
The threshold voltage of the EPROM cell 51a changes to "0".
It becomes a state. Further, when H level write data is input to the buffer 57 from the control device, the write control gate is turned off and no voltage is applied to the drain of the EPROM cell 51a. Then, the EPROM cell 51
No electrons are injected into the floating gate of a, and EP
The ROM cell 51a is in the "1" state.

As described above, the write operation is performed by applying the high voltage to the control gate of the EPROM cell and then changing the voltage applied to the drain. Note that the latch-up prevention NMOS transistor 5
The source of No. 8 is connected to the source of the power supply gate 52. Also, an enhancement type N channel MOS
The drain and gate of the transistor 58 are both connected to the power supply Vcc. Therefore, the NMOS transistor 58
Is turned on when the voltage of the high-voltage power supply VPP is lower than the power supply VCC, and turned off when the voltage of the high-voltage power supply VPP is higher than the power supply VCC. In this way, the high voltage power supply VPP
To EPROM cell 51 when back gate bias (substrate bias) is not applied from power supply VCC to EP
The back gate bias is applied to the ROM cell 51 to prevent the EPROM cell 51 from latching up.

[0009]

By the way, the threshold voltage of the MOS transistor changes due to the back gate bias.

[0010] In other words, the back gate P is grounded to the ground ^- in the NMOS transistor connected to form the substrate,
The back gate bias to the gate of the NMOS transistor increases, the depletion layer of the back gate expands, the number of ionized donors increases, and an extra gate electric field is required to induce the same amount of channel charge. Value voltage increases. When the threshold voltage of the MOS transistor increases, the on-resistance also increases. Therefore, as shown in FIG. 7, in the NMOS transistor in which the back gate is grounded to the ground and is resistance-connected, the drain voltage is significantly lower than the source voltage due to the increase in the on-resistance.

Therefore, the power supply gate 52, the write control gate 53, and the bit line selection gate 54.
The voltage drop between the source and drain of each becomes large. As a result, when writing data to the EPROM 51 with the high voltage power supply VPP, there is a problem that the voltage of the high voltage power supply VPP must be increased by the amount of the voltage drop. Also, E
Since a large current flows through the bit line BL at the time of writing in the PROM, there is also a problem that the power consumption increases due to the high on-resistance of each of the gates 52 to 54.

The present invention has been made to solve the above problems, and an object of the present invention is to reduce the voltage of the power supply for writing and the power consumption.
A non-volatile semiconductor memory device capable of erasing and rewriting data is provided.

[0013]

In a non-volatile semiconductor memory device in which a memory cell array is composed of a large number of non-volatile cell transistors capable of erasing and rewriting data, each bit line is composed of a MOS transistor. , And is connected to a high-voltage write power supply via a write control gate transistor and a write power supply gate transistor.

At least one of the gate transistors applies a back gate voltage to the well forming the back gate so that the back gate has zero bias with respect to the gate.

[0015]

Therefore, according to the present invention, the back gate bias is applied so that the well is zero-biased, so that the threshold voltage of the gate transistor composed of the MOS transistor is reduced, and the voltage drop between the source and the drain is extremely reduced. Becomes smaller. As a result, the voltage of the power supply for writing does not need to be higher than the level required for writing to the memory cell, and the power supply voltage can be lowered. Further, since the on resistance of the gate is reduced, power consumption can be reduced.

[0016]

EXAMPLE An EPR of an example embodying the present invention will be described below.
The OM will be described with reference to FIGS.

In this embodiment, the same components as those in the conventional example shown in FIG. 6 are designated by the same reference numerals and detailed description thereof will be omitted. As shown in FIG. 1, a power supply gate 1
1, the write control gate 12 and the bit line selection gate 13 are connected from the source to the back gate (N
(Well) with a back gate bias applied to the enhancement type P-channel MOS transistor.

The structure of each of the gates 11 to 13 is shown in FIG.
As shown in the cross-sectional view, P^-N on the shaped substrate 21^-Shape area
(N well) 22 is formed, and the surface of the N well 22 is formed.
To P ⁺Shaped source region 23s and drain region 23d
Are formed so as to sandwich the channel 24. That channel
The surface of 24 is a silicon oxide film (SiO 2₂) 25 covered,
Gate made of aluminum film on the silicon oxide film 25
The electrode 26 is formed to form a MOS structure. Also,
N on the surface of the N well 22⁺-Shaped charge injection region 27 is formed
The charge injection region 27 and the source region 23s are shown in the figure.
Not connected by aluminum wiring. And so
The source region 23s and the drain region 23d are respectively
Connected to source and drain electrodes not shown
There is.

Therefore, the N well 22 and the source region 23s
Are equalized and the back gate (N well 22) is zero-biased. Therefore, the back gate bias is reduced, the depletion layer of the back gate is narrowed, the number of ionized acceptors is reduced, an extra gate electric field is not required to induce the same amount of channel charge, and the threshold voltage is reduced. When the threshold voltage of the MOS transistor decreases, the on-resistance also decreases. Therefore, as shown in FIG. 8, the back gate is zero-biased and resistance-connected P
In the MOS transistor, since the on-resistance is small, the drain voltage and the source voltage are almost at the same level.

As described above, since there is almost no voltage drop between the source and drain of the power supply gate 11, the write control gate 12 and the bit line selection gate 13, the voltage of the high voltage power supply VPP is the EPROM cell 31.
The level required for writing is sufficient and can be made lower than the conventional example. Further, since the on resistance of each of the gates 11 to 13 becomes small, the power consumption can be made small.

The writing operation of the EPROM in this embodiment is omitted because the levels of the power supply switching signal and the write data input from the control device (not shown) are only inverted from those in the conventional example.

Since the power supply gate 11 is a PMOS transistor, it is an NMOS for preventing latch-up.
A power supply switching signal is input to the gate of the transistor 58 from a control device (not shown). Therefore, when the power supply switching signal is at the H level and the power supply gate 11 is in the off state, the NMOS transistor 58 is in the on state.
That is, when the back gate bias is not applied to the EPROM cell 51 from the high voltage power supply VPP, the power supply VCC
By applying a back gate bias to the EPROM cell 51, the latch-up of the EPROM cell 51 is prevented.

The present invention is not limited to the above embodiment, but may be carried out as follows. 1) Each of the gates 11 to 13 is an NM in which a back gate bias is applied to the back gate (P well) from the source.
It may be an OS transistor. That is, as shown in the sectional view of FIG. 3, an N ⁻ -type region 31 is formed on the P ⁻ -type substrate 21.
And a P ^{− type} region (P well) 32 is formed on the N ^{− type} region 22. Therefore, the P ^{− type} substrate 21 and the P well 32 are junction-separated by the N ^{− type} region 22. P
An N ^{+ type} source region 33s and a drain region 33d are formed on the surface of the well 32 with the channel 34 interposed therebetween. The surface of the channel 34 is covered with a silicon oxide film (SiO ₂ ) 25, and a gate electrode 26 made of an aluminum film is formed on the silicon oxide film 25. Further, a P ^{+ -type} charge injection region 35 is formed on the surface of the P well 32, and the charge injection region 35 and the drain region 33d are connected by an aluminum wiring (not shown). Then, the source region 33s and the drain region 33d are connected to a source electrode and a drain electrode (not shown), respectively. Also in this case, the threshold voltage can be reduced by controlling the back gate bias of the NMOS transistor as in the case of the above-described embodiment, and the voltage drop between the source and drain of each of the gates 11 to 13 is almost eliminated, and the on-state is turned on. The resistance decreases.

2) As shown in FIG. 4, a high voltage power supply V is applied to the back gates of the write control gate 12 and the bit line selection gate 13 which are PMOS transistors.
The back gate bias may be applied directly from PP.

3) Since there is almost no voltage drop between the drain and source of each of the gates 11 to 13, as shown in FIG. 5, the power supply gate 1 composed of a PMOS transistor is used.
A back gate bias may be applied to the 1 and the write control gate 12 from the drain.

4) A back gate bias may be applied to any one of the gates 11 to 13. 5) Not only EPROM but also EEPROM may be used for writing.

[0027]

As described above in detail, according to the present invention, in the nonvolatile semiconductor memory device capable of erasing and rewriting data, it is possible to reduce the voltage of the writing power source and the power consumption. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of an EPROM that embodies an embodiment of the present invention.

FIG. 2 is a sectional view of each gate transistor of the present invention.

FIG. 3 is a cross-sectional view of each gate transistor of the present invention.

FIG. 4 is a circuit diagram of an essential part of an EPROM embodying another embodiment of the present invention.

FIG. 5 is a circuit diagram of a main part of an EPROM that embodies another embodiment of the present invention.

FIG. 6 is a circuit diagram of a main part of a conventional EPROM.

FIG. 7 is a characteristic diagram showing a drain voltage and a source voltage of a resistance-connected NMOS transistor.

FIG. 8 is a characteristic diagram showing a drain voltage and a source voltage of a resistance-connected PMOS transistor.

[Explanation of symbols]

11 Write Power Supply Gate Transistor 12 Write Control Gate Transistor 13 Bit Line Select Gate Transistor 51, 51a EP as Nonvolatile Cell Transistor
ROM cell BL Bit line VPP High voltage write power supply

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/792 H01L 29/78 371

Claims (3)

[Claims] 1. A MOS for selecting a bit line (BL) of a memory cell array composed of a large number of nonvolatile cell transistors (51, 51a) capable of erasing and rewriting data.
A bit line selection gate transistor (13) composed of a transistor, and a non-volatile cell transistor (51, 51a) selected through the bit line selection gate transistor (13).
A write control gate transistor (12) composed of a MOS transistor for supplying write data to the non-volatile cell transistor (51a) selected via the bit line selection gate transistor (13) and the write control gate transistor (12). A non-volatile semiconductor memory device comprising a write power supply gate transistor (11) comprising a MOS transistor for supplying a high voltage write power supply (VPP), wherein each gate transistor (11, 12, 13) comprising the MOS transistor is provided. Of at least one gate transistor, the back gate voltage is applied to the well such that the well forming the back gate has zero bias with respect to the gate transistor. Semiconductor memory device. 2. A non-volatile semiconductor memory device is formed on a P-type semiconductor substrate, and a write control gate transistor (1
2), the write power supply gate transistor (11) and the write power supply gate transistor (11) are P-channel MOS transistors.
And a source voltage, a drain voltage or a high voltage write power supply (VPP) is applied as a back gate voltage to the N-type well region formed on the N-type semiconductor substrate. Claim 1
Non-volatile semiconductor memory device. 3. A non-volatile semiconductor memory device is formed on a P-type semiconductor substrate, and a write control gate transistor (1
2) The write power supply gate transistor (11) and the write power supply gate transistor (11) are N-channel MOS transistors, and the transistors are P
A P-type well region electrically isolated from the N-type region of the N-type semiconductor substrate is formed, and a drain voltage is applied as a back gate voltage to the P-type well region. Item 1. A non-volatile semiconductor memory device according to item 1.