JPH05204701A - System debugging method - Google Patents

Abstract

PURPOSE:To provide the system debugging method which can easily and early develop/debug a loaded system with a new microprocessor and further can debug it at the highest operating speed of the microprocessor. CONSTITUTION:A system bus arbiter circuit 17, which ON/OFF can be controlled by an external control signal, is provided so as to easily execute system debugging only by connecting an extended board 32 for memory register access to an existent computer 31 and since the case of accessing a target system 1 from a test system 2 can be completely separated from the case of fetching and executing an instruction by a microprocessor 1 in the target system 1, the frequency can be independently set as well. Further, since any excess delay is not generated, a high-speed operation is enabled in the case of executing a program in the target system 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system debugging method for debugging a system equipped with a microprocessor.

[0002]

2. Description of the Related Art As a conventional system debugging method,
For example, “To cope with changes in microcomputer development environment, improved chip performance and software scale,” Nikkei Electronics, 1
989.9.9.4, No 481, pp 99-118.

An example of the conventional system debugging method described above will be described below with reference to the drawings.

FIG. 4 shows a block diagram of this conventional system debug device. In FIG. 4, 5 is a target system to be developed and debugged, 6 is an in-circuit emulator for debugging the target system 5, 7 is a host computer for controlling the in-circuit emulator 6, and 11 is instruction fetch and execution. A microprocessor for executing, 12 is a boot ROM for storing instructions, 13 is a main memory for storing instructions and data, 1
4 is a memory controller for controlling the main memory 13, 15
Is an IO device group that directly controls a hard disk or a communication medium, 16 is an IO / DMA controller that controls the IO device group 15, 18 is an arbiter circuit that controls a bus master, 21 is an IC socket for the microprocessor 11, and 41 Is a memory for storing instructions and data, 42 is a switching circuit for switching between the memory on the target system 5 side and the memory in the in-circuit emulator 6, and 43 is a communication control circuit with the host computer 7.

A system debug method of the system debug device configured as described above will be described below.

During initial debugging of the target system 5, the test program is first downloaded from the host computer 7 to the memory 41 in the in-circuit emulator 6 via the communication control circuit 43 without using the boot ROM 12. Next, the switching circuit 42 distinguishes the fetch and execution of the instruction by the control signal of the microprocessor 11 and switches the in-circuit emulator 6 side and the target system 5 side in a timely manner.
After fetching the instruction from 1, the instruction is executed in the target system 5 via the IC socket 21 in the target system 5, and is executed via the memory controller 14 under the control of the bus master of the arbiter circuit 18. The memory 13 can be written / read, or the IO device group 15 can be accessed via the IO / DMA controller 16 to perform data transfer with the main memory 13.

Further, the boot ROM 12 is mounted, the control of the switching circuit 42 is transferred to the target system 5 side, and the fetch is performed in the target system 5 as well as the execution of the instruction, whereby a series of operation confirmation can be performed.

The microprocessor 11 is used to trace the execution of an instruction and store the result in the memory 41, or the values of the memory and registers in the target system 5 after the instruction is executed are uploaded to the memory 41. You can also do it.

[0009]

However, since the in-circuit emulator, which is an indispensable item for development, is complicated in the above-mentioned configuration, it takes a considerable amount of time since the introduction of a new microprocessor until its development and availability. It takes a long time, and the microprocessor is on the in-circuit emulator, and there is a problem that the operation speed becomes slow because a delay occurs in the cable between the target system and the microprocessor.

In view of the above problems, it is an object of the present invention to provide a system debugging method capable of easily developing and debugging an on-board system at an early stage with the advent of a new microprocessor and further debugging at the maximum operating speed of the microprocessor. And

[0011]

[Means for Solving the Problems]

(1) In order to solve the above problems, the system debugging method of the present invention provides a target system having a microprocessor and a bus arbiter function capable of on / off control by an external control signal, and a system bus of the target system. In a hardware environment with a test system that can be connected to and write / read the memory, registers, etc. on the target system, first turn off the arbiter function in the target system to open the system bus, The program is downloaded to the target system, or conditions such as memory and registers are set, then the arbiter function is turned on, and the microprocessor executes the program in the target system to debug the target system. (2) In order to solve the above problems, the system debugging method of the present invention includes a target system equipped with a microprocessor and having a bus arbiter function capable of on / off control by an external control signal, and a system bus of the target system. In a hardware environment that includes a circuit that connects to the terminals of the integrated circuit and that accesses the memory, registers, etc. of the target system on programmable hardware, and an emulation system that maps the integrated circuit under development in the target system. , First, turn off the arbiter function in the target system, open the system bus, and let the test system download the program to the target system or set conditions such as memory and registers, then turn on the arbiter function and set the target. In the system Microprocessor for executing a program, and performs debugging the target system.

[0012]

According to the present invention, with the above-described configuration, the arbiter function can be turned off, the test system can access the memory, registers, etc. on the target system to download the test program and upload the test results.
In addition, the arbiter function can be turned on, the microprocessor can be executed, and the test program can be run.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A system debugging method according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an apparatus for implementing a system debugging method according to the first embodiment of the present invention. In FIG. 1, 11 is a microprocessor and 12
Is a boot ROM (or RAM), 13 is a main memory, 1
Reference numeral 4 is a memory controller, 15 is an IO device group, and 16 is an IO / DMA controller. The above is the same configuration as the conventional example shown in FIG. 1 is a target system to be developed / debugged, 2 is a test system for debugging the target system 1, 17 is an arbiter circuit that can turn on / off an arbiter function for controlling a bus master by an external control signal, and 31 is a test system 2. A computer for controlling 32 is an expansion board of the computer 31, which is a memory / register access board capable of accessing the memory, registers and the like of the target system.

A system debugging method of the system debugging device configured as described above will be described below with reference to FIG.

At the time of initial debugging of the target system 1, first, the boot ROM 12 is replaced with a RAM, the arbiter function of the arbiter circuit 17 is turned off by a control signal from the test system 2, and the right to use the system bus is transferred to the test system 2. Then, from the computer 31
The test program is downloaded to the boot RAM 12 in the target system 1 via the register access board 32. Next, after resetting the target system 1, when the arbiter function of the arbiter circuit 17 is turned on by the control signal from the test system 2, the right to use the system bus returns to the target system 1 and the microprocessor 11 receives an instruction from the boot RAM 12. To execute the instruction, and under the control of the bus master of the arbiter circuit 17, write / read the main memory 13 via the memory controller 14 or the IO device group via the IO / DMA controller 16. Data can be transferred to and from the main memory 13 by accessing 15. Further, the arbiter function of the arbiter circuit 17 is turned off again by the control signal from the test system 2, and the value of the memory or register in the target system 1 after the instruction execution is uploaded to the computer 31 via the memory / register access board 32. You can also do it.

The operation of the memory / register access board 32 will be described with reference to the block diagram shown in FIG. (1)
The start address of the memory register to be accessed is written in the start address register 52. (2) Write the end address of the memory register to be accessed to the end address register 55. (3) Write data is sequentially written to the data FIFO memory 56 only when the memory register is accessed for writing. (4) A flag indicating whether to write or read and an execution start flag are written to the control register 51. (5) The address counter 53 fetches the start address from the start address register 52, and then sequentially increments the address from the start address to the end address while comparing with the end address stored in the end address register 55 by the address comparator 54. Then, the address is output to the target system side via the input / output interface 57. Further, at the time of writing, the data is output from the data FIFO memory 56 via the input / output interface 57, and at the time of reading, the data is input to the data FIFO memory 56 via the input / output interface 57. (6) Read data is sequentially read from the data FIFO memory 56 only when the memory register is accessed for reading. As described above, according to this embodiment, by providing the system bus arbiter circuit 17 capable of on / off control by the external control signal, it is possible to connect the expansion board 32 for memory / register access to the existing computer 31. The system debug can be easily performed, and the time when the target system 1 is accessed from the test system 2 and the time when the microprocessor 11 fetches and executes the instruction in the target system 1 can be completely separated. Can be set independently, and when the program is executed in the target system 1, no extra delay is generated, so that high speed operation can be enabled.

A system debugging method according to the second embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an apparatus for realizing the system debugging method according to the second embodiment of the present invention. In FIG. 3, 11 is a microprocessor and 12
Is a boot ROM (or RAM), 13 is a main memory, 1
Reference numeral 5 is an IO device group, and 17 is an arbiter circuit, which has the same configuration as that of the first embodiment shown in FIG. Reference numeral 3 is a target system to be developed / debugged, 4 is an emulation system that emulates the functions of a test system for debugging the target system 3 and the functions of an integrated circuit (memory controller and IO / DMA controller) in the target system 3, 22 Is an IC socket for a memory controller, 23 is an IC socket for an IO / DMA controller, 33 is a computer for controlling the emulation system 4, 34, 35, and 36 emulate a memory controller, an IO / DMA controller, and a memory / register access circuit, respectively. Programmable emulation board, 3
7, 38 are emulation boards 34, 3 respectively
5, a pattern generator and a logic analyzer for generating or tracing external / internal signals.

With respect to the system debug device configured as described above, the system debug method will be described below with reference to FIG.

The target system 3 can be debugged by programming the emulation boards 34 and 35 of the emulation system 4 and emulating the integrated circuit even before obtaining the integrated circuit of the memory controller and the IO / DMA controller. At this time, the memory / register access circuit used as the test system is also programmed in the emulation board 36 in the emulation system 4 so that it is more flexible and easier than the first embodiment shown in FIG. Can be built. First, the boot ROM 12 is replaced with a RAM, the arbiter function of the arbiter circuit 17 is turned off by a control signal from the emulation board 36 of the emulation system 4, and the right to use the system bus is transferred to the emulation system 4. Using the function, the test program is downloaded from the computer 33 to the boot RAM 12 in the target system 3 via the emulation board 36 in which the memory / register access circuit is programmed. Next, when the arbiter function of the arbiter circuit 17 is turned on by the control signal from the emulation board 36, the right to use the system bus returns to the target system 3, and the microprocessor 11 fetches the instruction from the boot RAM 12 and executes the instruction. Under the control of the bus master of the arbiter circuit 17, the main memory 13 is written / read via the emulation board 34 and the IC socket 22 which substitutes for the memory controller, and the IO / DMA controller substitutes. The IO device group 15 is accessed via the emulation board 35 and the IC socket 23 to access the main memory 13
Data can be transferred between and. Further, the arbiter function of the arbiter circuit 17 is turned off again by the control signal from the emulation board 36, and the value of the memory and the register in the target system 3 after the instruction execution is used by using the function of the logic analyzer 38. It can also be uploaded to the computer 33 via.

Further, a memory controller and IO / DM
After the A controller integrated circuit is obtained, replace the emulation boards 34 and 35 with the obtained integrated circuit as an IC.
By mounting in the sockets 22 and 23 respectively, when the target system 3 is accessed from the emulation system 4 as the test system and when the target system 3 accesses the target system 3 as in the first embodiment shown in FIG. Since it can be completely separated from the time of both fetching and executing, the frequency can be set independently to enable high speed operation when executing the program in the target system 3.

As described above, according to the present embodiment, in order to realize the circuit for accessing the memory and the register of the test system and the integrated circuit under development in the target system,
By using the programmable emulation system 4, a flexible test system can be developed early by sharing a part of the test system and the target system in the same system, and the target system can be debugged early even before the integrated circuit is obtained. ..

Although the arbiter circuit is independent in the first and second embodiments, it may be provided in the microprocessor or in the integrated circuit.

Further, in the second embodiment, the emulation board is divided into three for each emulation function for convenience of explanation, but this may have three functions programmed on one board. ..

[0026]

【The invention's effect】

(1) As described above, the present invention is turned on by the external control signal.
By providing a system bus arbiter function capable of off control, the system can be debugged easily and the operation can be performed at high speed. (2) As described above, the present invention is the memory of the test system,
A programmable emulation system is used to realize a circuit for accessing registers and the like and an integrated circuit under development in the target system. Test system can be developed early,
Also, the target system can be debugged early even before the integrated circuit is obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an apparatus that implements a system debugging method according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a memory / register access board according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of an apparatus that realizes a system debugging method according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional system debug device.

[Explanation of symbols]

1 Target System 2 Test System 3 Target System 4 Emulation System 11 Microprocessor 17 Arbiter Circuit 32 Memory / Register Access Board 34, 35 Integrated Circuit Emulation Board 36 Memory / Register Access Circuit Emulation Board 37 Pattern Generator 38 Logic Analyzer

Claims (2)

[Claims] 1. A target system equipped with a microprocessor and having a bus arbiter function capable of on / off control by an external control signal, and a memory on the target system, which is connected to a system bus of the target system.
In a hardware environment equipped with a test system that can write / read registers, etc., first turn off the arbiter function in the target system to open the system bus, and the test system downloads the program to the target system or memory. , A condition is set for registers and the like, then the arbiter function is turned on, and the microprocessor executes a program in the target system to debug the target system. 2. A target system equipped with a microprocessor and having a bus arbiter function capable of on / off control by an external control signal, and a system hardware of the target system and a terminal of an integrated circuit, which are connected to programmable hardware. In a hardware environment that includes a circuit that accesses the memory and registers of the target system and an emulation system that maps the integrated circuit under development in the target system, first turn off the arbiter function in the target system and then The bus is released, the test system downloads the program to the target system or sets conditions such as memory and registers, then turns on the arbiter function, the microprocessor executes the program in the target system, and the target system executes. System Debug wherein the debugging of the system.