JPH05204693A - Exceptional order guarantee testing system - Google Patents

Abstract

PURPOSE:To provide an exceptional order guarantee testing system capable of testing a computer system by combining all states of channels, CPUs, etc., in their normal operation and all exceptional events to be generated and inspecting the interruption priority order of plural exceptional events. CONSTITUTION:All exceptional events to be generated in a command or instruction string are integrated (step 1). Then the command or instruction string is executed (step 2), interruption validity is inspected in the ascending order of the interruption priority order to remove exceptional events (steps T3, T4). This test is repeated in the same command/instruction to test normality in the operation of the computer system. Consequently the normality of the priority order of plural exceptional events and the normality in the operation of the computer system for all the exceptional events can be tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test method for an electronic computer system, and more particularly to an exceptional order guarantee test method capable of systematically verifying the normality of the hardware logic of the electronic computer system.

[0002]

2. Description of the Related Art Recently, the performance of electronic computer systems has been improved.
Along with the demand for higher speed, an increasing number of electronic computers have realized higher performance and higher speed by using a plurality of CPUs together and distributing the processing. In addition, there is a tendency that a single system is made to appear as a plurality of systems by using a virtual machine (VM) so that a plurality of OSs can be used together and processing efficiency can be improved.

As described above, in order to verify the normality of the hardware logic which realizes the expansion of the system scale and the diversification of processing, it is not possible to cover the functional test by itself.
It is necessary to systemically verify the logic. FIG. 7 is a diagram showing the basic configuration of an electronic computer system. In the figure,
Reference numeral 101 is a main storage device, 102 is a storage control device, 103 is a central processing unit, 104 is a channel processing device, 105 is a block multiplexer channel, and 106 is a byte.
Multiplexer channel, 107 is a service processor, block multiplexer channel 10
In addition to the LAN controller shown in the figure, various input / output devices such as a magnetic drum device and a disk pack device are connected to the reference numeral 5, and a byte multiplexer channel 1
An input / output device such as the illustrated service processor 107 is connected to 06.

In the system verification of the electronic computer system described above, the channel processor 104 does not depend on the central processor 103 for interrupts and its operation is asynchronous with the central processor 103. Below, abbreviated as channel), it is necessary to verify the hardware logic. FIG. 8 is a flowchart showing a conventional channel system test method.

In a conventional channel system test, as shown in FIG. 1, first, a CCW (channel control word, hereinafter abbreviated as CCW) of the channel.
A column is randomly extracted (step S1). Then, the channel is activated, control is passed to another task for multi-tasking, and an interrupt is awaited (step S2, step S3, step S4).

Then, when there is an interrupt, the executed CC
The status of W and the channel were compared to check whether or not they correspond to each other, and the normality of the operation of the channel was verified. Although the channel system test method as described above verifies the normality of the possible states of the channel, system verification by the operation timing of the channel including exceptional events is insufficient, and this is the coverage of the system test. Was not the cause of improvement.

As for the system test of the central processing unit 103 (hereinafter abbreviated as CPU), conventionally, the system test has been performed by the method shown in the flowchart of FIG. In FIG. 9, first, data is randomly created (step R1), and a test instruction sequence and test data are created from the random data (step R2). Then, the instruction sequence created as described above is executed (step R3).

When an interrupt is generated as a result of executing a randomly generated instruction sequence, the executed instruction is compared with the cause of the interrupt to check the validity of the interrupt (steps R4 and R5). The normality of the operation of the CPU was verified. The system test method of the CPU as described above is
By generating and executing a sequence of instructions from random data,
Although all possible combinations of instruction sequences are realized, this method is fixed in each case where each instruction has an exception event and when it does not have an exception event. System verification was insufficient, which caused the coverage as a system test to not be improved as in the above-mentioned channel test.

As described above, the conventional system testing method lacks the verification from all aspects of the exceptional event, and cannot verify the interrupt priority of a plurality of exceptional events. ..

[0010]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned drawbacks of the conventional apparatus. All the states and occurrences of normal operation that can be taken by a channel or a CPU of a computer system are generated. It is an object of the present invention to provide an exception sequence assurance test method that can test a system by combining all obtained exception events and can also verify the interrupt priority of a plurality of exception events.

[0011]

FIG. 1 is a flow chart showing the principle of the present invention. The invention of claim 1 of the present invention is
As shown in FIG. 1, in order to verify the hard logic of the computer system, all possible exception events are incorporated into the environment to be tested (step T1).

Next, each time the test is executed, the same test is repeated while excluding the exceptional events from the highest interrupt priority order (steps T2, T3, T4). The invention of claim 2 of the present invention is an application of the invention of claim 1 to the verification of the hard logic of a channel of a computer system, and as shown in FIG. Incorporate state exceptions (step T
1).

Then, execution of the same channel command is repeated while excluding the exception events incorporated from the highest priority order (steps T2, T3, T4). The invention of claim 3 of the present invention is an application of the invention of claim 1 to the verification of the hardware logic of the CPU of a computer system. As shown in FIG. 1, all exception events are incorporated in the instruction sequence ( Step T1).

Then, the execution of the same instruction sequence is repeated while excluding the incorporated exception events from the highest priority order (steps T2, T3, T4).

[0015]

Operation: Incorporate all possible exception events into the computer system channel or CPU command or instruction,
It is possible to confirm the normality of the priority order of a plurality of exception events by repeating the execution of the same channel command while excluding the exception events incorporated from the highest interrupt priority order. Also, along with that, it becomes possible to verify the normality of the operation of the computer system for all exceptional events.

[0016]

FIG. 2 is a flow chart showing a first embodiment of the present invention, and the channel testing method which is the first embodiment of the present invention will be described with reference to FIG. First, in step H1, a CCW sequence of channels is randomly extracted. The CCW sequence is extracted in the following procedure. (1) Selection of CCW sequence First, a basic CCW sequence is prepared in advance. In this case, a CC that performs a series of operations on one CCW sequence until the end
Select column W (for example, in DASD control, C
Write 0 data to the head of E cylinder and read the written data again.) Also, the byte count (hereinafter BC
(Abbreviated as)) sets the necessary values in advance.
Bits that need to be turned on in the flag section are turned on in advance. One CCW sequence is randomly selected from a plurality of CCW sequences that perform various operations for the I / O selected as described above.

Then, in step H2, the CCW start address, CCW flag portion, CCW data address, IDAW (indirect data.
The address word) information, the channel DAT (channel dynamic address translation) are modified, and the exception event is modified in step H3. FIG. 3 is a diagram for explaining the modification of the CCW and its exception event, and FIG. 4 is a diagram showing a recovery table for writing a normal value for recovery when the exception event is modified. .. One recovery table is prepared for each CCW that incorporates an exceptional event.

Modification of CCW and its exceptional event will be described with reference to FIGS. (2) Modification of CCW sequence The selected CCW sequence is modified within a range that does not destroy the shape of the normal end. Use channel DAT to randomly assign logical addresses for CCW and data. For example, in FIG. 3a
Addresses of segment SS in CCW and data segment table 201 and page PP in page table 202 are randomly selected and assigned. Randomly modify the flag part. Further, in this case, when the IDA (indirect data address) of the flag portion is ON, as shown in FIG. 3b, the CCW data address 210
A table 220 for IDAW corresponding to is prepared.

Further, the data chain of the flag part is turned on.
In the case of, the count specified by the BC is divided and a CCW for the data chain is newly added. For example, in FIG.
When the BC of the CCW 230 is 4096 as shown in FIG. 7C, the CCW is BC = 102 as shown by 231 in FIG.
4, BC = 2048, BC = 1024, and two CCWs for a data chain are added to the divided BC.

Further, other flag parts such as the program control interrupt flag PCI and the skip flag SKIP for skipping data transfer to the main memory are randomly selected. Qualify the in-page address. For example, as shown in FIG. 3d, the start address of the CCW 240 is randomly selected from the in-page real address 241 of 4 KB. (3) Exception event modification In step H2, an exceptional event is incorporated into the modified CCW sequence. Using the channel DAT, incorporate an exception event for each randomly assigned logical address of CCW and data. For example, in FIG.
An exception event such as assigning an address such that the segment SS in the table 201 and the page PP in the page table 202 are invalid, or assigning a real address outside the specifiable real address is incorporated. For a real address, an exception event is incorporated in the protection factor, and the KEY value representing the protected area of the main memory is modified.

When the above-mentioned exceptional event is incorporated, the recovery table 250 shown in FIG. 4a is prepared,
Write the normal value in case of restoration. For example, when a real address out of the range is assigned, a correct address or the like is written in the recovery table 250. Randomly modify the flag part before incorporating the exception event.

For example, if the IDA is ON, then FIG.
Prepare a table 220 for IDWA as shown in
An event is set such that the DAW address is not the boundary of 8 (the CCW address must start from the 8th bit, but the CCW address is set so that the CCW address does not start from the 8th bit). For the real address, an event is set such that the second IDAW pointer is not 2K boundary (second IDAW).
The W pointer must be the start or end address of the 2K byte block, but the IDAW pointer is set not to be the start or end address of the 2K byte block).

At the same time, the correct IDAW address and the like are written in the recovery table 250 shown in FIG. Also, when the data chain is ON, the CCW BC is as described in the CCW modification.
After splitting and adding CCW for data chain,
For example, BC of CCW 251 is set to 0 as shown in FIG. 4b. At the same time, the correct BC value is written in the recovery table 250 as shown in FIG.

When a normal value at the time of incorporating and recovering an exceptional event is written in the recovery table 250, 1 is set to the corresponding bit of the exception embedding flag part 250a of the recovery table 250 shown in FIG. 4a. deep. Bits are defined in the exception embedding flag portion 250a of the recovery table 250 in the order of priority of exception events.

After modifying the exceptional event as described above, in step H4 of the flow chart of FIG. 2, step H5 is performed to activate the channel and perform multitasking.
At, a task change is performed and control is transferred to another task. Next, in step H6, an interrupt is waited, and if there is an interrupt, the process proceeds to step H7, and step H7
In step S8, it is determined whether or not it is the exceptional event status.

When the exceptional event status is detected, in step H8, the CCW in which the exceptional event is detected is determined from the next CCW address, and the CCW is searched in the order of higher priority of the exceptional event to set the exceptional event. And confirm the legitimacy.
In step H9, the detected exceptional event is recovered to the normal state. When recovering, referring to the recovery table 250 shown in FIG. 4, the recovery information is extracted from the recovery table 250, the exception event of CCW is eliminated, and the corresponding information in the recovery table 250 is set to 0. Clear and return to step H4.

For example, when BC = 0 is set, BC = 1024 is extracted from the BC position of the recovery table 250 shown in FIG.
The BC value of W is corrected and the recovery table 2
The flag of BC of the exception embedding flag portion 250a information of 50 is cleared to 0. When the exception events incorporated in all CCWs are recovered by repeating the above steps H4 to H9, the exception status is excluded.
The process proceeds from step H7 to step H10, confirms that the status is normal, and returns to step H1.

FIG. 5 shows the flow chart of FIG. 2 in which after an interrupt occurs in step H6, step H7
11 is a flowchart showing a processing procedure from determination of an exception status to step H9. Processing of an exceptional event will be described with reference to FIG. When an interrupt occurs due to the exception status, in step J1, it is compared whether or not the interrupt factor is an interrupt due to a CCW exception event. If the interrupt is due to a CCW exception event,
At step J2, it is confirmed from the fact that the contents of the recovery table 250 are 0 that there is no exceptional event in the CCW up to immediately before.

Next, for the CCW in which the exceptional event has occurred in J3, the following steps J4 to J7 are performed.
In the procedure up to, the interrupt factor and the exception event are compared by referring to the exception embedding flag portion 250a of the recovery table 250. That is, in step J4, it is determined whether or not an exceptional event is incorporated in the CCW address conversion process. If YES, then go to step J9, and if NO, go to step J5. In Step J5,
It is determined whether or not the exceptional event is incorporated by the information in the CCW. If YES, the process proceeds to step J9, and if NO, the process proceeds to step J6. In step J6, I
It is determined whether or not the exceptional event is incorporated in the DAW information. If YES, go to step J9, and if NO, go to step J7. In step J7, it is determined whether or not the exceptional event is incorporated in the data, and YES
If NO, go to step J9, and if NO, go to step J8.

If NO in any of the above steps J4 to J7, it means that the interrupt has occurred even though the exceptional event is not incorporated, so the process goes to step J8 to perform the error processing. If YES in any of J4 to J7, the process goes to step J9 to compare the built-in exception event with the interrupt factor to determine whether they match, and if they do not match, an error occurs. Perform processing.

If the built-in exception event and the interrupt factor are compared and if they match, the process goes to step J10, the exception event is deleted based on the information in the recovery table 250, and the corresponding recovery table 250 is deleted. The exception embedding flag portion 250a is cleared to 0. When the verification of the randomly selected CCW sequence is completed as described above, the process returns to step H1 and the CCW sequence is randomly selected again and the above verification is repeated.

As described above, according to this embodiment, exception events are incorporated into CCW sequences randomly selected from the basic CCW sequences, and the priority levels of the exception events are assigned in descending order. While confirming, recover the exception event,
Since it is repeatedly processed until all exception events are cleared, it is possible to verify all exception events while verifying the priority of the exception event for the basic CCW sequence.

FIG. 6 is a flow chart showing the second embodiment of the present invention, and this figure is a flow chart showing the test system of the CPU. It is possible to perform a test in the CPU test in the same way as in the channel test, and a CPU test method according to the second embodiment of the present invention will be described with reference to FIG.

In FIG. 6, first, in step C1, data is randomly created, and in step C2, a test instruction string and test data are created from the random data. Then, in step C3, the instruction sequence created as described above is executed. When an interrupt occurs as a result of executing the randomly generated instruction sequence, the executed instruction is compared with the cause of the interrupt in step C4.

Then, as in the case of the channel, the cause of the interrupt is removed from the interrupt instruction and the interrupt code in step C5, the instruction is returned to the interrupt cause address in step C6, and the process returns to step C3 to repeat the above procedure. When all the causes of interruption have been eliminated as described above, the process proceeds to step C7, the task is switched, and the process returns to step C1.

As described above, even in the CPU test,
Similar to the channel test, it is possible to verify all exception events while verifying the priority of exception events possessed by randomly generated instruction sequences.

[0037]

As is clear from the above description,
In the present invention, while checking the interrupt priority of a plurality of exception events incorporated in the CCW or the instruction,
Since it is configured to be excluded and to be repeated until all exceptional events are eliminated, it is possible to confirm the normality of the hardware logic in all combinations of normal and exceptional states that can be taken by the channel and CPU system. The operation of the hardware of the computer is guaranteed, and it greatly contributes to the improvement of the reliability of the electronic computer system.

[Brief description of drawings]

FIG. 1 is a flowchart of the principle of the present invention.

FIG. 2 is a flowchart showing an embodiment of the present invention.

FIG. 3 is a diagram illustrating modification of CCW and incorporation of exceptional events.

FIG. 4 is a diagram showing a configuration of a recovery table.

FIG. 5 is a diagram showing interrupt processing in the first embodiment of the present invention.

FIG. 6 is a flowchart showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a basic configuration of an electronic computer system.

FIG. 8 is a diagram showing a conventional channel test system.

FIG. 9 is a diagram showing a conventional CPU testing method.

[Explanation of symbols]

 220 table for IDWA 250 recovery table 250a exception embedding flag part

Claims (3)

[Claims] 1. In a test method for verifying the hard logic of a computer system, all possible exception events are incorporated into the environment to be tested (step T1), and the interrupt priority is set every time the test is executed. By excluding the exception events from the highest order, and repeating the same test (steps T2, T3, T4), while confirming the normality of the priority of multiple exception events, the system operation for all exception events Exception order guarantee test method characterized by verifying. 2. In a test method for verifying a hard logic of a channel of a computer system, exception events of all possible states of the channel are incorporated in a channel command (step T1), and they are incorporated in descending order of interrupt priority. By repeating the execution of the same channel command while excluding exception events (steps T2, T3, T4), while confirming the normality of priority of multiple exception events, the system operation for all exception events can be confirmed. Exception order guarantee test method characterized by verification. 3. In a test method for verifying the hard logic of a processing unit of a computer system, all exception events are incorporated in an instruction sequence (step T1), and exception events incorporated in descending order of interrupt priority are excluded. By repeating the execution of the same instruction sequence (steps T2, T3, T4), while confirming the normality of the priority of multiple exception events, the operation of the processing unit for all exception events is verified. Exception order assurance test method.