JPH05204502A - Electric power management sequencer - Google Patents

Abstract

PURPOSE: To provide a power management device which doesn't require the additional cost by providing a power management sequencer which sequences power management instructions obtained through an I/Q bus independently of a CPU instruction sequencer. CONSTITUTION: The power management device includes the power management sequencer which sequences power management instructions obtained through an I/Q bus 22 independently of the CPU instruction sequencer. These instructions are stored in a BIOS EPROM 48, and consequently, they can be customized by a manufacturer so that they include specific power management instructions required for peripheral devices included in a system. The BIOS EPROM doesn't cost the computer manufacturer additionally because it is included anywhere at need unless it purposes to include a proper initialization routine for the combination of a BIOS and specific attached peripheral devices.

Description

Description: FIELD OF THE INVENTION The present invention relates to IBM PC AT compatible computers and, more particularly, to an apparatus for managing the reduced power consumption mode of certain peripherals in these computers. Regarding

(Description of Related Art) A typical IBM PC AT compatible microcomputer is Intel Corporation.
80286, 80386, 80486 manufactured by Ion
And so on. The CPU is connected to a local bus capable of memory access and data transfers at high speeds (ie, on the order of 10-50 MHz according to today's technology). The local bus contains 16 or 32 data lines, multiple memory address lines, and various control lines. A typical IBM PC AT compatible platform also includes a DRAM main memory, a timer, a real time clock, and possibly a cache.
And memory, all of which are connected to the local bus. A typical IBM PC AT compatible computer also includes a local bus and a separate I / O bus. The I / O bus (sometimes referred to as the AT bus, ISA bus, or EISA bus in these systems) is connected to the local bus via some type of interface circuit. The I / O bus contains 16 or 32 data lines, a plurality of I / O address lines, and control lines. The I / O address space is logically separate from the memory address space, and if the CPU wants to access a certain I / O address, some special I / O instruction Do it by running. I / O like this
The instruction issues a memory access signal on the local bus, but also an MIO # signal to indicate that this is an access to the I / O address space. MIO
The # line is often considered simply another address line. The interface circuit recognizes such CPU generated I / O signals, performs the desired operation over the I / O bus, and returns the result, if appropriate, back to the CPU over the local bus. In fact, some I / O addresses may physically reside on the local bus and some memory addresses may physically reside on the I / O bus. The interface circuit can respond to recognize that one memory access or I / O address access should be emulated by an access to another bus, and also perform this emulation. You can respond to do so. For example, a ROM (or EPROM) BIOS may physically be on the I / O bus, but actually forms part of the local memory address space. C during system boot
Non-I / O where PU is physically present in ROM BIOS
When an address is sent, the interface circuit recognizes it, enables the buffer that sends the address to the I / O bus, and activates the chip select for the ROM. The interface circuit then uses the data returned by the ROM to transfer the data of the size expected by the CPU.
Assemble the word, send it to the local bus, and the CPU receives it. In many systems, at some point during the ROM-based bootup procedure, the ROM BIOS is copied to an equivalent location in DRAM main memory and then accessed directly. The portion of DRAM that receives this portion of BIOS is sometimes referred to as "shadow RAM". More specifically, in the standard architecture, the logical main memory address space is the low memory area (0h-9FF
FFh), reserved memory area (A0000h-FFFFF
h), extended memory area (100000h-FFFFFF
h). In a typical system, the system ROM BIOS is logically address F0000.
It is located at h-FFFFFh and is physically located on the I / O bus. Address C0000h-EFFFFh contains the ROM BIOS portion for the special add-on card and is physically located on each card of the I / O bus. Address A0000h-BFFFFh is I /
It contains a video buffer physically located on the video controller card of the O-bus. Typically D on the local bus for address C0000h-FFFFFh
Duplicate memory space is provided in RAM to allow the user of the system to select the portion of the ROM BIOS to be "shadowed" by being copied into the duplicate DRAM space during bootup. BIO
Subsequent access to the "shadowed" portion of S is DR
This is done for AM copies, which are usually much faster than accessing ROM copies. In addition to the above elements, in the case of a video display controller, a keyboard controller is also typically connected to the I / O bus. A typical IBM PC AT compatible system is
It also includes a DMA controller that allows peripherals on the I / O bus to directly read from and write to main memory, as well as an interrupt controller that transmits interrupts from various add-on cards to the CPU. Sometimes. Add-on cards are I / O
It is a card that plugs into a slot connector connected to the bus to enhance the system's capabilities. IBM in various aspects
For general information about PC AT compatible computers, see Sanchez, "IBM Microcompu.
ter: A Programmer's Handbo
ok "(McGraw-Hill: 1990) and S
olari "AT Bus Design" (San
Diego: Annabooks, 1990). In addition, "i486 Mic" published by Intel Corporation (copyright date 1990)
roprocessor Hardware Review
See also the various data books and data sheets published by Intel Corporation regarding the structure and application of the iAPX-86 series microprocessors, including "Rense Manual". All of the above materials are incorporated herein by reference. In recent years, in order to simplify the processing system of the IBM PC AT compatible computer,
Efforts have been made to integrate most or all of the resource and interface functions onto a small number of chips in a single chipset. An example of such a chipset is
OPTi, Inc. of Santa Clara, California.
There is an OPTi-386 PC / AT chipset available from Publications include OPTi, Inc. (March 28, 1991) published "OPTi-386
WB PC / AT Chipset (82C391 / 8
2C392 / 82C206) Preliminary
82C391 / 82C392 Date Book "describes this chipset, which is also incorporated herein by reference. In recent years, efforts have also been made to reduce the size of the entire IBM PC AT compatible computer to make it portable. The main limiting factors for portability were the size and weight of the battery and the duration before recharging. Therefore, it was common to include power saving features in the chipsets and other parts of the computer described above. Some peripheral device manufacturers also include power saving features in their products to facilitate power savings in portable computers. For example, some disk drives are made to save power in one of two ways. First, if the disk drive has not been accessed for more than a few minutes, a step can be taken to shut down all power to the disk drive until the next time the disk drive needs access. it can. This power saving mode is referred to herein as "power down." If the disk drive (or its controller) contains its own configuration register, the CPU must read and store the configuration before powering down the drive. Generally, power down has traditionally been impossible for peripherals that maintain configuration data and cannot be read back by the CPU. Alternatively or additionally, the disk drive can be designed to have a reduced power mode that can be invoked by commands issued across the I / O bus connected to it. When such a mode is called
Depending on the characteristics of the drive, the drive will stop its motor, reduce power to most of its circuitry, retain content in internal commands or configuration registers, and also I / O.
It is possible to keep only the circuits available to resume full power supply when receiving another command issued through the bus. This power saving mode is referred to herein as the "reduced power" mode. ConnerPeri
CP3044IDE manufactured by Pherals
A disk drive is an example of a drive that has a reduced power mode. The Conner drive is even more
Has a built-in auto power-down mode, which is programmed by commands issued across the I / O bus to monitor access to itself and no access within a programmable number of minutes Means that the reduced power mode can be activated. Conner Peripherals CP3
044 and Conner Peripherals,
"CP3044 Product / Manual", R
Evision VI. 1 is incorporated herein by reference. Other power saving modes may be provided for a particular peripheral device. Depending on the particular peripheral, a "command" issued to this peripheral across the bus is as simple as a single read or write access to the address assigned to this peripheral. Or it may be a fairly complex series of accesses. Various methods are used to determine when a particular peripheral should be placed in a power saving mode. For example, some I / O bus interface chipsets monitor the I / O bus address lines to keep the I / O bus within a given I / O address area, for example, an I / O assigned to a disk drive If no address within the address area has been accessed for at least a predetermined number of minutes, a signal is generated indicating it.
As another example, many systems include circuitry that indicates when the battery voltage is low and indicates that power saving mode should be activated. Many systems also have an external switch that allows the computer user to activate it to invoke the power saving mode, and the host software running on the CPU activates the power saving mode. You can also let them know that you should. Conventionally, if a peripheral device should enter a power saving mode, such information would be provided if the signal originated external to the CPU.
The CPU is notified via either the NMI interrupt pin or the IRQ interrupt pin and the signal is
If it came from an algorithm, it was informed to the CPU by a software interrupt. In either case, the host processor is vectored to the interrupt handler to determine the source of the power down interrupt and then the power saving mode to call. Once the desired power saving mode has been called and the peripheral device has been powered down, the CPU running under the control of the interrupt handler reads and saves the device command and configuration registers, then the CPU Activating the port pin either on itself or on an external chip,
Power to this peripheral is shut off. If the reduced power mode of the peripheral itself should be invoked, then CP
Under the control of the driver, U will issue the appropriate command to do so via the interface circuit and I / O bus. CP for power management
An example of a chipset that uses U interrupt activation technology is Western Digi, Irvine, California.
WD760 manufactured by tal Corporation
It is a 0 chipset. One of the problems with CPU interrupt driven methods for power management is that they require CPU intervention and take time away from other tasks that may be more effectively performed. Another problem with the CPU interrupt driven method, depending on the software the computer is running on, is that it is impossible to install a power management driver for a particular peripheral in the ROM BIOS, or It is inconvenient. When a computer manufacturer ships a computer to an end user, it is desirable to have all the basic control codes unique to each particular peripheral included in the computer pre-stored in ROM or EPROM. This includes initialization routines required by specific peripherals as well as power management routines in the case of portable computers. ROM or EPROM storage for such routines is possible if the computer is adapted to run software running under the DOS operating system sold by Microsoft Corporation. For example, here the interrupt vector is supposed to always stay at the known address of the memory (00H-3FFH). However, other software packages may move the interrupt vector table to somewhere else in memory. For example, the program known as "Windows" available from Microsoft Corporation does this. Operating system OS / 2
Does this as well. These programs also set up their own interrupt driver, ROM
IRQ or MN that may already exist in BIOS
Ignore the I driver. Therefore, the manufacturer
Q, any power management code that you want to include in the MNI's ROM-based interrupt handler will also be ignored when these programs are started. Windows and OS
/ 2 allows the user to load a new interrupt handler after startup, but manufacturers wishing to include the power management feature must distribute an alternate driver on disk, each of these programs About different drivers have to be distributed. Another problem with the CPU interrupt driven method for power management is that it consumes one or more maskable interrupt levels or, if attached to the NMI, needs to handle additional service codes. Is that there is. In any case, all IRQ interrupt levels are pre-defined for standard IBM PC AT compatible computers, so using IRQs for power management will make your system compatible with standard IBM PC AT compatible computers. Will be reduced. One possible solution to the above problem consists in offloading power management functions to the KiboDodo controller already present in the system. The keyboard controller is I
ntel Corp. They are often processed by an 8042 microcontroller, available from Microsoft Corp., and connected to the I / O bus. 8042 is a command or data I
A general-purpose peripheral interface controller that can receive from the I / O bus and send to the I / O bus. The 8042 also includes internal ROM program memory connected to an internal command processor through an internal bus, as well as a plurality of ports for connecting to peripheral devices. Typically, 8042 within the system is programmed to perform only keyboard operations.
However, it also responds to various sources of power-down signals and uses the port pins that are not used for the purpose of the keyboard controller to reduce the reduced power characteristics of separate peripheral devices such as disk drives. It may also be programmed to control. In addition, if the 8042 is attached to the I / O bus, it also monitors access to the disk drive and calls its own routine to call the disk drive if no access is made within a predetermined time. It may be used to put the drive into a power saving mode. Using a keyboard controller to manage the power consumption of disk drives and other peripherals will avoid many of the problems described above for CPU interrupt driven methods for power management. However, since the 8042 is not normally connected to all address lines of the I / O bus (it only receives the chip select signal KBDC # generated by the chipset and SA (1: 0)), Extended external logic is required to monitor signal-related addressing events for. 8042
Issued commands across the I / O bus to peripherals would require additional expansion logic. The use of a keyboard controller for power management control is also inadequate because each individual disk drive or other peripheral device requires its own unique power management code. For each replacement in the system, another 8 each with its own uniquely programmed ROM
A 042 keyboard controller is required. Since any of a number of different types of disk drives or other peripheral devices may be inserted into any given system, any given 8042 may be such a ROM.
It would be difficult or impossible to achieve the huge output needed to economically manufacture a base microcontroller. A version of 8042 (87
42) can be used with EPROM instead of ROM, but this device is expensive and rarely used.

(Summary of the Invention) According to the present invention, a power management device is a CP
Separate from the U instruction sequencer, it includes a power management sequencer that orders the power management instructions available through the I / O bus. These instructions are stored in the BIOS EPROM and thus can be customized by the manufacturer to include the specific power management instructions required for each peripheral included in the system. BIOS
And a computer manufacturer, because such a BIOS EPROM can be included anywhere as needed, except for the purpose of including an appropriate initialization routine for each particular peripheral combination installed. Has no additional cost. Furthermore, this power management sequencer can be integrated into one of the chips in a chipset, thus:
There is no need to increase the number of integrated circuit chips required to be incorporated into the system. This concept can be extended to peripheral management functions that are independent of power.

DETAILED DESCRIPTION FIG. 1 is a block diagram illustrating various functions of an IBM PC AT compatible computer of a type that may include an embodiment of the present invention. This is CPU10
(Eg, Intel 80386). This CPU 10 is connected to the local bus 12,
This local bus has 32 data lines (CD
(31: 0)) and 24 address lines (CA
(25: 2)) and four byte enable lines (BE (3: 0)). The address space directly addressable through the local bus is 64 MB long. The upper 24 bits (sufficient to identify a 4-byte word) are present on line CA (25: 2), and a particular byte within the specified word is a 4-byte enable line BE (3: 0) is used for identification. The local bus also contains additional control lines. Most of this control line is omitted in FIG. 1 for simplicity. The computer of FIG. 1 has a coprocessor 1 connected to a local bus 12 and a CPU 10.
4 (eg, Intel 80387). The computer of FIG.
It also includes an I / O interface circuit 20 connected between the bus 12 and the I / O bus 22. The interface circuit 20 may actually be divided into two or more chips in a chipset, but the division of functions between the various chips in such a chipset is not critical to the invention. .. In addition to the circuit configuration for interfacing between the local bus and the I / O bus, the interface circuit 20 includes a 14.3 MHz clock, a reset control unit, an interface to a real time clock (RTC), and a keyboard controller. To the coprocessor 14, the interface to the DRAM main memory, and the interface to the cache. cache·
The interface connects to cache memory unit 34 through line 32. The cache memory unit is the data line C on the local bus 12.
It is connected to D (31: 0). Interface circuit 2
0 is the data line CD (3
1: 0), the address lines CA (25: 2) and the byte enable lines BE (3: 0), and the CPU 10 via various control lines 24.
Is also connected to. The interface circuit 20 is also connected to the coprocessor 14 via various control lines 26. As will be apparent later, the interface circuit 20 also includes a power management unit (PMU) according to the present invention. The DRAM main memory interface portion of interface circuit 20 may be up to 64 megabytes long DR
Addressing information is provided through lines 28 to banks of AM main memory 30. DRAM main memory 30
Is a data line CD (31:
Bidirectional connection to 0). The I / O bus 22 includes address lines SA (19: 0), LA (23:17) (herein collectively referred to as SA (23: 0)) and data lines.
Line SD (15: 0). Like the local bus 12, there are many control lines on the I / O bus 22, which are omitted in FIG. 1 for simplicity.
The interface circuit 20 includes address lines, data
It is connected to both lines (SA, SD). Some peripheral devices may be connected to the I / O bus 22.
For example, an IDE disk drive controller, such as 40, may be connected to the address and data lines of I / O bus 22, similar to LCD display controller 42. These two special peripherals are shown in FIG. 1 because they are useful subjects of power management. Also connected to the I / O bus 22 is a keyboard controller 44, which is a programmed Int.
el 8024. Such a device is commercially available from Phoenix Tech, Norwood, Massachusetts.
It can be purchased from companies such as Nologies in a pre-programmed form to act as a keyboard controller. Real-time clock (RT
C) is the lower eight data lines SD of the I / O bus 22, similar to the EPROM 48 and the SYSRAM 50.
It is also connected to (7: 0). EPROM 48 is I /
Lower 17 address bits SA (1
6: 0) and also includes the system BIOS. As will become apparent, EPROM 48 may also include power management code according to the present invention. The EPROM 48 is logically a main memory at addresses E0000-FFFFF.
It is in the address space and, as mentioned earlier, the EP
ROM BIOS is DRA as part of the boot procedure.
M main memory 30 may be copied. SYSRAN5
0 is a battery-backed SR up to 32 Kbytes
It is an AM array. In the example of FIG. 1, 8 Kbytes of SYS
It contains only RAM and receives only the lower 13 address bits SA (12: 0) of the I / O bus 22. S
The YSRAM 50 is logically C0000h-FFFF.
It is located in the main memory address space of any user-selectable 32 Kbyte block from Fh.
When the I / O space image buffer function is enabled (index of interface circuit 20
(By setting 1 bit in one of the registers), the least significant 1 Kbyte of SYSRAM 50 is the I / O address location 000 if it is write only.
h. 3FFh, where the entire AT I / O address space is copied, including the I / O peripheral command and control registers. Any command, write access to the control register in this I / O address space will also be written to the corresponding location in SYSRAM 50. Thus
If the power to one or more of the peripherals is intentionally cut off due to a power outage or power management, the system reads the state of these registers from SYSRAM50 and writes them back to the peripherals. The register state can always be resumed. In other systems, the I / O space image buffer is located logically (for read access), exclusively in the I / O address space, or selectively I / O.
It may be located in the address space or the main memory address space. The interface circuit 20 also sends a signal SYSR
AMCS # is given, EPROM 48 is given a chip select signal ROMCS #, and keyboard controller 4
4 to the chip select signal KBDCS #. Note that in some systems, some of the above peripherals (eg, IDE controller 40 and LCD display controller 42) are isolated from other peripherals by buffers. This buffer is provided to ensure sufficient drive current for the two controllers (and any other peripherals inserted in the add-in slots) and is "on the I / O bus". It does not change the characteristics of these peripherals. In operation, immediately after power-on or reset, the CPU 10 issues a fetch for an instruction located at the lower 15 bytes of the uppermost address of the main memory. Interface circuit 20 decodes this access and returns a jump instruction to the base address of EPROM 48. The CPU 10 then proceeds to the EPROM 48
And perform various self-test and initialization routines. For all these accesses, the CPU
The instruction fetch address is placed on the local bus and interface circuit 20 decides to decode the CPU fetch address and write it to EPROM 48. Interface circuit 20 then sends the address onto address lines SA (23: 0) of I / O bus 22 to energize ROMCS #. The interface circuit 20 also includes the data lines SD of the I / O bus 22.
Assemble the 1-byte wide instructions and data returned from EPROM 48 on (7: 0) into a 32-bit word and drive them onto local bus 12 data lines CD (31: 0). Also, EPROM 48
At some point during the initialization sequence running from
The PROM code is sent to the CPU 10 by the B from the I / O bus.
Causes the IOS routine to be copied to the corresponding shadow memory location in DRAM main memory 30. Thus, the operating system for these BIOS routines
Calls by the system can proceed faster than if the routine stays only in ROM on the I / O bus. The power management routine, as described below,
It may be included in the OM 48 but need not be copied to the main memory 30. At some point during the initialization sequence, the operating system is loaded into main memory 30. Control is transferred to the operating system when the initialization sequence is complete. Other parts of the initialization sequence related to power management will be described later. 2 and 3 show main internal functional units of the two chips 100 and 200 in the chipset included in the interface circuit 20 (FIG. 1). The identification of the various pins of these chips is also shown in FIGS.
In these figures, the pin names written inside the arrows pointing to the chips 100 and 200 are the inputs to the chips, and the names of the arrows pointing away from the chips 100 and 200, respectively. The pin name written inside is the output from the chip. Chip 10
The pin names inside the arrows pointing in both directions for each of 0 and 200 are bidirectional pins for the chip. As can be seen in FIG.
Is a CPU interface, a coprocessor interface, an interface leading to the chip 200, a cache interface, a DRAM interface, an I / O
Bus interface and power management unit (PM
U) 110. Similarly, as shown in FIG. 3, the chip 200 has a CPU interface, an interface leading to the chip 100, a 14.3 MHz clock, a reset control unit, an I / O bus interface, microprocessors D (31: 0) and SD ( 15: 0) data buffer, two 8-bit DMA controllers, two interrupt controllers, timer / counters,
It includes a real time clock (RTC) interface and a keyboard interface. The function of each pin on the two chips 100, 200 is shown in Tables I and II below.
A brief explanation will be given with reference to. Detailed descriptions of individual functional units are not necessary for an understanding of the present invention and are omitted for simplification. Only the features of the functional units that are most relevant to the invention will be described in detail below.

Chips 100, 200 operate in response to a number of commands and configuration registers that can be written to or read from the CPU. To access the index register, the CPU first writes the index number to the I / O port, eg, 22h, then the data to another I / O port, eg, 2h.
Must be read from or written to 4h. The fields of the register are shown in FIGS. 6-9, and only the index register most relevant to the present invention is described in detail below. 6 to 9,
Double hyphens in the field indicate an inverted bit. The index registers are as follows:

30 (7: 6) Chip 100 Rev. No. 30 (5: 3) AT Bus Clock Select 0 0 0 8 MHz 0 0 1 6 MHz 0 1 0 4 MHz 0 1 1 1 10 MHz 1 x x 5 MHz 30 (2) '1' = Special wait state in AT cycle. '0' = non-special wait state.

30 (1) Keyboard reset control. '1' is C
A stop command is required before PURST occurs. '0' is
Does not require a stop order.

30 (0) Alternative rapid reset. '1' is enabled. '0' is disabled.

31 (7) '1' is an enable PMU. '0' is disabled. Must be maintained at '1'.

31 (6) '1' is enable ROMCS # C0000-C7FFF. '0' is disabled.

31 (5) '0' enables parity check. '1' disabled.

31 (4) '1' enables cache. '0'
Is disabled. 31 (3: 2) cache size 0 0 32K 0 1 64K 1 0 128K 1 1 256K 31 (1: 0) cache wait state 0 0 reserved 0 1 0 ws 1 0 1 ws 1 1 0 ws standing Has a falling delay.

32 (7) F block control. '1' is for reading from ROMCS # and writing to DRAM. '0' is read-only. Not writable.

32 (6) D block control. '1' is shadow enable. '0' is shadow disable.

32 (5) E block control. '1' is shadow enable and ROMCS # is disabled. '0' is ROM
CS # enable.

32 (4) D block shadow write control. ′
1'is not writable, '0' is writable.

32 (3) E block shadow write control. ′
l'is not writable, '0' is writable.

32 (1) Alternative rapid Gate A20. '1' is enabled and '0' is disabled.

32 (0) '1' Single ALE during bus conversion, '0' is multiple ALE.

Support coupling system and video BIOS, ROMCS #
Are F blocks only, F and E blocks, or F and E8000-EFFFF and C0000-C7F.
Can be set to FF.

Set to F block only: 32 (7) = 1, 32
(5) = 1 31 (6) = 0 Set to F and E blocks: 32 (7) = 1, 32
(5) = 0, 31 (6) = 0 Set to F, E, C blocks: 32 (7) = 1, 32
(5) = 0, 31 (6) = 1 33 (7) Shadow EC000-EFFFF, '1' enable, '0' disable 33 (6) Shadow E8000-EBFFF'1 'enable,' 0 'disable 33 (5) Shadow E4000-E7FFF'1 'enable,' 0 'disable 33 (4) Shadow E0000-E3FFF'1' enable, '0' disable 33 (3) Shadow DC000-DFFFF'1 'enable,' 0 'Disable 33 (2) Shadow D8000-DBFFF'1' Enable, '0' Disable 33 (1) Shadow D4000-D7FFF'1 'Enable,' 0 'Disable 33 (0) Shadow D0000-D3FFF'1' Enable, '0' disabled 4 (3) reserved 34 (7: 4) DRAM configuration, banks 0 and 1 34 (2: 0) DRAM configuration, banks 2, 3 35 (7: 6) DRAM read wait state 0 0 Reserved 0 1 1 additional ws, (base ws is 3) 1 0 1 additional ws 1 1 2 additional ws 35 (5: 4) DRAM write wait state 0 0 0 addition ws, (base ws is 2) 0 1 1 addition ws 1 0 2 addition ws 1 1 3 addition ws 35 (3) reserved 35 (2) reserved 35 (1) '0' can be DRAM cached Area can be used. "1" makes the entire DRAM non-cacheable.

35 (0) C0000-C7FFF cache available. ′
0'cache enabled, '1' cache disabled.

36 (7) F block write control. '1' write enabled, '0' write disabled. This bit is 32 (7)
Is 0, it means don't care.

36 (6) C0000-EFFFF control. '0'AT
Read from R / W and '1'AT by bus and write to DRAM.

36 (5) C block shadow write control. ′
1'writable, '0' writable.

36 (4) C block control. '1' shadow enable, '0' shadow disable.

36 (3) Shadow CC000-CFFFF, '1' enable, '0' disable 36 (2) Shadow C8000-CBFFF, '1' enable, '0' disable 36 (1) Shadow C4000-C7FFF, '1' Enable, '0' Disable 36 (0) Shadow C0000-C3FFF '1' Enable, '0' Disable 37 (7: 6) Reserved 37 (5: 4) Reserved 37 (3: 0) Cache enabled Address area: 0000 0-64 Mb 0001 0-4 Mb 0010 0-8 Mb 0011 0-12 Mb 0100 0-16 Mb 0101 0-20 Mb 0110 0-24 Mb 0111 0-28 Mb 1000 0-32 Mb 1001 0 -36 Mb 1010 0-40 Mb 1011 0-44 Mb 1100 0-48 Mb 1101 0-52 Mb 1110 0-56 Mb 1111 0-60 Mb Note: For a 1.32K cache, the maximum cacheable address area is 0-8Mb.

In the case of a 2.64K cache, the maximum cacheable address area is 0-16Mb.

For a 3.128K cache, the maximum cacheable address area is 0-32Mb.

For a 4.256K cache, the maximum cacheable address area is 0-64Mb.

The 5.640K-1M memory area is non-cacheable except C0000h-C8000h which is controlled by another register bit.

Index register 38 (non-cacheable block 1) is used with index 39 to form a non-cacheable block. The non-cacheable block's starting address must have the same granularity as the block size. For example, if a 512Kb non-cacheable block is chosen, its starting address is a multiple of 512K. As a result, only the A19-A23 address bits have meaning and A16-A18 are "don't cares."

38 (7: 5) Size of non-cacheable memory block 1 (64K, 128K, 256K, 512K or unusable) Default = unusable 38 (4: 2) Unused 38 (1: 0) Non-cacheable memory block 1 A25 and A24 address bits. Default = 00 39 (7: 0) Non-cacheable block 1 index 39 Index registers 3A, 3B are n. c. b. The case of 2 is similar to the indexes 38 and 39. Power management register index registers 44-47 contain timers for four peripherals. Once started, each timer will restart whenever there is access to the address assigned to the corresponding peripheral. pw
The r-1cd timer and port pins control the power to the LCD backlight and LCD panel and access to memory address A0000-BFFFF (display memory) or I / O address 3B0.3dF (command and configuration register). The timer is restarted every time. The pwr_drV timer and port pin control the power to the floppy, IDE drive and this timer is restarted on every access to the I / O address 1FX-3FX. Of these addresses, the actually meaningful address is the I / O address 3F0-3F5h or 3F7, I for accessing the floppy drive.
3F6 or 3F7h for DE drive access
However, a larger area is used for ease of decoding. The pwr_kbd timer and port pin control the power to the keyboard. This timer is
It is restarted each time the / O address 60-67h is accessed. The pwr_gnr timer and port pin control the power to the peripheral defined device. A user-defined address area (described below) is also checked for access. The PWR_XXX pin means can be turned off bit by bit using the index registers 41, 43h. The clock source for each timer has several frequencies SQW covering different areas.
It can be selected from (3: 0). If the normal power management method (CPU interrupt driven method) is selected when the timer times out, an SNMI is generated and the CPU software can turn off the pin. When the device is next accessed, the interface circuit 2
A 0 again generates an SNMI, causing the software to turn on the pin. The CPU of the index 41 is PWR_
Allow writing directly to the xxxport pins. 41
The bits written to (7: 4) act as a write mask for the corresponding bits of 41 (3: 0). "1" of 41 (7: 4) corresponds to 41 (3:
Enables writing to port pin 0).

41 (3: 0): read / write data, bit 0 for PWR_LCD pin bit 1 for PWR_DRV pin bit 2 for PWR_KBD pin bit 3 for PWR_GNR pin index 42 for each of the 4 timers All timer clocks selected from SQW (3: 0) are: 42 (7: 6): Timer clock source for pwr_gnr timer 42 (5: 4): For pwr_kbd timer Timer clock source 42 (3: 2): Timer clock source for pwr_drv timer 42 (1: 0): Timer clock source for pwr_lcd timer Index 43 is assigned to each pin when the corresponding timer times out. Display whether to write. Yes bit "1" means a low bit write to the pin,
The high bit “0” means that access to the pin is prohibited.

43 (7: 6): Automatic write to pwr_gnr pin upon timeout 43 (5: 4): Automatic write to pwr_kbd pin upon timeout 43 (3: 2): Automatic write to pwr_drv pin upon timeout 43 (1: 0) ): Auto write on pwr_lcd pin on timeout These timers are contained in index registers 44-47.

44 (7: 0): timer for pwr_lcd 45 (7: 0): timer for pwr_drv 46 (7: 0): timer for pwr_kbd 47 (7: 0): timer for pwr_gnr Timeout is enabled , The port pin for that timer is set by the interface circuit 20. In the conventional (CPU interrupt driven) power management method, the interface circuit 20 generates an SNMI for the CPU. (In this sequencer method, code sequences are processed by the PMU itself without interrupting the CPU.)
The service routine can turn off the corresponding PWR_XXX pin or send a command to the corresponding peripheral to activate the power saving mode. The next time the I / O accesses the device, the interface circuit recognizes it and returns READY without causing the corresponding AT bus cycle. Instead, the I / O address, data, m / io, r / w and byte enable information are latched in index registers 60-66h and another SNMI is generated for the CPU. CP
The U service routine then issues the appropriate command to turn off the peripheral power and wait a predetermined amount of time depending on when the device is supposed to power up, and then from index registers 60-66h. Reads the latched information, and based on the latched information, I / O bus
Re-execute the cycle. 16 bits of data or 3
In order to latch 2 bits, the interface circuit 20
Performs a bus conversion cycle. This is because the power management device is provided with only data bits 7: 0.
Index registers 48, 49 are PWR_GNR
Defines timer and port pin behavior. PWR_G
The NR pin will change state when there is no activity in the programmable I / O space for a period of time. The operation is similar to the PWR_XXX pin, but with programmable I / O space that is to be monitored. The fields of index registers 48, 49 are defined as follows.

48 (7: 0) defines the I / O base address A (8: 1) to be monitored. A (O) is never monitored.

49 (7) I / O base address A (9) 49 (6) '1' enables comparison in WRITE cycle and '0' inhibits comparison in WRITE cycle.

49 (5) '1' enables comparison in READ cycle and '0' prohibits comparison in READ cycle.

49 (4: 0) I / O address A (5: 1) mask
bit. When it is '1', 48 (4: 0) corresponding bits are not compared. This is used to define the I / O address block size to monitor.

In addition, the interface circuit 20 has eight peripheral device power (PPWR) pins that control the power supply to the peripheral device. Each pin is associated with a register bit in index register 54 or 55. The other bits in these registers act as write masks as follows.

54 (7: 4): write mask for writing to PPWR (3: 0). "1" enables writing to the corresponding bits of 54 (3: 0).

54 (3: 0): Read / write data bits for PPWR (3: 0).

55 (7: 4): Write mask for writing to PPWR (7: 4). "1" enables writing to the corresponding bits of 55 (3: 0).

55 (3: 0): PPWR (7: 4) read / write data bits.

The various power add management interrupts are controlled through the bits of index register 40.

40 (7) This bit is read only. '1'
Indicates that the last read or fetch from address XXXFFFF0 was an SMIADS # cycle, and '0' means it was a normal ADS # cycle.

40 (6) Reserved 40 (5: 4) low_bat and low_ba
t Pin polarity for power management input pin. '0' is high active and '1' is low active.

40 (3) Write "0" to this bit to set SQW
Indicate that the IN pin is the 8khz clock. ′
1'means 32 khz clock.

40 (2: 0) NMI (2: 0) pin polarity for input. '0' is high active and '1' is low active.

As described in more detail below, the sequence code for use with the power management sequencer in PMU 110 is stored in a 1 kbyte segment in ROM or SYSRAM. The base for this code
The address is stored in the write-only register of the chip 200. Only 17:10 is stored as the bits of the sequence base address. This is necessary and sufficient to define a 1 kbyte segment.

51 (7: 0): Sequence code base address A (17:10). The sequence is C in either ROM or battery-backed SYSRAM.
It can be in any 1 Kbyte segment of the F block.

52 (7) This indicates whether the code is in ROM or SYSRAM. '1' indicates SYSRAM, and '
0'indicates ROM.

52 (6) Reserved 52 (5) '0' allows the lower 1K of up to 32K bytes of SYSRAM to act as an I / O space image buffer. When possible,
All writes to I / O address are in SYSRAM
Is copied to the corresponding location at 1K below. S
The YSRAM can then be read into the main memory address space in the usual manner. This allows the system to temporarily turn off power to peripheral devices to save power. This is possible even if this peripheral has an unreadable command or configuration register that will lose its contents. Upon resumption of power to this peripheral, the system (either the CPU or PMU operating under control of the power management sequence) simply reads the lost information from SYSRAM and rewrites it to the device. Only.

52 (4) '0' SYSRAM is writable. '1'
SYSRAM is not writable.

52 (3) Reserved 52 (2: 0) SYSRAM base address. SY
The SRAM memory is up to 32K bytes located in C0XXX-FFXXX under register selection, as shown below.

000 C0XXX 001 C8XXX 010 D0XXX 011 D8XXX 100 E0XXX 101 E8XXX 110 F0XXX 111 F8XXX Two general-purpose programmable I / O chip-select CS
The G (1: 0) # output pins are registered in register 4A as follows.
Controlled by -4Dh.

4A (7: 0) Define base I / O address for CSG0. Since address bit 0 has not been tested, it contains address bits 8: 1.

4B (7) CSG0 base address A (9).

4B (6) '1' enables comparison in WRITE access. '0' prohibits comparison by WRITE access.

4B (5) '1' enables comparison by READ access. '0' prohibits comparison by READ access.

4B (4) Specifies timing for CSG0 # output. '0' is active before ALE. '1' is I / O
It becomes active just like a command pulse.

4B (3: 0) A (4: 1) CSGO I / O address compare mask bits. When "1", 4A
Corresponding bits of (4: 0) are not compared. this is,
Used to define I / O address block size.

Same as 4C-4A.

Same as 4D-4B.

Memory Card Chip Select CSM (1: 0) #
Are controlled by the index register 53. R
When the G (1: 0) bit is '10' or '10', access to blocks A, B, C, D of memory is marked with CSML # (low byte) or CSMH # (high byte). Will be energized. Also, a regular AT bus
The commands MRD # and MWR # are never generated. Chip 100 is replaced by MCDRD # and MCDWR #
To occur.

53 (5: 0) Memory card block address. Each block is 256 Kbytes.

The interface circuit 20 includes four bidirectional parallel ports.
Includes pins PIO (3: 0). These port pins can be written by the power management sequence code or by the CPU via registers 56-57.

56 (7: 4) Write mask for PIO (3: 0). "1" means writing of the corresponding bits from 56 (3: 0) to the port, and "0" means writing prohibition.

56 (3: 0) Read / write data. When reading, the interface circuit 20 latches the data from the pin. When writing, the bit in the corresponding direction is "1"
If set to (output), data will appear on the pin at the end of the cycle.

57 (7): '1' can be refreshed. '0'
Cannot be refreshed.

57 (6: 4): Reserved 57 (3: 0): PIO (3: 0) pin direction. '1'
Means output and '0' means input.

The RI input pin to PMU 110 enables the modem ring activation function. If the RI pin change lasts longer than the number programmed in the counter, the PMI is triggered to wake up from sleep or suspend mode. R
The I input is controlled by the index register 5F as follows.

Read-only bit directly from the 5F (7) pin. AC
Indicates whether power is on (displayed by HIGH).

5F (6) Enable "1". ACPWR is High
, The chip 100 does not generate the interrupted PMI and the ACP
When WR is low, the chip 100 can generate a power saving mode transition interruption. "0" is disabled and always allows a transition to power saving mode.

5F (5) "1" enabled, INTR pin goes high and resumes if chip 100 is in suspend mode. A "0" prevents INTR from affecting the break situation.

5F (4) "1" PI counter countout will cause resume. The "0" RI counter does not affect the suspend situation.

5F (3: 0) RI Count Number Chip 100 also includes an idle timer, which can be used to determine if the entire system has been idle for a predetermined amount of time. When this timer times out, a PMI occurs. The idle timer is combined with the PWR_XXX timer, and each combination is turned on / off individually. I
The dle timer is controlled by index registers 4E-4F.

4E (7: 6) Timer clock source. SQW
It is selected from (3: 0).

4E (5: 4) Indicates whether 1pt and com ports should be monitored. A "1" means that an access to 1 pt / com will restart the idle timer, and a "0" means that the access will not affect the idle timer. 1pt address is 378-
37F or 278-27F. The com address is 3F8-3FF or 2F8-2FF.

4E (3: 0): Indicates whether the pwr_xxx port should be monitored. '1' means that access to the port is I
It means restart the dle timer, and '0' means Id
This means that access does not affect the le timer.

4F (7: 0): Idle Timer As will become apparent, the CPU may initiate a power management sequence with any 16 byte code block of sequence code. This is done by writing the block address to index register 5E as follows.

5E (7) This bit is write-only and is '1'
When is written, the sequence starts.

5E (6) Reserved 5E (5: 0) Start address A (9: 4) that specifies one of 64 code blocks. Since each block is 16 bytes long, A (3: 0) always starts at 0.

The register 50 has various functions.

50 (7: 6) Chip 200 revision number 50 (5) Polarity selection for IRQ8. '0' is low active and '1' is high active.

50 (4: 3) Turns on and off the 14.3 MHz clock. This clock is turned off to save power.
When this clock is on, bit 4 must first be set to '1'. When this clock is turned off, bit 3 is set to "0" and bit 4 is set to "0" in the next cycle.

50 (2) Resume Ready (RTR) bit. This bit is automatically set to '1' at the beginning of resume, indicating that the resume program is ready to execute.

50 (1) PMU mode. This read-only bit contains '1' if it is '0' in suspend mode.

50 (0) Interrupt mode is started by writing this bit to '1'. Nothing happens with writing '0'. Always read '0'.

As mentioned above, index registers 60-66h
Latches information from the last I / O access when there is an attempt to access the peripheral in power save mode. This information is included as follows:

60 (7: 0) Latched D (7: 0) 61 (7: 0) Latched D (15: 8) 62 (7: 0) Latched D (23:16) 63 (7: 0) Latched D (31: 24) 64 (7: 2) Latched A (7: 2) 64 (1) Latched MIO 64 (0) Latched wr / rd 65 (7: 0) Latched A (15: 8) 66 (7: 4) Latched A (19:16) 66 (3: 0) Latched BE (3: 0) The index register 67h describes some system condition.

67 (7) '0' means a static characteristic CPU. In suspend mode, chip 100 stops the CPU clock. '1' means it is a dynamic CPU. In suspend mode, CPU clock is 1
Divided by zero.

67 (6) "1" row refresh, "0" regular refresh.

67 (5: 2) Reserved 67 (1: 0) CPU Clock Frequency Select 0 0/1 0 1 AT Bus Clock 1 0/10 1 1 Stop As revealed after, PMU 110 has 16 power managements. It contains an interrupt (PMI) source. These sources are defined as follows. Where NMI
Note that O can only generate NMI to the CPU and cannot start the sequence.

# 0-LLOW_BAT pin # 1-NMI1 pin # 2-NMI2 pin # 3-LOW_BAT pin # 4-IDLE_TMR timeout # 5-RI or INTR pin. The INTR pin is only enabled in suspend mode. In that case, IN
The TR pin is the same as the RI pin that initiates the resume action.

# 6-RESUME # 7-SUSPEND # 8-LCD_TIMER # 9-DSK_TIMER # 10-KBD_TIMER # 11-GNR_TIMER # 12-LCD_ACCESS # 13-DSK_ACCESS_15-ESK_CS-CSK_AC-CS ## 5
It is configured through Bh.

58 (7: 6) Configuration for PMI Source # 3 (LOW_TAT Pin) 0 0 Disable this PMI.

0 1 Starts the sequence when this PMI is activated.

1 0 Activates the SMI pin when this PMI is activated.

1 1 Mask the SMI.

58 (5: 4) Configuration for PMI Source # 2 58 (3: 2) Configuration for PMI Source # 1 58 (1: 0) Configuration for PMI Source # 0 59 (7: 6) Unused 59 (5: 4) Configuration for PMI Source # 6 59 (3: 2) Configuration for PMI Source # 5 59 (1: 0) PMI (Because Suspend and Resume must be configured the same way) Configuration for Source # 4 5A (7: 6) Configuration for PMI Source # 11 5A (5: 4) Configuration for PMI Source # 10 5A (3: 2) Configuration for PMI Source # 9 5A (1: 0) Configuration for PMI Source # 8 5B (3) PMI Source # 5 is enabled and then the configuration of Source # 11 is followed.

5B (2) Enable PMI source # 14, then follow configuration of source # 10.

5B (1) PMI source # 13 is enabled, at which time the configuration of source # 9 is followed.

5B (0) PMI source # 12 is enabled, at which time the source # 8 configuration is followed.

5B (4) Reserved 5B (5) '1' enables sequences and '
0'disables all sequences.

5B (6) '1' Mask all SMIs. '0' enables SMI.

5B (7) '1' SNMI pin is CPU NMI
Moved to. '0' SNMI pin is changed to CPU SMI.

The index registers 5C, 5D indicate which of the PMIs was interrupted by the CPU. The NMI / SMI service routine reads these registers to determine which power management interrupt handler to go to. Writing a '1' to one of these bits will clear it if it was active. Writing '0' has no effect. Only one of these bits can be cleared at a time. Internal data and control paths used to execute the power management sequence from the EPROM or SYSRAM in the PMU 110 (FIG. 2) are described below with reference to FIG. This figure is
It has been simplified for better understanding of the invention.
The PMU 110, as described in more detail below,
It includes a plurality of 8-bit registers adapted to receive and latch various bytes of a 6-byte sequence code command group. In particular, the chip 10
0 SD (7: 0) pin derived SDIN (7:
0) The data bus is the operand (OP) register 31
0, select (SEL) register 312, first I / O command register 314, second I / O command register 316, I / O command data register 318,
Timer register 320, index register 32
A few, three 4-bit port registers 324, 32
6, 328 and other registers (not shown). port. Registers 324, 326, 32
Each of the 4 bits of 8 is clocked individually for each of the reasons described below, each of which is the SDI as data.
Receive only N (6, 4, 2, 0). As will be seen later, the data from the second, third and fourth bytes of the 5 byte sequencer code command is selectively
I / O command, data registers 314, 316, 3
18 or port registers 324, 326,
Is written to 328. The lower 6 bits (indicated by OP (5: 0)) of the OP register 310 are connected to the first input port of the 3-input 6-bit wide multiplexer 330. The second input port of the multiplexer 330 is 5
6 of index register 5Eh indicated by E (5: 0)
Connected to receive the two lower output bits. Bits 3: 0 of the third input port of the multiplexer 330
Are connected to receive the output of the 16-line to 4-line interrupt encoder 332. Multiplexer 3
The upper two bits of the third input port of 30 are connected to logic zero. The 6-bit output of multiplexer 330 is concatenated with the upper bits above the 4-bit output of 4-bit counter 331 and the 10-bit result is sent to the first input port of 10-bit wide 2-input multiplexer 333. Similarly, the first I / O command register 314
Lower two bits of the second I / O command register 31
Connected to the high order bits above 6 output bits of 6, the 10 bit result is sent to the second input port of multiplexer 333. The 10-bit output of multiplexer 333 is sent to the lower bits 8 bits below the sequence base address register 335 (which is the index register 51h). 18-bit result is I / O bus 22
Configure the SAOUT (17: 0) sequence address to be added to the SA line. The encoder 322 is
PMI from 16 available PMU interrupt sources
It has 16 input lines connected to receive (15: 0). These interrupt sources are two low battery pins (LLOW_BAT, LOW_BAT).
And two NMI pins (NMI1, NMI2) [NMI
0 can cause an NMI output to the CPU, but cannot initiate a PMU sequence]
And idle timer timeout (IDEL_TM
R) and the modem ring input (RI pin) [also this
Energized by a signal on the INTR pin when the system is in suspend mode], SUSPEND, REJ
UME inputs (both from keyboard suspend / resume switch) and timeout indicators (LCD_TIMER, DS) from four device specific timers
K_TIMER, KBD_TIMER and GNR_T
IMER) and four signals (LCD_ACCESS, each indicating access request to the same four devices).
DSK_ACCESS, KBD_ACCESS, GNR
_ACCESS). I / O command data
The 8-bit output part of the register 318 is an octal 2-input AND
Connected to the eight inverting inputs of gate 334, the other eight inputs are non-inverting and connected to SDIN (7: 0). The outputs of the eight AND gates 334 are connected to the data inputs of the 4 deep temporary register file 336. The 2-bit select input portion of this temporary register file 336 is the first I / O command
TMPSEL field of register 314 (bit 3:
2) is connected to receive. Temporary register
The eight outputs of the file 336 are the eight OR gates 3.
One input of each of the 38 is connected to the other input, and the other input is connected to receive the output of the I / O command data register 318. The eight outputs of the OR gate 338 are connected to one input port of the 2-input 8-bit wide multiplexer 340. The second input port of multiplexer 340 is connected to receive eight I / O command data register 318 output bits. The SAOUT (17: 0) signals described above are sequentially multiplexed with other sources (by means not shown) and SA (17 :) of the chip 100 as an output.
0) given to pin. Similarly, multiplexer 340
Output SDOUT (7: 0) of is further multiplexed with other sources (by means not shown) and provided as output to the SD (7: 0) pins of chip 100. The clock inputs for operand register 310 and SEL register 312 receive the Latch0 and Latch1 signals, respectively. These Latch 0, Latch 1 signals are generated by the control unit 350 of the PMU 110 and latch on a byte of the PMU sequence being retrieved from the EPROM or SYSRAM (sequence base address register index 51h). dependent upon). The control unit 350 also
Latch 2, latch 3, latch 4, and latch 5 signals are also generated. The Latch 2 signal is sent to one input of AND gate 352 and its output is sent to the clock input of the first I / O command register 314. The latch 3 signal is sent to one input of AND gate 354 and its output is sent to the clock input of the second I / O command register 316. Latch 4 signal is AND gate 354
Of the I / O command.
It is sent to the clock input of the data register 318.
The second of each of the AND gates 352, 354, 356
All inputs are connected to each other is there. The Latch 2 signal is also indicated generally at 362 by 4
It is sent to one input of each of the AND gates and its output is sent to the respective clock input of the individually clocked bits of the port register 324. Similarly,
Latch 3 signal is four AND's, generally indicated at 364.
Sent to each of the gates, the output of which is sent to the respective clock input of the individually clocked bits of the port register 326. Latch 4 signal is generally 366
To each of the four AND gates, indicated by, and their outputs are sent to the respective clock inputs of the individually clocked bits of port register 328. Four A
The second input of each of the ND gates 362 is connected to receive each of the data lines SD (7, 5, 3, 1). Therefore, SD (6, 4, 2, 0)
, The corresponding bit of SD (7,5,3,1) is high only when P
It will be timed to PWR (3: 0). Similarly, 4
The second input of each of the four AND gates 364 is connected to receive each of the data lines SD (7, 5, 3, 1), and the second input of each of the four AND gates 366 is , Data lines SD (7, 5,
It is connected so as to receive each of 3, 1). A
The third inputs of each of the ND gates 362, 364, 366 are all connected together and are Receive the signal. The Latch5 signal generated by control unit 350 is sent to the clock input of timer register 320. The control unit 350 also includes a counter 33
1 and various signals (not shown) for controlling the PMU 110. Wdekode 5E
The signal is generated elsewhere by means not shown. The index register 5Eh serves as a mechanism for causing the CPU 10 to start one sequence at the beginning of any desired sequence code block. PMU in Figure 4
Before explaining the operation of the above, it is helpful to understand the PMU sequence code format. Sequence for operating the power management unit using the sequencer method
The code makes up a 1 Kbyte block in either EPROM 48 or SYSRAM 50 (FIG. 1). The base address for this 1 Kbyte block is
During initialization, it is set in the sequencer base address register (index 51h) of the interface circuit 20. In particular, this register is provided in the chip 200 (FIG. 3) and outputs to SA via pins SA (17:10) and to the SA bus via pins SA (9: 0) of chip 100. Sequencer address SAOU
It is connected to the lower 10 bits of T (9: 0). Figure 5
Figure 2 shows a 1 Kbyte format breakdown of sequence code. The byte addresses shown in FIG. 5 are for the sequencer base address.
The 1 Kbyte area of the sequence code consists of 64 16
It is divided into byte sequence code blocks. The first 16 of these blocks (address 0
0-F0) configures entry points for 16 available power management interrupts. Each power management interrupt occurs on each of the first 16 sequence clocks. As will be appreciated, if more than 17 bytes are required to handle one power management interrupt, the sequence may continue in any of blocks 10-3F. As shown in FIG. 5, one sequence block consists of one opcode followed by three opcodes.
It consists of five 5-byte commands. Each of the 5-byte commands includes a select byte S, three command or port bytes C / P ₁ and a timer byte T. The interpretation of the various bytes within the sequence block is shown schematically in Table III below.

Control unit 350 causes each C ₁ / C ₂ / C ₃ command to be executed after the last byte has been loaded into that register.

If S (5) = 0 (port): P ₁ (7,5,3,1) = mask for writing data to PPWR (3: 0) P ₁ (6,4,2,0) = Mask for writing data to PPWR (3: 0) if corresponding mask bit is 1 P ₂ (7, 5, 3, 1) = Mask P for writing data to PPWR (7: 4) ₂ (6,4,2,0) = mask for writing data to PPWR (7: 4) if the corresponding mask bit is 1 P ₃ (7,5,3,1) = PIO (3: Mask for writing data to 0) P ₃ (6, 4, 2, 0) = Mask for writing data to PIO (3: 0) if the corresponding mask bit is 1 PIO (3: 0) Depends on the respective index register 57h bits 3: 0, Can be selected as input or output. T (7: 0) -Initial value to be loaded into the 8-bit timer counter. Force a delay while processing the sequence code after the current 5-byte command is completed.
All zeros indicate no delay. In operation, CP
Suppose U10 is legitimately executing an external source (not shown) signal on NMI (2) to invoke the reduced power mode of the IDE drive on I / O bus 22. If conventional power management methods are used, that is, bits 5: 4 of index register 58h is 1
If it contains 0, this interrupt is
CPU10 NMI (or SM via the above SNMI pin
I) It is only passed through the inputs. Next, the CPU 10
A procedure is taken to read the index registers 5Ch and 5Dh to vector the power management routine which first determines the source of the interrupt, and then invoke the reduced power mode of the IDE drive. CPU1 if the sequencer method is selected (bits 5: 4 of index register 58h equal to 01)
Zero is never interrupted. Instead, NMI (2)
Fires one of the PMIs (15: 0) to the encoder 332 (FIG. 4), thereby encoding a 4-bit value. Two bits of zeros are attached to the high end of the 4-bit code, resulting in a number in the OF range. In response to a signal (not shown) from the control unit 350, the multiplexer 330 outputs this number to the upper bit above the 4-bit output of the counter 331, initially setting it to zero. The multiplexer 333 selects a combination 10-bit address to be combined with the sequence base address register by means (not shown), outputs it to the SA line of the I / O bus 22, and causes the interface circuit 20 to start from the specified address. Execute the read 1 byte. The data is SD (7:
0) When it's ready above, it's SDIN
Appearing on (7: 0) (FIG. 4), control unit 350 issues a crow on the latch zero line, loading it into OP register 310. Obviously, the sequence with the external power management interrupt starts at the beginning of any of the 16 least significant 16 byte sequence blocks in the 1 Kbyte sequence code address space. After the first byte of the first 16-byte sequence code block is latched in the OP register 310, the counter 331 is repeatedly incremented, the resulting address is placed outside the SA bus and the first 5 bytes Read the command. First byte ("S" byte, 16
Byte block byte 1) is SEL register 312
Latched in. As shown in Table III, this byte bit 5 identifies whether the next three bytes are for a port register or a command register. The next byte to be read from the I / O bus is C / P ₁ . When the S (5) bits indicate that bytes 2, 3, 4 should be written to the port, C / P ₁ (7,
5, 3, 1) is PPWR (3: 0) and C / P ₁ (6,
It becomes a mask for writing (4, 2, 0). This is apparent with reference to FIG. 4, which shows SDIN
The (6,4,2,0) bits are provided as data inputs to the separately clocked registers of the port register 324 and the SDIN (7,5,3,1) bits are the latch 2 clock pulses. It is used to prevent reaching each bit of 324. S
If the mask bit in DIN (7,5,3,1) equals 1, the corresponding data bit in SDIN (6,4,2,0) is written to the corresponding bit in the register.
Otherwise, the bits in the register will remain unchanged. In addition, here Note that it prevents reaching register 324 and allows it only if the S (5) bit is set to zero. When S (5) = 1, all gates 362, 364, 366 have their respective latch
Block pulse, Latch 2, Latch 3, Latch 4, and instead feed the clock inputs of command registers 314, 316, 318. The output of the port register is
It is connected to an external power transistor that controls the power to each peripheral. C / P ₁ is port register 3
After being written to 24, the counter 331 is advanced again and C / P ₂ is read in the same way and written to the port register 326. Then the counter 331 advances again and the C / P ₃ is read across the I / O bus,
It is written to the port register 328 in the same manner. S
If (5) = 1, then the three C / P bytes are intended to be used for command registers 314, 316, 318 instead of port registers 324, 326, 328. These bytes also have different field definitions than intended for the port. These field definitions are shown in Table III. Third C
After the / P bytes have been read, the counter 331 is incremented again and the T bytes are read from the sequence memory and written to the timer register 320. First 5
After the byte command is executed, the counter 331 is again incremented to read the next 5 byte command into the register and execute it. This is then done for the third 5-byte command. The third 5-byte command completes the 16-byte block of sequence code, and if OP (7) = 0, the sequence is complete. O
If P (7) = 1, the sequence continues at another block and OP (5: 0) contains the block address with which it should continue. These bits are selected by multiplexer 330 and counter 33 selected by multiplexer 333 as the six upper bits.
Concatenated with the 4-bit output of 1 (now 0), again
Index register 51 as the 10 lower bits
Combined with the sequence base address of h. Thus, the next block of sequence code can be any of the 64 blocks of 1 Kbyte available for the sequence code. Ordering through this code continues until the block containing OP (7) = 0 is complete. While the sequence is in progress, the control unit 350 generates the SEQACC signal, which is indicated to the portion of the interface circuit 20 where the sequence is in progress. The SEQACC signal is also used to generate the SEQU output from chip 100 (FIG. 2). Before the sequence actually begins, PMU110
Inquires of the CPU interface control block of the interface circuit 20 if there is currently any activity on the I / O bus. C when the bus is clear
The PU interface control block returns a positive signal to the PMU 110 so that the sequence can begin. If the CPU attempts to perform an I / O access while the sequence is in progress, the interface circuit 20
Delay access to the I / O bus until the sequence is complete before performing the access. Since the CPU will maintain its address, the data and control signals are valid on the local bus until the READY signal is returned from the interface circuit 20 to the CPU, and power management sequence activity is completely transparent to the CPU 10. Can be. The following is the above Conner Per
A sample code segment for invoking the "standby" power saving mode of the ipherals CP3044 IDE disk drive. In this drive's standby mode, the drive slows down and most of the analog circuitry is disabled, but the drive accepts commands from the interface. To put the drive in standby mode, in a typical system, the CPU would write the command E0h to the IDE command register 1F7h after it was interrupted. To restore full power to the drive, the CPU would write the value E1h to the same command register address 1F7h after the interrupt. The following steps are performed during initialization.

-Write BF to the index 51, and the index uses the sequence code base address as EFCOO.
Set to, and therefore the sequence code is EFC
Occupy OO-EFFFFh.

Write 0 to index 52 bit 7 and set the sequence code location in ROM.

-Write 80h to index 45 and write '10'
Is written into index 42 (3: 2) and the IDE activity timer is set to 30 seconds.

-Write '10' into index 5A (3: 2) and use the sequence method (S
Configure IDE activity timer to use (instead of NMI method).

-Write "1" to the index 31 (7), PM
U110 is almost usable.

-'1 'is written in the index 5B (5), and the sequence method is almost usable.

The following code is sequence code block 9 (RO
M address EFC09). This code will send a regional command to the IDE and make it wait for 2 seconds.

"Code # 9" -16 bytes 00-Indicates the last block.

160-Set to write command, 128
Select the Hz clock source (SQW1).

221-Data E0 is transferred to I / O address 1F7h
Write in.

3 F7 4 F0 5 FF-Set the timer to 2 seconds.

600-Everything following 0 means that there are no more actions.

7 00 8 00 9 00 10 00 11 11 00 12 00 13 00 14 14 00 15 00 The following code is the sequence code block 13
(ROM address EFCOC). This code sends a Resume Full Power command to the IDE drive, waiting 7 seconds for the disk to start spinning.

"Code # 13" -16 bytes 00-Indicates the last block.

1 A0-Set to command writing, 4Hz
Select the clock source (SQW2).

221-Data E1 is transferred to I / O address 1F7h
Write in.

3 F7 4 E1 5 1C-Set timer to 7 seconds.

600-Everything following a 0 means that there is no further action.

7 00 8 00 9 00 10 00 11 00 12 00 13 00 14 00 15 00 During normal operation, when there is no activity on the IDE drive for 30 seconds, the IDE activity timer times out and PMI # 9.
Generate a power management interrupt. After checking that the I / O bus is idle, the PMU 110
At block 9, the acquisition of sequence code through the I / O bus begins. The PMU will execute that code, which will put the IDE in standby mode. On the next IDE access, PMU 110 begins sequence # 3 in a similar fashion, returning IDE to normal mode. Although the invention has been described with respect to specific embodiments thereof, it should be understood that numerous modifications and changes can be made to the embodiments described above without departing from the scope of the invention. In particular, note that the concept can be extended to include general purpose smart peripheral controllers and smart I / O bus controllers.

[Brief description of drawings]

FIG. 1 is a functional block diagram of a computer architecture embodying the present invention.

FIG. 2 is a diagram illustrating main functional blocks and external pin connections for two chips of a chipset in an interface circuit 20 of FIG.

FIG. 3 is a diagram illustrating main functional blocks and external pin connections for two chips of a chip set in the interface circuit 20 of FIG.

FIG. 4 is a block diagram of an important part of the power management apparatus as shown in FIG.

5 illustrates a memory map for instructions used with the power management system of FIG.

6 is a diagram showing command and field definitions of a control register in the interface circuit 20 of FIG.

7 is a diagram showing the field definitions of commands and control registers in the interface circuit 20 of FIG.

8 is a diagram showing command and control register field definitions in the interface circuit 20 of FIG. 1. FIG.

9 is a diagram showing command and control register field definitions in the interface circuit 20 of FIG. 1. FIG.

[Explanation of symbols]

 10 CPU 12 Local Bus 14 Coprocessor 20 Interface Circuit 22 I / O Bus 24 Control Line 26 Control Line 30 DRAM Main Memory 44 Keyboard Controller 46 Real Time Clock 48 EPROM 50 SYSRAM 100 Chip 110 Power Management Unit 200 Chip 310 Operands Registers 312 Select Registers 314 First I / O Command Registers 316 Second I / O Command Registers 318 I / O Command Data Registers 320 Timer Registers 322 Index Registers 324 4 Bit Port Registers 326 4 Bit Ports Register 328 4-bit port register 330 Multiplexer 333 Multiplexer 334 Octal 2-input AND gate To 336 4 Deep temporary register file 338 OR gate 340 2 input 8-bit wide multiplexer 350 Control unit 352 AND gate 354 AND gate

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[Procedure amendment]

[Submission date] January 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor David Lynn California 95117 San Jose Wood Creek Lane 3922

Claims (16)

[Claims] 1. A device for use in a system including a host CPU, a peripheral bus, and a peripheral device,
Means for transmitting a command issued by the host CPU to the peripheral device through the peripheral bus; and the host CP
A device separate from U and including external means for detecting a predetermined condition and issuing a predetermined command to the peripheral device through the peripheral bus in response to the predetermined condition. 2. The apparatus of claim 1, wherein said means for transmitting comprises a local bus separate from said peripheral bus. 3. The apparatus according to claim 1, wherein the transmission means makes an access request to the local bus for an address reachable only through the local bus connected to the host CPU and the peripheral bus. Interface means for sometimes detecting it and issuing a corresponding access request for said peripheral bus. 4. The apparatus of claim 3, wherein said external means further comprises signaling means for signaling said interface means during the progress of the command it issued through said peripheral bus. apparatus. 5. The apparatus according to claim 1, wherein the peripheral device has a power saving mode, and the predetermined command issued through the peripheral bus is recognized by the peripheral device as a command to activate the power saving mode. A device characterized by being performed. 6. The apparatus of claim 1, wherein the peripheral device includes means for activating a power saving mode in response to the predetermined command issued through the peripheral bus. 7. The apparatus according to claim 1, further comprising:
The external means includes a memory means for storing a code indicating how to issue the predetermined command, the external means reads the code through the peripheral bus in response to the predetermined condition, and the external means reads the code according to the code. A device comprising means for issuing the predetermined command through a peripheral bus. 8. The apparatus according to claim 1, wherein said external means further detects an additional condition and issues an additional command through said peripheral bus in response to this additional condition. Further comprising a memory means storing a first code indicating how the predetermined command should be issued and a second code indicating how the additional command should be issued, The external means reads the first code in response to the predetermined condition, reads the second code in response to the additional condition, and again which of the first and second codes is read. An apparatus comprising means for issuing a command through the peripheral bus in response to being issued. 9. A device for use in a system including a host CPU, a local bus connected to the host CPU, a plurality of devices, and a peripheral bus connected to the devices, the peripheral bus Through a memory means storing a plurality of codes each indicating how to issue a command to one of the devices, and separate from the host CPU. A plurality of predetermined conditions are detected, corresponding ones of the codes are read out through the peripheral bus in response to the predetermined conditions, and one of the devices corresponding to the corresponding one of the codes is read. An external means for issuing commands through the peripheral bus. 10. The apparatus of claim 9, wherein one of the predetermined conditions is for a predetermined time.
A device characterized in that there is no access through the peripheral bus to a predetermined address area assigned to one of the devices. 11. The device according to claim 9, wherein the external means accesses a restartable timer and a predetermined address area assigned to a specific one of the devices through the peripheral bus. Means for restarting the timer in response to the timer, and for reading the first code corresponding to the specific device from the memory means through the peripheral bus in response to the timer timing out. A device comprising means for issuing commands to the device through the peripheral bus. 12. The apparatus according to claim 11, wherein said external means further responds to an access to said predetermined address area through said peripheral bus with said second code corresponding to said specific apparatus. A device comprising means for reading from the memory over the bus and issuing another command over the peripheral bus to the particular device in response to the second code. 13. A power management device for use in a system having a separate CPU, a bus, and a plurality of peripheral devices each having a power saving mode, said means for detecting a predetermined power management state. And a means for invoking a power saving mode of one of the peripherals in response to this condition. 14. The power management apparatus according to claim 13, wherein the calling means includes means for cutting off power to the one peripheral device among the peripheral devices. 15. The power management apparatus of claim 13, wherein the one of the peripherals has a reduced power mode that can be activated by a power reduction command received through the bus, Means
A power management device comprising means for issuing the power reduction command to the one of the peripheral devices via the bus. 16. A host CPU having a CPU instruction sequencer, a local bus connected to the host CPU, an interface device connected to the local bus, and an I / O bus connected to the interface device.
A power management device for use in a system including a peripheral device connected to the I / O bus, the peripheral device having a reduced power mode that can be invoked by a command issued through the I / O bus, and A power management device adapted for use with a power down indicator signal, separate from said CPU instruction sequencer and sequenced through power management instructions in response to said power down indicator signal, A power management processor for issuing a command through the I / O bus in response to the power management command to invoke the reduced power mode of the peripheral device; and the power management command for the power management processor through the I / O bus. A power management device including a sending means.