JPH0520190A - Cache invalidation processing circuit - Google Patents

Abstract

PURPOSE:To retrieve a flash address to be invalidated at a high speed in a cache invalidation processing state in response to a vector store instruction given to a main storage. CONSTITUTION:A fact whether the data on a main storage are registered or not in a cache of each block is registered in an area valid bit register part 3 when the address area of the main storage is divided into plural blocks. If a block corresponding to a relevant store area is registered in the part 3 in response to a vector store instruction, it is decided that the address in a relevant block is stored in a cache. Then the flash processing is carried out by a flash circuit 6. Otherwise the circuit 6 carries out no flash processing if a VST deciding circuit 7 decides that the relevant address is not registered in the cache.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache invalidation processing circuit, and more particularly to a cache invalidation processing which performs a cache invalidation processing (flush processing) in response to a vector store instruction which is a continuous write request of vector data to a main memory device. It relates to a processing circuit.

[0002]

2. Description of the Related Art In a conventional cache invalidation process of this type, in response to a vector store instruction, a base address B which is a start address of a store area in a main memory, a distance D which is a distance between vector elements, and a vector. Flash index addresses B, B + D, B + 2D, B + 3D, ..., B using each information with the length L which is the number of elements
All + (L-1) D are created, and it is determined whether or not an address equivalent to the flash index address is registered in the cache.

In the above-described matching check process between the flash index address and the cache-registered address for the cache invalidation process, the area actually stored in the vector store instruction is far from the address registered in the cache. Also in this case, a flash index address is created and it is determined for each address whether cache registration has been completed.

Therefore, there is a drawback in that the flash processing in the vector store instruction consumes more time than necessary.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a cache invalidation processing circuit which can perform flush processing in a vector store instruction in the shortest possible time.

[0006]

According to the present invention, there is provided a cache invalidation processing circuit for performing cache invalidation processing in response to a vector store instruction which is a continuous write request of vector data to a main memory, An area valid bit registering unit that divides the address area on the storage device into a plurality of blocks, and indicates that the data on the main memory is registered in the cache for each block, and a store area instructed by the vector store instruction. Is registered in the area valid bit registering means as valid, and means for performing cache invalidation processing only when it is determined that the area valid bit registering means is valid. A cache invalidation processing circuit is obtained.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In this embodiment, a start / end address that creates a start / end address of the store area on the main storage device by the base address (B), distance (D), and length (L) of the store area by the VST (vector store) instruction. The creation circuit 1 and any number of bits of the address on the main memory for the data registered in the cache and the data registered in the cache are valid (usable)
Or the upper address registration unit 2 for registering valid information indicating whether it is invalid (unusable), and the address area on the main memory device is divided into arbitrary blocks, and the data on the main memory device is cached for each block. The area valid bit registering section 3 for registering the judgment valid bit indicating that it is registered, and the area valid bit for updating the valid bit information of the area valid bit registering section 3 at the same time when the peripheral of registering the data in the cache is performed. And an update circuit 4.

Further, of the start address in the VST instruction created by the start / end address creating circuit 1, the upper several bits necessary for extracting the data of the area effective bit register are set, and thereafter +1 is added every machine cycle. (If the start address value is higher than the end address value, it is -1) and the read counter 5 counts up (counts down), and the read counter 5 sequentially reads and reads all the blocks up to the end address of the VST instruction. It is determined for each machine cycle whether or not the area on the main memory used in the vector store for the block is registered, and when all blocks are not registered, the flash circuit unit 6 is stopped for cache invalidation at VST. And a VST determination circuit 7 for instructing.

As an example of the above, when the entire memory area is simply divided into four blocks, the results are as shown in FIGS. At this time, 4 blocks are represented by [00, 01, 10, 11],
In addition, each block has one valid bit for determination for valid [1] and invalid “0”.

In FIG. 2, the area [A part] registered in the cache and the store area [B in the VST instruction are shown.
1, B2 part], the start address and the end address of the store area [B2 part] in the VST instruction show 1 block [1, 1] out of 4 blocks, and the judgment of the area effective bit is made in the cache. It is only necessary to determine whether the simple block address [0, 1] registered is valid or invalid, and the valid bit information [0] read from the area valid bit registration unit for the simple block address [1, 1]. Is sent to the VST determination circuit 7, and the VST determination circuit 7 determines whether or not there is a match. Since the valid bit information is “0”, the flash circuit unit 6 is instructed to invalidate the VST process.

Similarly, regarding the B1 portion of the store area in FIG. 2, the effective bit information [1] for the simple block address [0, 1] is sent from the area effective bit registration section 3 to the VST determination circuit 7 to perform the VST determination. In the circuit 7, since the valid bit information for the simple address [0, 1] is "1", the instruction for invalidating the VST process is not issued. Therefore, the flash processing is performed in the flash circuit unit 1 as usual.

Next, in FIG. 3, assuming that the area [A section] registered in the cache and the store area [B section] in the VST instruction are the store area [B section in the VST instruction.
Consider that the [part] spans two or more simple blocks.

At the start address [1,0], the effective bit is read from the area effective bit registration unit 3 and sent to the VST determination circuit 7, after which the read address counter 5 increments "+1" at the start address [0,1]. (When start address <end address, read address counter is "+1", when start address> end address, read address counter is "-1"), end address [1,1]
Read the effective bit from the area effective bit registration unit 3 with VS
It is sent to the T determination circuit 7.

The VST judging circuit 7 judges the simple block address, and since the valid bit is "0" in both, the flash circuit section 6 is instructed to invalidate the VST process.

[0016]

As described above, according to the present invention, the conventional flash circuit, that is, the start address / end address created by the start / end address creating circuit of the area at the same time as or before the flash index address is created, Since it is possible to judge whether a large block is valid or invalid (whether it is registered in the cache) and cancel the creation of the flash index address, it is necessary to uselessly perform cache flush processing (create the flash index address). There is no need to expect faster processing.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a relationship among a memory block area, a block address, and a valid bit for explaining the operation of the present invention.

FIG. 3 is a diagram showing another example of a relationship between a memory block area, a block address, and a valid bit for explaining the operation of the present invention.

[Explanation of symbols]

 1 Start / End Address Creating Circuit 2 Upper Address Register 3 Area Effective Bit Register 4 Area Effective Bit Update Circuit 5 Read Address Counter 6 Flash Circuit 7 VST Judgment Circuit

Claims (1)

Claim: What is claimed is: 1. A cache invalidation processing circuit that performs cache invalidation processing in response to a vector store instruction that is a continuous write request of vector data to a main storage device, wherein An area valid bit registering unit that divides the address area on the storage device into a plurality of blocks, and indicates that the data on the main memory is registered in the cache for each block, and a store area instructed by the vector store instruction. Is registered in the area valid bit registering means as valid, and means for performing cache invalidation processing only when it is determined that the area valid bit registering means is valid. Cache invalidation processing circuit.