JPH0519812A - Parallel control system - Google Patents

Parallel control system

Info

Publication number
JPH0519812A
JPH0519812A JP17546391A JP17546391A JPH0519812A JP H0519812 A JPH0519812 A JP H0519812A JP 17546391 A JP17546391 A JP 17546391A JP 17546391 A JP17546391 A JP 17546391A JP H0519812 A JPH0519812 A JP H0519812A
Authority
JP
Japan
Prior art keywords
control
host computer
information
time information
controlled devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17546391A
Other languages
Japanese (ja)
Other versions
JP2547903B2 (en
Inventor
Masami Hara
政巳 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP3175463A priority Critical patent/JP2547903B2/en
Publication of JPH0519812A publication Critical patent/JPH0519812A/en
Application granted granted Critical
Publication of JP2547903B2 publication Critical patent/JP2547903B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To provide a parallel control system which has no delay in processing time, performs highly precise simultaneous processing, localizes a fault in a system, eliminates the need for hardware switching, and have superior reliability and cost performance. CONSTITUTION:This parallel control system is equipped with a host computer 11 which issues a control command including respective pieces of control timing information by the classifications of equipments to be controlled, a timer device 12 which generates time information, an information transmitting means 13 which transmits respective pieces of output information of the host computer 11 and timer device 12, and plural equipment controllers which are provided corresponding to the equipments 141-14n and receive the control command from the host computer 11 and the time information from the timer device 12 through the information transmitting means and compares the time information and control command to perform necessary control over the corresponding object equipments at timing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、例えば自動番組送出
装置等に用いられ、複数の被制御機器をそれぞれ任意の
時刻に駆動制御する並列制御システムに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel control system which is used, for example, in an automatic program transmitting device or the like, and which drives and controls a plurality of controlled devices at arbitrary times.

【0002】[0002]

【従来の技術】周知のように、自動番組送出装置は、複
数の映像・音声ファイルを任意の時刻に駆動して、放送
番組の制作、送出等を行う。このような並列制御システ
ムは、一般に図2、図3に示すように構成される。
2. Description of the Related Art As is well known, an automatic program sending apparatus drives a plurality of video / audio files at arbitrary times to produce and send a broadcast program. Such a parallel control system is generally configured as shown in FIGS.

【0003】図2は単独の制御用ホストコンピュータ1
1を用いて複数の被制御機器21〜2nを駆動制御する
場合を示しており、ホストコンピュータ1と被制御機器
21〜2nは制御インターフェース3を通じて直接的に
接続されている。
FIG. 2 shows an independent control host computer 1.
1 illustrates a case where a plurality of controlled devices 21 to 2n are driven and controlled by using the control unit 1. The host computer 1 and the controlled devices 21 to 2n are directly connected via the control interface 3.

【0004】図3は複数台(図では2台)の制御用ホス
トコンピュータ11,12を用いて複数の被制御機器2
1〜2nを駆動制御する場合を示しており、各ホストコ
ンピュータ11,12はそれぞれ制御インターフェース
31,32を通じてシステム切換器4に接続され、この
切換器4の切替操作により各被制御機器21〜2nに接
続されるようになっている。
FIG. 3 shows a plurality of controlled devices 2 using a plurality of (two in the figure) control host computers 11 and 12.
1 to 2n are driven and controlled. The host computers 11 and 12 are connected to the system switching unit 4 through the control interfaces 31 and 32, respectively, and the controlled devices 21 to 2n are switched by the switching operation of the switching unit 4. It is designed to be connected to.

【0005】しかしながら、従来の並列制御システム
は、制御用ホストコンピュータが全ての制御を集中して
実行しており、処理が集中する結果、使用コンピュータ
が高性能のものでなければならない。また、図2のよう
に単独制御の場合はホストコンピュータの障害が即シス
テムダウンとなるため、信頼性に欠け、同一タイミング
制御の集中により、どうしても制御動作に処理の遅れが
影響する。
However, in the conventional parallel control system, the control host computer centrally executes all the control, and as a result of the centralized processing, the computer used must have high performance. Further, in the case of independent control as shown in FIG. 2, the system failure immediately results in a failure of the host computer, which lacks reliability, and the concentration of the same timing control inevitably affects the control operation due to the processing delay.

【0006】図3のように複数台のホストコンピュータ
を使用すればその改善を図れるが、システム切替が集中
するため、規模が大きくならざるを得ない。さらに、ま
た、制御インターフェースや切換器等のハード構成が複
雑になり、コスト増大、故障率の増大を招く。
Although it is possible to improve this by using a plurality of host computers as shown in FIG. 3, the system switching is concentrated, so that the scale must be increased. Furthermore, the hardware structure of the control interface, the switch, and the like becomes complicated, resulting in an increase in cost and an increase in failure rate.

【0007】[0007]

【発明が解決しようとする課題】以上述べたように従来
の並列制御システムでは、ホストコンピュータにより集
中制御を行っているため、単独制御によれば処理集中に
よる処理時間の遅れが制御動作に影響し、ホストコンピ
ュータの障害が即システムダウンとなり、複数制御によ
れば、その問題が改善されるものの、ハード構成が複雑
となり、コスト増大、故障率の増大を招く。
As described above, in the conventional parallel control system, the central control is performed by the host computer. Therefore, with the independent control, the processing time delay due to the processing concentration affects the control operation. However, the failure of the host computer immediately causes the system to go down, and although the problem is solved by the multiple control, the hardware configuration becomes complicated, and the cost and the failure rate increase.

【0008】この発明は上記の問題を解決するためにな
されたもので、比較的性能の低いホストコンピュータを
用いても、処理時間の遅れがなく、精度の高い同時処理
が可能で、システム障害も局所化することができ、ハー
ド切替が不要で、信頼性、コストパフォーマンスに優れ
た並列制御システムを提供することを目的とする。
The present invention has been made in order to solve the above problems. Even if a host computer having a relatively low performance is used, there is no delay in processing time, high-accuracy simultaneous processing is possible, and there is no system failure. It is an object of the present invention to provide a parallel control system that can be localized, does not require hardware switching, and has excellent reliability and cost performance.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
にこの発明は、複数の被制御機器をそれぞれ任意の時刻
に駆動制御する並列制御システムにおいて、前記複数の
被制御機器別に各制御タイミング情報を含む制御コマン
ドを発生するホストコンピュータと、時刻情報を発生す
る時計装置と、前記ホストコンピュータ及び時計装置の
各出力情報を伝送する情報伝送手段と、前記複数の被制
御機器それぞれに対応して設けられ、前記情報伝送手段
を通じて前記ホストコンピュータから制御コマンドを、
前記時計装置から時刻情報を受取り、時刻情報と制御コ
マンドとを比較して該当タイミングで対応する被制御機
器の必要な制御を行う複数の機器コントローラとを具備
して構成される。
In order to achieve the above-mentioned object, the present invention is a parallel control system for driving and controlling a plurality of controlled devices at arbitrary times, in which control timing information is provided for each of the plurality of controlled devices. A host computer that generates a control command including a clock, a clock device that generates time information, an information transmission unit that transmits each output information of the host computer and the clock device, and a plurality of controlled devices. A control command from the host computer through the information transmission means,
It comprises a plurality of device controllers that receive time information from the timepiece device, compare the time information with control commands, and perform necessary control of corresponding controlled devices at corresponding timings.

【0010】[0010]

【作用】上記構成による並列制御システムでは、ホスト
コンピュータで被制御機器別に各制御タイミング情報を
含む制御コマンドを発生して各機器コントローラに供給
し、コントローラ側で制御コマンドを時刻情報と比較し
て制御タイミングを判別し、被制御機器の駆動制御を開
始するようにしている。
In the parallel control system having the above configuration, the host computer generates a control command including each control timing information for each controlled device and supplies the control command to each device controller, and the controller side controls the control command by comparing with the time information. The timing is determined and the drive control of the controlled device is started.

【0011】[0011]

【実施例】以下、図1を参照してこの発明の一実施例を
説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

【0012】図1はその構成を示すもので、11は制御
用ホストコンピュータ、12は時計装置、13は情報デ
ータの通信回線となるLAN、141〜14nは被制御
機器、151〜15nはそれぞれ被制御機器141〜1
4nを直接的に制御する制御コントローラである。
FIG. 1 shows the configuration thereof. 11 is a control host computer, 12 is a clock device, 13 is a LAN serving as a communication line for information data, 141 to 14n are controlled devices, and 151 to 15n are controlled devices. Control devices 141 to 1
It is a controller that directly controls 4n.

【0013】時計装置12は常に基準となる時刻情報を
出力する。この時刻情報はLAN13を通じてホストコ
ンピュータ11及び制御コントローラ151〜15nに
送られる。
The clock device 12 always outputs reference time information. This time information is sent to the host computer 11 and the controllers 151 to 15n via the LAN 13.

【0014】ホストコンピュータ11は制御データファ
イル111に格納された制御手順に従って、各被制御機
器141〜14nへの制御コマンドを作成する。この
際、制御コマンドに、上記時刻情報を基準に制御開始時
刻を指定する制御タイミング情報を含める。これらの制
御コマンドは予めLAN13を通じて対応する制御コン
トローラ151〜15nに送出される。
The host computer 11 creates control commands for the controlled devices 141 to 14n according to the control procedure stored in the control data file 111. At this time, the control command includes control timing information that specifies the control start time based on the time information. These control commands are sent to the corresponding control controllers 151 to 15n through the LAN 13 in advance.

【0015】制御コントローラ151〜15nはそれぞ
れ入力した制御コマンドをいったん内部メモリ(図示せ
ず)に記憶しておき、コマンド中の制御タイミング情報
と時計装置12からの時刻情報とを比較し、一致した時
点で対応する被制御装置に制御コマンドで指定された制
御を開始する。
Each of the control controllers 151 to 15n temporarily stores the input control command in an internal memory (not shown), compares the control timing information in the command with the time information from the clock device 12, and finds a match. At the time point, the control specified by the control command is started for the corresponding controlled device.

【0016】すなわち、上記構成による並列制御システ
ムでは、ホストコンピュータ11で被制御機器141〜
14n別に各制御タイミング情報を含む制御コマンドを
発生して対応する機器コントローラ151〜15nに供
給し、コントローラ151〜15n側で制御コマンドを
時刻情報と比較して制御タイミングを判別し、被制御機
器141〜14nの駆動制御を開始するようにしてい
る。
That is, in the parallel control system having the above configuration, the host computer 11 controls the controlled devices 141-141.
A control command including each control timing information is generated for each 14n and supplied to the corresponding device controllers 151 to 15n. The controller 151 to 15n compares the control command with the time information to determine the control timing, and the controlled device 141 The drive control of 14n is started.

【0017】したがって、上記構成によれば、各被制御
機器141〜14nはそれぞれ対応して設けられた制御
コントローラ151〜15nで制御されるので、処理集
中による処理時間の遅れを生じることなく並列制御が可
能となる。また、ホストコンピュータ11は、予め制御
コマンド作成して事前に制御コントローラ151〜15
nに送出しておけばよいので、リアルタイム性の要求か
ら解放され、これによって比較的安価なものが使用可能
となる。
Therefore, according to the above configuration, since the controlled devices 141 to 14n are controlled by the corresponding controllers 151 to 15n, the parallel control can be performed without causing a delay in the processing time due to the processing concentration. Is possible. In addition, the host computer 11 creates a control command in advance and creates the control controllers 151 to 15 in advance.
Since it has only to be sent to n, the requirement of real-time property is released, and thereby a relatively inexpensive one can be used.

【0018】特に、本システムは並列制御数が限定され
ないため、相当複雑な同時処理が可能になり、これによ
ってより複雑な多重処理も実現できる。例えば、放送用
の自動番組送出装置では、制御が同一の同期信号にタイ
ミングが集中することが多いが、当該システムを用いれ
ば容易に処理することができる。
In particular, since the number of parallel controls is not limited in this system, considerably complicated simultaneous processing is possible, and thereby more complicated multiple processing can be realized. For example, in an automatic program transmission device for broadcasting, the timing is often concentrated on the same synchronization signal under control, but it can be easily processed by using the system.

【0019】さらに、ホストコンピュータの切替等のク
リティカルパスがなくなって、システムのアベイラビリ
ティが高くなるため、障害に強くなり、信頼性を向上さ
せることができる。また、単独のホストコンピュータで
制御するので、コストパフォーマンスに優れたものとな
る。
Further, since the critical path such as the switching of the host computer is eliminated and the availability of the system is enhanced, the system is resistant to a failure and the reliability can be improved. In addition, the cost performance is excellent because it is controlled by a single host computer.

【0020】[0020]

【発明の効果】以上のようにこの発明によれば、比較的
性能の低いホストコンピュータを用いても、処理時間の
遅れがなく、精度の高い同時処理が可能で、システム障
害も局所化することができ、ハード切替が不要で、信頼
性、コストパフォーマンスに優れた並列制御システムを
提供することができる。
As described above, according to the present invention, even if a host computer having relatively low performance is used, there is no delay in processing time, high-accuracy simultaneous processing is possible, and system failures are localized. Therefore, it is possible to provide a parallel control system that does not require hardware switching and is excellent in reliability and cost performance.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明に係る並列制御システムの一実施例を
示すブロック構成図。
FIG. 1 is a block diagram showing an embodiment of a parallel control system according to the present invention.

【図2】従来の単独ホストコンピュータ制御による並列
制御システムの構成を示すブロック図。
FIG. 2 is a block diagram showing the configuration of a conventional parallel control system controlled by a single host computer.

【図3】従来の複数ホストコンピュータ制御による並列
制御システムの構成を示すブロック図。
FIG. 3 is a block diagram showing a configuration of a conventional parallel control system controlled by a plurality of host computers.

【符号の説明】[Explanation of symbols]

11…制御用ホストコンヒピュータ、12…時計装置、
13…LAN、141〜14n…被制御機器、151〜
15n…制御コントローラ。
11 ... host computer for control, 12 ... clock device,
13 ... LAN, 141-14n ... Controlled device, 151-
15n ... Control controller.

Claims (1)

【特許請求の範囲】 【請求項1】 複数の被制御機器をそれぞれ任意の時刻
に駆動制御する並列制御システムにおいて、前記複数の
被制御機器別に各制御タイミング情報を含む制御コマン
ドを発生するホストコンピュータと、時刻情報を発生す
る時計装置と、前記ホストコンピュータ及び時計装置の
各出力情報を伝送する情報伝送手段と、前記複数の被制
御機器それぞれに対応して設けられ、前記情報伝送手段
を通じて前記ホストコンピュータから制御コマンドを、
前記時計装置から時刻情報を受取り、時刻情報と制御コ
マンドとを比較して該当タイミングで対応する被制御機
器の必要な制御を行う複数の機器コントローラとを具備
する並列制御システム。
Claim: What is claimed is: 1. A parallel control system for driving and controlling a plurality of controlled devices at arbitrary times, and a host computer that generates a control command including control timing information for each of the plurality of controlled devices. A clock device for generating time information, an information transmission means for transmitting each output information of the host computer and the clock device, and a plurality of controlled devices provided corresponding to each of the controlled devices. Control commands from the computer,
A parallel control system comprising: a plurality of device controllers that receive time information from the clock device, compare the time information with a control command, and perform necessary control of corresponding controlled devices at corresponding timings.
JP3175463A 1991-07-16 1991-07-16 Parallel control system Expired - Lifetime JP2547903B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3175463A JP2547903B2 (en) 1991-07-16 1991-07-16 Parallel control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3175463A JP2547903B2 (en) 1991-07-16 1991-07-16 Parallel control system

Publications (2)

Publication Number Publication Date
JPH0519812A true JPH0519812A (en) 1993-01-29
JP2547903B2 JP2547903B2 (en) 1996-10-30

Family

ID=15996506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3175463A Expired - Lifetime JP2547903B2 (en) 1991-07-16 1991-07-16 Parallel control system

Country Status (1)

Country Link
JP (1) JP2547903B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053547A (en) * 2005-08-17 2007-03-01 Toshiba Corp Automatic program delivery control facility and special service program delivery method thereof, and broadcast schedule managing device
US9679295B2 (en) 2005-02-25 2017-06-13 Yellowpages.Com Llc Methods and apparatuses for sorting lists for presentation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965309A (en) * 1982-10-06 1984-04-13 Hitachi Ltd Multi-sequencer system
JPS62247409A (en) * 1986-04-21 1987-10-28 Hitachi Ltd Program maintenance device for process controller
JPS6441902A (en) * 1987-08-07 1989-02-14 Canon Kk Control device for automatic assembling device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965309A (en) * 1982-10-06 1984-04-13 Hitachi Ltd Multi-sequencer system
JPS62247409A (en) * 1986-04-21 1987-10-28 Hitachi Ltd Program maintenance device for process controller
JPS6441902A (en) * 1987-08-07 1989-02-14 Canon Kk Control device for automatic assembling device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9679295B2 (en) 2005-02-25 2017-06-13 Yellowpages.Com Llc Methods and apparatuses for sorting lists for presentation
JP2007053547A (en) * 2005-08-17 2007-03-01 Toshiba Corp Automatic program delivery control facility and special service program delivery method thereof, and broadcast schedule managing device

Also Published As

Publication number Publication date
JP2547903B2 (en) 1996-10-30

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