JPH05198079A - Communication system - Google Patents

Abstract

PURPOSE:To perform a highly reliable transmission when the communication system which controls a controlled device by a wire type remote controller sends and receives data and a clock through two lines. CONSTITUTION:The wire type remote controller 5 and controlled device 1 both have microcomputers 2 and 8 and are only connected by two leads 13 and 14; and the format of data is determined so that the data and clock are sent and received, and the data are securely transmitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system suitable for use in a cable type remote control device such as a portable CD player and a cassette tape recorder.

[0002]

2. Description of the Related Art As a communication system of a conventional cable type remote control device such as a portable cassette tape recorder or a portable CD player, a remote control device (hereinafter referred to as a remote control) is provided between the portable electronic device and an earphone. Then, various operations of the electronic device are controlled by operating the remote controller near the hand.

FIG. 11 is a system diagram showing the overall structure of a conventional portable CD player and a remote controller.
Reference numeral 1 denotes a CD player that constitutes a controlled device, which is configured to reproduce a CD and the like, and is a main microcomputer (hereinafter referred to as H-C) for controlling various operations.
2).

Further, the reproduction output of the CD player 1 is such that the output leads 3 and 4 for the left and right channels LCH and RCH are connected to the earphone 6 via the remote controller 5.

The H-CPU 2 of the CD player 1, the microcomputer (hereinafter referred to as CPU) 8 in the remote controller 5 and the like are driven by a power source 7 arranged on the CD player 1 side.

In the remote controller 5, in addition to the CPU 8, an LCD 9 as a display device, a key group 10 and a decoder 11 for decoding various operations of the key group 10 and supplying the CPU 8 with a backup power source for backing up the memory of the CPU 8 and the like. H-CPU 2 and CPU 8 have a clock (CLK) lead 13 and a data (DATA) lead 1.
4, request (REQ) lead 15, key (KEY)
It is connected by a lead 16, and power is supplied from the power supply 7 to the remote controller 5 side through a power supply lead 17.

[0007]

In the above conventional configuration, C is used.
CD for data transmission between the D player 1 and the remote controller 5.
H-CPU 2 on the player 1 side and CPU 8 on the remote control 5 side
In between, three leads 13, 14 and 15 for transmitting CLK and data for DATA and REQ are required.

That is, the format once defined cannot be easily changed because the REQ data is required, so that there is a problem that there is no expandability.

Further, since the key group 10 is supplied to the CD player 1 side through the decoder 11 and the CPU 8 on the remote controller 5 side, not only the decoder has to be built in a small remote controller housing, but also the CPU 8 fails. In that case, there is a problem that the remote control operation by the key group 10 becomes completely impossible. Furthermore, if it is attempted to transfer CLK and DATA only with the two leads 13 and 14 as in the present invention,
There was a problem that data deviation occurred when the power was turned on and became unstable.

The present invention has been made in order to solve the above problems, and its purpose is to make a request for data bit by bit by using a clock signal so that only two leads are used. The present invention aims to provide a wired remote control communication system having a high format expandability while diversifying the display on the display means.

[0011]

As shown in FIG. 1, the communication system of the present invention has a wire 29 (3, 4, 13, 14, 16) between the controlled means 1 and the remote control means 5. , 1
In the communication system in which the data is transmitted by connecting the display means 7 and 18), the display data is transmitted from the controlled means 1 to the display means 9 provided in the remote control means 5 through the first lead 14, and the remote control means is provided. 5, a 1-bit unit clock is transmitted from the control unit 5 to the controlled unit 1 through the second lead 13, and the display data transmission request is made by the clock.

[0012]

According to the communication system of the wired remote controller of the present invention, data is supplied from the H-CPU 2 of the CD player 1 of the controlled means to the CPU 8 of the remote controller 5 using the lead 14 and the clock is sent from the CPU 8 side to the H-CPU 2 side. (CLK) is supplied in 1-bit units using the lead 13 and is used as a request signal for data transmission. Therefore, not only the lead 15 for a request is not required, but also a highly expandable format can be obtained. ..

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A remote control 5 for remotely controlling a portable CD player 1 will be described below as an embodiment of the communication system of the present invention.

In FIG. 1, a CD player 1 on the controlled electronic device side
Has a power supply 7 for driving the H-CPU 2 and a CD player,

An LCD 9 is provided in the remote controller 5, and the display data of the LCD 9 is displayed on the CD player 1 side of the H-C.
A CPU 8 is provided which receives from the PU 2 and supplies it to the LCD 9. Between these H-CPU 2 and CPU 8, a CLK signal from the CPU 8 is supplied to the H-CPU 2 side by a line 13 as a request in 1-bit units.
The display data (DATA) is transmitted from the 2 side to the CPU 8 side via the line 14.

Also, + B from the power source 7 on the CD player 1 side
The voltage is the key group 1 along with the CPU 8 and LCD 9 on the remote control 5 side.
Line 1 for voltage source (B) and ground potential (GND) at 0
Supplied via 7 and 18.

The left and right channel audio signals LCH and RCH of the CD player 1 are supplied to the earphone 6 via the remote controller 5.

Further, various operating voltages of the key group 10 are analog signal types in which predetermined voltages are divided by resistors R ₀₁ , R ₁₁ ... RN ₁ , and are supplied as KEY signals to the CD player 1 side via the leads 3. It is configured to be supplied to the H-CPU 2 and the like.

FIG. 2 is a plan view of the remote controller 5 of this example, in which the case 20 is made of a gourd shape and made of plastic or the like.
The CPU 8 is built in the case 20. An LCD 9 is provided at the left center of the case 20 to provide various displays.
The key group 10 is a PLAY key 26 for reproduction and an F key for fast forward.
F key 23, REW key 24 for rewinding, ST for stopping
OP key 25, DSP key 27, hold switch 28
Etc.

Reference numeral 29 is the above-mentioned leads 3, 4, 13, 14,
A lead remote controller is provided between the CD player 1 and the remote controller 5 by connecting a plug 31 (described later) to the jack on the side of the CD player 1 to connect the CD player 1 and the remote controller 5. Constitute. Incidentally, 30 is connected to the earphone 6 by a jack.

FIG. 3 shows a circuit diagram of the remote controller 5, and the LCD 9 is controlled by the CPU 8 integrated into an IC.

+ B, DATA, KEY, C of the plug 31
The LK pins are supplied to the CPU 8 and the key group 10 via leads 17, 14, 16, and 13. That is, the CLK and DATA leads 13 and 14 are connected to the CPU 8 through the resistors R ₁ and R ₂ , and + B is the + B lead 17 and the FF key 23, REW which constitutes the key group 10 through the OFF contact of the hold switch 2. It is connected to one fixed contact of the key 24, the PLAY key 26, the DSP key 27, the STOP key 25 and the like. Resistor R ₄ and capacitor C
₇ is connected in parallel to form a smoothing circuit.

+ B is further connected to the CPU 8 via a diode D ₁ , a smoothing resistor R ₃ , a capacitor C _{6 and the} like. Incidentally capacitor _{C 1, C 2, C 3} , C 4, C 5 and crystal X ₁ etc. indicates the components that are external to the CPU 8.

The KYE lead 16 is connected to the other fixed contact of each key of the key group 10 directly or via resistors R _{5 to} R _12, and depending on each operation mode, a voltage of + B is applied to these resistors R 5. _The value divided by _{5 to} R ₁₂ is set to H of the CD player 1.
-By directly supplying the analog signal to the CPU2 side, the H-CPU2 side corresponds to the voltage value by PLAY, DS.
Decode to P, STOP, etc.

The audio plug 32 includes left and right channel LCH and RCH leads and GND leads 3 and 4.
Connected in parallel to 18, the LCH and RCH leads of 3 and 4 are connected to the jack 30 via the volume adjusting variable resistors RV ₁ and RV ₂ .

In this example, the PLAY key 26 will be described later.
PLA so that CPU8 is reset by pressing
The Y key 26 is connected to the reset terminal via the lead 33 from one fixed contact side.

The data format in the above-mentioned configuration is shown in FIGS. 4A to 4C.

FIG. 4G shows a one-frame data format supplied from the H-CPU 2 of the CD player 1 to the CPU 8 of the remote controller 5. Ie MSB to LSB
Up to 20-bit data and 5-bit header (Head
er).

As shown in FIG. 4A, the header is composed of 5-bit continuous data of 1, 1, 1, 1, 1 and the status (Status) is 0 for the first bit as shown in FIG. 4G.
Fixed bits of 0 to 7 as shown in FIG. 6B.
7 are OPEN, STOP, ACES, and A, which will be described later.
MS, CUE, PLAY, NO DISC and LOWB
Indicates an attery.

In the mode data and the DSP data, 1 bit out of each 4 bits is a check bit, and the second is 0 from the beginning in the mode data and the last is 1 in the DSP mode. In the mode data, as shown in FIG. 4C, the first bit DIR is 1 for REW, 0 for FF (FWD), and Pause (also used as a PLAY key) and Shuf.
The fle is set to 1 at 1 o'clock and is in the shuffle mode.

In the DSP mode, as shown in FIG. 4D, the first bit is Battery, the next bit is DBB, the next bit is DDS, and 1 is Battery in Battery.
ryEmpty is D when it is 1 in DBB and DDS
Indicates the BB or DDS state. The DBB and DDS bits are never 1 at the same time.

The upper digit representing the track number is TRACK-
H, and the lower digit is TRACK-L, which is composed of 0 to 9 as shown in E and F of FIG. 4, respectively. In both of these track bits, the first and second bits are both 1,1.
It is made not to be.

The communication method of this example in such a data format will be described in detail with reference to FIGS.

FIG. 5 shows the DATA displayed between the H-CPU 2 on the CD player 1 side and the CPU 8 on the remote control 5 side on the LCD 9 of the remote control 5 using the two leads 13 and 14.
And CLK are communication timings.

FIG. 5A shows a clock (CLK) serving as a REQ for requesting display data from the CPU 8 of the remote controller 5 to the H-CPU 2 of the CD player, and CLK is input bit by bit. At the falling edge (low: "L") of this CLK, the H-CPU 2 on the CD player 1 side is configured to set the next 1 bit by an interrupt.

CLK is on the remote controller 5 side (high: "H")
In this state, one bit transferred from the CD player side is taken in, the CLK for the next REQ is set to "L" and output, and then returned to "H" after several 100 μsec.
Since the CPU 8 on the remote controller 5 side processes 1-bit data in about 3 to 4 millisecond, there is enough time for the H-CPU 2 to perform data conversion.

DATA for display and update transmitted from the H-CPU 2 of the CD player 1 to the CPU 8 of the remote controller 5.
4G outputs the 20-bit DATA including the 5-bit header from MSB to LSB in the format shown in FIG. 4G bit by bit as shown in FIG. 5B, and when the data for one frame shown in FIG. 4G is captured. If the data is correct after performing a predetermined check with the check bit in,
The display corresponding to the update data is displayed on the LCD 9.

FIG. 6 shows such communication timing for each frame. FIGS. 6A and 6B show timing waveforms of the CPU 8 on the remote controller 5 side, and FIGS. 6C and 6D show timings of the H-CPU 2 on the CD player side. The waveform is shown.

FIG. 6A shows a timing waveform of the TBC (time base collector) of the CPU 8. The CPU 8 on the remote controller 5 side needs to display on the LCD 9 such that the disk is rotated, which will be described later. 62.5 millisecond (16 Hz), the CLK for one frame and the display on the LCD 9 are displayed as shown in FIG. 6B during this period.

That is, as shown by CLK in FIG. 6B, 62.5
DAT transferred from the H-CPU2 side within a millisecond
If A has been updated, the updated data is displayed on the LCD 9, and display processing is performed after 62.5 msec. 6C and 6D are timing waveforms on the H-CPU 2 side of the CD player 1 side and C on the remote controller 5 side in bit units as shown in FIG. 6C.
DATA is transmitted with respect to the CLK received from the PU 8, and the data display section on the remote control 5 side has the data fixed as shown in FIG. 6D.

That is, 5 bits of H or 1 level are output to the head of the display DATA, then 1 bit of L or 0 level is output, and the actual display DATA is C from the next bit.
Since it is transmitted from the H-CPU 2 to the PU 8 via the lead 14, the H or 1 level is not continuously output for 5 bits or more. Therefore, on the remote control 5 side, if 5 bits H or 1 level continues, it may be regarded as a header. or,
In FIG. 4G after the H or 1 level of the header, there is a possibility that the L or 0 level of the fixed data at the beginning of the status mode may continue to L or 0 level for 11 bits. Or H if it is one level
-The CPU 2 is viewed as stopped and the display on the LCD is cleared. Timings of conditions of such a low voltage (referred to as HALT) mode are shown in FIGS. 7A to 7C.

FIGS. 7D to 7F are timing charts showing conditions for canceling the HALT mode. In this HALT mode, it is assumed that the CD player 1 has entered the sleep state when the L or 1 level continues for 15 times or more. CP on the remote control 5 side
U8 is also in the HALT state (status OPEN mode).

Further, since fixed data is provided at several places in each of the status, mode, DSP, track-H and track-L modes, if these fixed data are data other than the set value, it is judged as abnormal data. It is designed so that it can be seen and captured again.

Since data is transferred according to the format thus determined, the READ for REQ is used to
Compared to the communication system of FIG. 11 which performs ATA latching, data transmission can be performed with only two leads 13 and 14 with the same or higher reliability as in the case of three leads. Further, in the case where more display data is to be transferred after this format determination, even if new data is added after the 20-bit data shown in FIG. 4G, the CPU 8 of the remote controller 5 simply ignores the extra DATA. Since it is good, it is possible to extend the communication method of a compatible wired remote controller.

An actual mode of the display data pattern on the LCD 9 described above is shown in FIGS. That is, in FIG.
Various display patterns on D9 are shown. That is, FIG.
As explained in B status mode, the display output condition is H
In ALT mode OPEN, all the displays are turned off. S
Track display 40 showing the track number in TOP mode
Is 00, and the disc display 41 has stopped rotating.

The ACES mode is an access mode or the like, the track display 40 displays the access track NO, and the disk display 41 is arranged so that two pieces 42 of the disk mark are moved and rotated every 125 mmS as shown in FIG. Is made.

AMS mode is truck change, F
In the modes such as F and REW, the track display 40 shows a predetermined track display, and the two pieces 42 of the disc mark are A.
Rotate as in CES mode.

Even in the CUE mode, the track display 40 and the disk display 41 rotate like in the ACES mode, and the RE
In W, the disc display 41 rotates in the opposite direction, and the REW display 43 and the FF display 44 are displayed.

In the PLAY mode, the reproduction track NO is displayed and the two pieces 42 of the disc mark of the disc display 41 are rotated at 250 mmS.

In the LOW Battery mode, only the battery mark 45 is turned on, and if the repeat and DSP are on, the repeat display 46, BB and DDS display 47 are individually displayed. Incidentally, the state 48 in FIG. 9 shows a display state for about 1 second immediately after changing from PLAY to STOP.

In this example, the jack 3 for the earphone 6
As described above, by pressing the PLAY key 26, the CPU 8 pushes the line 33 through the line 33 as a measure against the incomplete resetting of the CPU 8 on the remote control 5 side when inserting / removing 0 or when the power is turned on. It is made to be reset. At the time of reset, the display of the LCD 9 is not erased, and the display is not updated until the regular data is obtained.

In the conventional wired remote controller shown in FIG. 11, when the CPU 8 is reset, a command for turning off the LCD 9 is sent to reset the CPU 8 so that the LCD is momentarily turned off and the operator feels uncomfortable. In this example, since the LCD off command is not transmitted, the display on the LCD 9 does not disappear instantaneously, and the backup power source 12 is unnecessary. FIG. 10 shows a flowchart for resetting the LCD 9 so as not to turn it off temporarily.

When the CPU 8 of the remote controller is reset in the first step ST ₁ of the start in FIG. 10, the hardware logic of the conventional normal CPU 8 is configured to turn off the LCD 9 or software. LCD9
Was turned off.

In this example, such a soft "off" operation is prevented (second step ST ₂ ).

In the next third step ST ₃ , the RAM attached to the CPU 8 is cleared, and in the fourth step ST ₄ , 1-bit data is input.

In the next fifth step ST ₅ , CLK is set to CP.
The data is output from U8 to the H-CPU2 side and a data update request is made.

In the next sixth step ST ₆ , it is checked whether the transmitted DATA is H or 1. Checks H or 1 In a seventh step ST ₇ proceeds to a seventh step ST _7, if H at sixth step ST ₆ is a example 9 times, and the data transmission is inaccurate at the 15 step ST _15, if YES Observe and clear the data.

If the sixth step ST ₆ is not H or 1, the process proceeds to the eighth step ST ₈ to check if L or O is, for example, 15 times, and if YES, the twelfth step ST ₁₂ And the data is judged to be incorrect, the data is cleared in the twelfth step ST ₁₂
3 turns off the LCD9 in step ST ₁₃ is returned to fourth step ST ₄ input data check for the next 1 bit is performed.

If L or O is not continuous 15 times in the eighth step ST ₈ , the transmission data is regarded as normal, and the data is stored in the RAM in the ninth step ST ₉ .

The tenth step ST ₁₀ is 5 for one frame.
It is determined whether or not a total of 25-bit data including a bit header and 20-bit data has been input. If NO, the process returns to the fourth step ST ₄ , but if YES, the process proceeds to the eleventh step ST ₁₁ .

In the 11th step ST ₁₁ , 25-bit 1
A check is made by checking whether or not the frame data is correct data, that is, a check bit. If not correct, the data is cleared in the 15th step ST ₁₅ , Y
When correct data for one frame is taken in by ES, the data is saved in the display area of the RAM in the 14th step ST ₁₄ , and the data in the display area is displayed on the LCD 9 in the 16th step ST ₁₆ .

According to the communication system of the wired remote controller of the present invention, even if CLK and DATA are transmitted by only two leads, it is possible to perform highly reliable transmission as compared with the communication system in which the latch data is further transferred. Even if data is added after the format is determined, since there is no latch data, it is possible to provide a compatible and highly expandable communication system.

Further, the display pattern on the LCD mounted on the remote control side can be used in a variety of ways, and a communication system can be obtained which can perform the functional operation of the remote control even if the CPU 8 on the remote control side is disabled.

[0064]

According to the communication system of the wired remote controller of the present invention, it is possible to obtain highly reliable data transmission which is equal to or more than that of the three-wire system by only transferring the clock and the data by the two-wire system.

[Brief description of drawings]

FIG. 1 is a system diagram showing an overall configuration showing an embodiment of a communication system of the present invention.

FIG. 2 is a configuration diagram of remote control means used in the communication system of the present invention.

FIG. 3 is a circuit diagram of remote control means used in the communication system of the present invention.

FIG. 4 is an explanatory diagram of a signal format of the communication system of the present invention.

FIG. 5 is a timing chart of the 1-bit communication system of the communication system of the present invention.

FIG. 6 is a timing chart of the one-frame communication system of the communication system of the present invention.

FIG. 7 is an operation timing chart of a HALT mode of the communication system of the present invention.

FIG. 8 is a diagram showing a display pattern of the display means of the remote control means used in the communication system of the present invention.

FIG. 9 is a diagram illustrating a display state of a display pattern according to the present invention.

FIG. 10 is a flowchart for explaining a reset method of the present invention.

FIG. 11 is a system diagram showing an overall configuration of a conventional communication system.

[Explanation of Codes] 1 CD player 2 H-CPU 3,4,13,14,16,17,18 Lead 6 Earphone 8 CPU 9 LCD 10 Key group

Claims (1)

[Claims] 1. In a communication system for transmitting data by connecting a wire between the controlled means and the remote control means, the controlled means is connected to a display means provided in the remote control means via the first lead. Communication for transmitting display data from the remote control means to the controlled means via the second lead, and requesting display data transmission by the clock. method.