JPH05197369A - Display controller - Google Patents

Abstract

PURPOSE:To enable the superposing display of graphic data of bits different from that of text data on the text data. CONSTITUTION:A display controller is comprised of a multiplexer 31 which outputs the high-order four bits and low-order four bits of the graphic data GD of eight bits sequentially at every display period of one dot, delay circuits 33, 34 which generate data FG1, FG2 by delaying the output GX of the multiplexer 31 for a one-dot display period and a two-dot display period, and circuits 32, 35-37 which (i) generate and output the text data of eight bits for a first dot which comprises a picture element, and output by connecting the data FG1 and FG2 for a second dot, or (ii) output by connecting the data FG1 and GX for the first dot, and generate and output the text data of eight bits for the second dot. By employing such constitution, it is possible to display the text data converted to the one of eight bits on one of two dots comprising one picture element of a display device, and the graphic data on the other of the two dots, and to realize the superposing display.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device having a function of superposing and displaying graphic data and text data on the same display screen of a display device.

[0002]

2. Description of the Related Art There is known a technique for displaying a character and a graphic image, in other words, text data and graphic data in a superimposed manner on a display device such as a CRT or FPD (flat panel display).

In this type of technique, display characters are generally stored in a text memory in the form of attribute data indicating a character code and a display color (character color and background color), and a graphic image specifies a color of each display pixel. Stored in the graphic memory in the form of graphic data (data that specifies the color of the corresponding pixel). Then, the text data that specifies the color of each display pixel on the display screen is generated from the character code and the attribute data, and one of the text data and the graphic data is selected and supplied to the display device to obtain a combined image. There is.

[0004]

However, in the conventional display control device, the text data and the graphic data can be overlapped only when the number of bits (width) of both data is equal. .. For example, 8-bit graphic data (256 colors can be specified) and 4-bit text data (16 colors can be specified) cannot be superimposed and displayed. Therefore, when the graphic data is superimposed on the 4-bit text data and displayed, more than 16 colors can be used to represent the graphic image although 256 colors are originally used. There wasn't.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a display control device capable of superposing and displaying text data and graphic data having different bit widths. Another object of the present invention is to enable use of various colors when displaying text data and graphic data in an overlapping manner.

[0006]

In order to achieve the above object, the display control device according to the first aspect of the present invention is
Text data supply means for supplying text data of m-bit width which is the above integer, graphic data supply means for supplying graphic data of n-bit width larger than m, and graphic data supply means connected to the graphic data supply means. Is connected to the text data supply means, receives the text data, and displays the text data and the predetermined text data for superimposing display of the graphic data and the text data. Connected to the multiplex means, the text data selecting and outputting means for connecting the constant data of 1 to generate n-bit text data and outputting it to the display device, and the text data selecting means outputs the n-bit text data. The multiplexed graphics based on the timing of Restore Kudeta the data of n bits wide, and a graphic data selection output means for outputting the recovered data to a display device.

A display control device according to a second aspect of the present invention is a text data supply means for supplying text data of m bit width and a graphic data supply means for supplying graphic data of n bit width larger than m. In order to display text on the display device, the (n−m) -bit data is concatenated to the m-bit width text data supplied from the text data supply means to generate n-bit width text data. In order to generate and output and display the graphic image on the display device, the graphic data having the n-bit width supplied from the graphic data supply means is output, and the text and the graphic image are superimposed on the display device. One of the dots that make up one pixel of the display device for display
For this purpose, the (n-m) -bit data is concatenated to the m-bit width text data supplied from the text data supply means to generate and output the n-bit width text data, and the plurality of dots For another one of the above, a conversion / selection unit for outputting the graphic data of the m-bit width supplied from the graphic data supply unit, and an n-bit data output from the conversion / selection unit are analog video signals. It is characterized in that it is provided with a video DAC means for converting to.

The converting / selecting means outputs, for example, a first multiplexer means for sequentially outputting the upper bit and the lower bit of the graphic data for each one-dot display period, and an output GX of the first multiplexer means. A delay unit for delaying the 1-dot display period and the 2-dot display period to generate the delay data FG1 and FG2, and a plurality of dots forming one pixel for displaying the text data and the graphic data in an overlapping manner. For the first dot, the n-bit width text data is generated and output, and for the second dot, the data FG2 and F
G1 may be concatenated and output, or data FG1 and GX may be concatenated to generate delayed video data for the first dot, and the delayed video data may be output for the second dot. It includes an output means for generating and outputting bit-width text data.

[0009]

According to the display control apparatus of the first aspect of the present invention, graphic data is multiplexed, and further, graphic data to be output is restored from the multiplexed data in accordance with the timing of selecting text data. And output. Therefore, the graphic data having different bit widths and the text data can be appropriately overlapped and displayed.

Further, according to the display control device of the second aspect of the present invention, the n-bit text data is converted into the same m bits as the graphics data, and is converted into one dot forming one pixel. Since the bit text data and the m-bit graphic data are displayed, the graphic image having a different bit number and the text can be displayed in an overlapping manner.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a display system according to an embodiment of the present invention. The display system of FIG. 1 includes a display control device 1 and a CPU (Central Processing).
Unit) 2, graphic memory 3, video DAC 4, C
An RT display device (hereinafter referred to as CRT) 5, a flat panel display device (hereinafter referred to as FPD) 6 such as a liquid crystal display device and a plasma display device, a text memory 20, and an FPD conversion circuit 21 are provided. The CPU 2 controls the entire display system.

The graphic memory 3 is R (red) G
It is composed of four memory planes corresponding to (green) B (blue) I (luminance). In this embodiment, each graphic data is composed of data of 2 bits (8 bits in total) read from four memory planes, and corresponding pixels on the display screen (composed of 2 dots in this embodiment). Color) and brightness.

The text memory 20 stores a character code (8 bits or 16 bits) CC of a display character and attribute data (4 bits (a total of 8 bits) data indicating a character color and a background color) AD.

The video DAC 4 comprises 256 color look-up tables and a D / A converter. Each color lookup table is selected by using the output data (8 bits) of the display control device 1 as an address, and stores color data of 6 bits for each of RGB (18 bits in total). Also, D
/ A converter reads the RG read from the selected register
Each 6-bit B color data is converted into an RGB analog video signal and supplied to the CRT 5. In the CRT 5, two dots arranged in the horizontal direction form one pixel. The FPD conversion circuit 21 converts the CRT analog video signal output from the video DAC 4 into an FPD signal, and supplies the FPD signal to the FPD 6.

The display control device 1 is under the control of the CPU 2.
The data stored in the graphic memory 3 and the text memory 20 are read out and selected or combined to create a CRT 5 or FPD.
The display data of 6 is output. Next, the configuration of the display control device 1 will be described.

The display control device 1 includes a horizontal display control circuit 1
0, parameter register 11, graphic / video data generation circuit 12, text / video data generation circuit 1
3, a mode setting circuit 14 and a transmission control circuit 15 are provided.

The parameter register 11 holds various parameters transferred from the CPU 2. Various parameters are parameters that specify the display mode, addresses A and I.
/ O light control signal, display data CD, and whether or not the transparent mode is set, and parameters indicating whether to display the text display, the graphic display, and the superimposed display are included.

The mode setting circuit 14 sets various modes such as a graphic image display mode, a text display mode, a graphic image and text overlay display mode, and a transparent mode according to the parameters held in the parameter register 11. .. Here, the graphic image display mode is a mode for displaying the graphic image stored in the graphic memory 3, the text display mode is a mode for displaying the text stored in the text memory 20, and the overlay display mode is the graphic image. This is a mode in which and text are displayed in a superimposed manner.

The transmission control circuit 15 includes a mode setting circuit 14
A transparent control signal for instructing whether or not to set the transparent mode is output for each pixel based on the transparent mode from the image data and the attribute data (display attribute data) AD from the text memory 20. Here, in the transparent mode, in the superimposed display, when the graphic image and the character overlap, the graphic data and the text data are displayed together, and when the graphic image and the background portion of the text overlap, the graphic mode is displayed. This is a mode for displaying data.

The clock generation circuit 17 has a clock signal C.
R, CL and load signal SL are generated. Clock signal C
R and CL are signals that have a period of one dot display period of the display device and determine the display timing in the horizontal direction.
The load signal SL is a signal having a period of one pixel (two dots) display period.

The horizontal display control circuit 10 is responsive to the clock signal CR from the clock generation circuit 17 to the graphic video data generation circuit 12 and the text video data generation circuit 13 which is a signal HE for designating the dot number on the horizontal scanning line. Is output.

The selection control circuit 16 is the clock generation circuit 1
CRT in synchronization with the clock signal CL and load signal SL supplied from 7 and the selection signal S in synchronization with the clock CL
Output to the output circuit 18.

Graphic / video data generation circuit 12
Under the control of the CPU 2, reads the graphic data stored in the graphic memory 3, converts the graphic data into graphic video data GD, and responds to the control signal HE from the horizontal display control circuit 10 with the graphic video data at an appropriate timing. GD is sequentially output. The graphic video data GD is 8-bit data that specifies the color of the corresponding pixel on the display screen.

The text / video data generation circuit 13 is
Under the control of the CPU 2, the attribute data AD corresponding to the character code data CC is read from the text memory 20, and the corresponding text / video data TD is sequentially output at appropriate timing in response to the control signal HE.
Specifically, the text / video data generation circuit 13 converts the character code data CC into a dot pattern by using a character generator, and further, this dot is "1".
When the dot is "0", 4-bit data indicating the character color of the attribute data is output as text / video data TD, and when this dot is "0", the 4-bit data indicating the background color of the attribute data is output as text / video data TD. To do.

The CRT output circuit 18 is the selection control circuit 16
According to the load signal SL and the selection signal S supplied from
The 8-bit graphic data GD and the 4-bit text data TD are selected or combined and output so that the display according to the set mode is performed.

Next, the structure of the CRT output circuit 18 will be described with reference to FIG. The CRT output circuit 18 has a color palette 30, a first multiplexer 31, a second multiplexer 32, flip-flops (F / F) 33 to 36, and a third multiplexer 37.

The color palette 30 has 16 palette registers selected by 4-bit text / video data (color attribute data) TD, and each palette register has 4-bit color text data (color designation data) T.
Hold X.

The first multiplexer 31 responds to the load signal SL, and when the load signal SL is at a high level, the upper 4 bits (4 to 7) of the graphic video data GD.
When the load signal SL is at a low level, the lower 4 bits (0 to 3 bits) are selected and output as data GX.

The flip-flop 33 outputs the data GX output from the first multiplexer 31 to the clock signal C.
The data FG1 delayed by one clock of L is output. The flip-flop 34 outputs the data FG2 obtained by delaying the data GX output from the first multiplexer 31 by two clocks of the clock signal CL.

The second multiplexer 32 has a selection signal S.
In response to color text data TX, data FG
One of the outputs of 1, FG2 and flip-flop 35 is selected and output. The flip-flop 35 latches the output data of the second multiplexer 32 in synchronization with the clock signal CL, supplies the latched data to the second multiplexer 32, and outputs the upper 4 bits of the output data of the display control device 1. Is supplied to the video DAC 4.

The third multiplexer 37 has a selection signal S
In response to this, one of the data GX and FG1, the output of the flip-flop 36 described later, and the data “0000” is selected and output. The flip-flop 36 latches the output data from the third multiplexer 37 in synchronization with the clock signal CL. The flip-flop 36 supplies the latched data to the third multiplexer 36 and also supplies it to the video DAC 4 as the lower 4 bits of the output data of the display controller 1. Next, the operation of the embodiment shown in FIGS. 1 and 2 will be described.

First, in response to the execution of an application program or the like, the CPU 2 writes graphic data defining a graphic image to be displayed in the graphic memory 3, and the character code CC of the text to be displayed and the attribute data AD to the text. Write to memory 20.

Further, the CPU 2 sets parameters for setting the display mode and parameters relating to the transmission control. The mode setting circuit 14 outputs a mode signal indicating the designated display mode according to the set parameters.

The transmission control circuit 15 is a mode setting circuit 14
According to the mode designating signal from the and the attribute data AD from the text memory 20, a transparency control signal indicating whether or not to perform the transparency control is output for each pixel. For example, when the color attribute data AD supplied from the text memory 20 specifies a specific color and the CPU 2 specifies "transparent" for this specific color, the transparency control circuit 15 indicates that the transparency control should be executed. Output a transmission control signal. Regarding the transmission control itself, for example, Japanese Patent Publication No. Sho 54-
161839, Sho 57-167079, Sho 57-185
085, Sho 60-220387, etc., and details thereof are omitted.

The selection control circuit 16 is a mode setting circuit 14
And a second and a third in response to the signal from the transparent control circuit 15.
The multiplexers 32 and 37 of 1 output the selection signal S indicating the signal to be selected.

The graphic video data generation circuit 12 sequentially reads the graphic data defining the display color of the pixel to be displayed from the graphic memory 3, converts it into graphic video data GD, and supplies it to the CRT output circuit 18.

Further, the text video data generation circuit 13
Sequentially reads the character code CC and the attribute data AD of the character to be displayed, and develops the read character code CC into pattern data using a character generator. Further, the text video data generation circuit 13 generates 4-bit graphic text data TD corresponding to the display color of the pixel to be displayed from the obtained pattern and the attribute data AD and supplies it to the CRT output circuit 18.

The CRT output circuit 18 receives the graphic video data GD and the graphic text data TD, and operates as follows according to the clock signal CL, the load signal SL, and the selection signal S.

The first multiplexer 31 (when the display of the graphic image is designated) responds to the load signal SL shown in FIG. 3B to the higher order of the graphic video data GD supplied at the timing shown in FIG. 3C. Four
The bits and the lower 4 bits are sequentially selected and output as shown in FIG. 3D.

As shown in FIGS. 3E and 3F, in response to the selection signal S, the second multiplexer 32 selects the data FG1 and the third multiplexer 37 selects the data at the timing when the load signal SL is at the low level. Select GX. The output of the second multiplexer 32 is delayed by one clock via the flip-flop 35 and output to the video DAC 4 as upper data, and the third multiplexer 37.
Output of the video DAC4 via the flip-flop 36
Is output as lower data to.

On the other hand, as shown in FIGS. 3E and 3F, when the load signal SL becomes high level in response to the selection signal S, the second multiplexer 32 causes the flip-flop 3 to operate.
The Q output of 5 is selected, and the third multiplexer 37 selects the Q output of the flip-flop 36. The outputs of the second and third multiplexers 32 and 37 are the flip-flop 3
It is output to the video DAC 4 via 5, 37.

Therefore, as shown in FIG. 3G, the display control device 1 delays the video graphic data GD supplied from the data generating circuit 12 by one cycle of the load signal SL, that is, by delaying one pixel display period, Output to video DAC4. The video DAC 4 uses a color lookup table to convert this data into color data of 6 bits for each of RGB, and further D / A converts the color data.
Supply to CRT5. (When the display of the text data is designated) Using the text data TD supplied from the text video data generation circuit 13 at the timing shown in FIG. 4C as an address, one color palette register in the color palette 30 is selected and selected. The 4-bit color text data TX held in the color palette register is output as shown in FIG. 4D. As shown in FIGS. 4E and 4F, the second
Of the multiplexer 32 in response to the selection signal S, while the load signal SL is at the low level, the color text data T
X is selected, and the third multiplexer 37 selects fixed data "0000". The output of the second multiplexer 32 is output to the video DAC 4 as higher order data via the flip-flop 35, and the third multiplexer 37
Is output to the video DAC 4 as lower data via the flip-flop 36. That is, the display control device 1
Data "TX · 2 ⁴ As shown in FIG. 4E Is output.

As shown in FIGS. 4E and 4F, the load signal S
When L goes high, in response to the selection signal S, the second
The multiplexer 32 selects the Q output of the flip-flop 35, and the third multiplexer 37 selects the Q output of the flip-flop 36. In other words, the second and third multiplexers 32 and 37 output the output data T half cycle before.
X 2 ⁴ Is output as is. The outputs of the second and third multiplexers 32 and 37 are delayed by one clock by the flip-flops 35 and 36 and supplied to the video DAC 4. That is, the data display control apparatus 1, as shown in FIG. 4G "TX · 2 ⁴ Is output.

The video DAC 4 outputs this output data TX.2.
^Four Select a color lookup table with and convert to RGB each 6-bit color data.
/ A converted and supplied to CRT5.

(When displaying a composite image of a graphic image and text) In this case, as shown in FIGS. 5C and 5D, the graphic text data TD and the graphic video data GD are sequentially supplied to the CRT output circuit 18. In response to the load signal SL, the first multiplexer 31 alternately outputs the upper 4 bits and the lower 4 bits of the graphic video data GD, as shown in FIG. 5E.

The "superposition mode and transmission mode" are designated in pixel units. Therefore, with respect to the pixel for which the superimposition instruction is not given, as shown in FIGS. 5F and 5G, in response to the selection signal S, the first and second multiplexers 3
Reference numerals 2 and 37 select the data FG1 and GX, respectively, when the load signal SL is at the low level, and select the outputs of the flip-flops 35 and 36, respectively, when the load signal SL is at the high level. Therefore, the output of the display control device 1 is
As shown in FIG. 5H, the graphic data becomes data delayed by one pixel display period.

On the other hand, when the "superimposition mode and transparent mode" is designated, the selection control circuit 16 causes the second multiplexer 32 to select the color text data TX and the third multiplexer 37 to receive the data "0000". The control signal S for selection is output. In response to the selection signal S, the second multiplexer 32 selects the color text data TX, the third multiplexer 37 selects the data “0000”, and the selected data is set to 1 by the flip-flops 35 and 36. The clock is delayed and output to the video DAC 4.

As shown at timing T1, when the second multiplexer 32 selects the color text data TX when the load signal SL is low level, when the load signal SL becomes high level, the second multiplexer 32 is selected.
Selects the data FG2, and the third multiplexer 37 selects the data FG1. Therefore, 2 that form one pixel
Text data TX × 2 ^{4 in} one before one dot Is displayed, and the graphic data GD is displayed on the back one.

On the other hand, as indicated by the timing T2,
Text data when the load signal SL is high level
When TX is selected by the second multiplexer 32
The load signal SL one clock before is at the low level.
Already, the second multiplexer 32 has already
FG1 is selected, and the third multiplexer 37 selects the data G
X has been selected. Therefore, the two pixels that make up one pixel
Graphic data GD is displayed in front of one of the dots
And the text data TX x 2 in the back one^Four Is displayed
Be done.

As a result, the screen of the CRT 5 shown in FIG.
As shown in, the 16-color 4-bit text data T
D and 256 colors 8-bit graphic video data G
Color display is performed with D superimposed.

As described above, according to this embodiment, when the overlay mode is designated, the text data is displayed on one of the two dots forming one pixel and the graphic data is displayed on the other. To do. Therefore, even if the bit widths of the graphic data and the text data are different, the graphic data and the text data can be displayed in an overlapping manner.

In the above embodiment, one pixel is composed of two dots per scanning line, but for example, one pixel is composed of four dots per scanning line, and superposition is designated. Sometimes text data and graphic data may be displayed in two dots each.

In the present invention, the number of bits of each data is not limited to that in the above embodiment, and various changes can be made. In the above embodiment, the multiplexer 31 outputs the graphic data GD in the order of upper 4 bits and lower 4 bits. However, for example, the multiplexer 31 may output the lower 4 bits and the upper 4 bits of the graphic data GD in this order. In this case, for example, when displaying graphic data, the second multiplexer 32 selects the data GX and the third multiplexer 37 selects FG.
Select 1. Further, for example, when the text data TX is selected for the first dot of one pixel, the second multiplexer 32 causes the data FG1 for the first dot.
Is selected, and the third multiplexer 37 selects FG2. Further, in the above embodiment, in order to convert the 4-bit text data TX into the 8-bit text data, the data "0000" is concatenated to the lower part of the text data TX, but the data "0000" is concatenated to the upper part of the text data TX.
May be connected. The data to be linked is "000
Fixed data other than 0 "may be used.

FIG. 6 shows the CRT output circuit 18 shown in FIG.
A modification of is shown. The configuration of FIG. 6 is different from the configuration of FIG. 2 in that a color palette 30A is arranged between the output end of the multiplexer 41 and the first flip-flop 33. The color palette 30A includes 16 color palette registers selected by 4-bit data output from the multiplexer 31. The 4-bit color data set in the selected color palette register is supplied to the first flip-flop 33 and the multiplexer 37. The subsequent operation is the same as the operation of the CRT output circuit shown in FIG. A configuration without using the color palette register 30 is also possible.

FIG. 7 shows an example of a concrete circuit configuration of the display system shown in the block diagrams of FIGS. In FIG. 7, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

The display system shown in FIG. 7 has a CPU 2, a Chinese character text memory 103, a video memory 105, multiplexers 107 to 113, an OR gate 115, a transparency control circuit 117, a mode setting circuit 119, and a clock generating circuit 12.
1, AND gate 123, flip-flop 125, selection signal generation circuit 127, color palette 30, multiplexers 32 and 37, flip-flop (F / F) 33 to
Have 36.

The CPU 2 controls the entire system. The Kanji text memory 103 stores a 16-bit Kanji code and 8-bit attribute data (4 bits for specifying a character color and 4 bits for specifying a background color). The Kanji text memory 103 includes a character generator, and generates and outputs a character pattern from a Kanji code. The video memory 105 stores graphic data, and stores dot pattern data, an 8-bit ANK (alphanumeric-kana) code, and 8-bit attribute data. The video memory 105 is provided with a character generator and generates a character pattern from an ANK code and outputs it, while the 8-bit graphic data is output as it is.

The 8-bit attribute data output from the Kanji text memory 103 and the 8-bit attribute data output from the video memory 105 are supplied to the multiplexer 109 via the multiplexer 107. In response to the selection control signal S, the multiplexer 107 selects and outputs one of the Chinese character attribution data and the attribution data of the ANK code. The multiplexer 109 responds to the signal from the OR gate 115 by the multiplexer 1
One of the upper 4 bits (specifying the character color) and the lower 4 bits (specifying the background color) of the attribute data supplied from 09 is selected and output.

The 8-bit graphic data output from the video memory 105 is supplied to the multiplexer 111. In response to the load signal SL, the multiplexer 111 selects and outputs the upper 4 bits of the graphics data when the load signal SL is at the high level, and selects the lower 4 bits of the graphics data when the load signal SL is at the low level. And output.

The output data of the multiplexer 109 and the output data of the multiplexer 111 correspond to the multiplexer 113.
Is supplied to. The multiplexer 113 responds to the signal for switching the graphic and the text from the CPU 2,
One of 4-bit graphic data and 4-bit text data is selected and supplied to the color palette 30.
The color palette 30 includes 16 palette registers selected by 4-bit data supplied from the multiplexer 113, and each palette register holds 4-bit color designation data. The 4-bit output data of the multiplexer 111 is further supplied to the flip-flop 33 and the multiplexer 37.

The transmission control circuit 117 designates the transmission mode in pixel units under the control of the CPU 2. The mode setting circuit 119 specifies the superposing mode in pixel units. The AND gate 123 outputs a signal of logic "1" level when the "transmission mode and superposition mode" is designated. The flip-flop 125 delays the output of the AND gate 123 by one clock CL. Selection signal generation circuit 127
Outputs a selection signal S according to the outputs of the AND gate 123 and the flip-flop 125 and the load signal SL.
Next, the operation of the display system shown in FIG. 7 will be described by taking the case of displaying a composite image of a graphic image and a text as an example.

In response to the execution of the application program or the like, the CPU 2 writes the graphic data defining the graphic image to be displayed and the ANK code in the video memory 105, and further writes the character code and the attribute data of the kanji character to be displayed in the kanji text. Write to the memory 103.

The video memory 105 reads the display data under the control of the CPU 2, supplies the display data to the multiplexer 113 when the display data is the dot pattern data, and supplies the character generator when the display data is the ANK code. It is expanded into a bitmap pattern by using it, and the bitmap pattern is supplied to the multiplexer 113.
The attribute data is supplied to the multiplexer 107.

On the other hand, the Kanji text memory 103 stores the CP
Read out the Kanji code that should be displayed under the control of U101,
It is developed into a bit map pattern using a caruta generator. Data indicating the on / off state of dots on the bitmap pattern (second bit) is supplied to the OR gate 115, and corresponding attribute data is supplied to the multiplexer 107. Multiplexer 107 is CP
One of them is output in response to a Kanji attribute and ANK attribute switching signal from U2.

The multiplexer 113 outputs the supplied 8-bit data in units of 4 bits twice in response to the load signal SL. The second output of the multiplexer 111
Bit (indicates dot on / off of dot pattern)
Are supplied to the OR gate 115.

Bit data and multiplexer 1 supplied from the Kanji text memory 103 to the OR gate 115
The second bit supplied from 13 to the OR gate 115 is data indicating whether or not the corresponding pixel is on. When the corresponding pixel is on, the display color of the pixel is the character color specified by the attribute data. On the other hand, when the corresponding pixel is off, the display color of the pixel is the background color specified by the attribute data. Therefore, when the output of the OR gate 115 is “1” (ON), the multiplexer 109 selects the 7th to 4th bits (specifying the character color) of the attribute data supplied from the multiplexer 107, and the output of the OR gate 115. Is 0 (off), the 3rd to 0th bits (specifying the background color) of the attribute data supplied from the multiplexer 107 are selected.

In response to the selection signal from the CPU 2, the multiplexer 111 selects the data from the multiplexer 113 when the display of the graphic data is designated, and from the multiplexer 109 when the display of the text data is designated. Select data and output. The data selected by the multiplexer 111 is converted into 4-bit color data by the color palette 30 and supplied to the multiplexer 32.

The transmission control circuit 117 outputs a signal that becomes an active level when the transmission (graphic display mode) is designated, and when the mode setting circuit 119 designates the superposition mode, the output of the AND gate 123 is It becomes "1" level. The selection signal generation circuit 127 responds to the output of the AND gate 123 and its 1-clock delay signal, and further to the load signal SL, and the multiplexer 32,
37 specifies the data to be selected as follows. AND FF SL MUX32 MUX37 0 0 L FG1 GX 0 0 H FF35 FF36 1 0 L FG1 GX 1 0 H TX 0 0 0 1 L FG2 FG1 0 1 H 1 FG1 GX 1 G 1 F 1 L

By setting the selection signal S as described above, the multiplexers 32 and 37 sequentially select the data as shown in the timing charts of FIGS. 5F and 5G, and the display device selects the 4-bit text data and the 8-bit text data. The bit graphic data is overlaid and displayed.

[Brief description of drawings]

FIG. 1 is a block diagram of a display system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a CRT output circuit shown in FIG.

3A to 3G are timing charts for explaining a graphic display mode.

4A to 4F are timing charts for explaining a text display mode.

5A to 5H are timing charts for explaining an overlapping display mode.

FIG. 6 is a block diagram showing a modification of the CRT output circuit shown in FIG.

FIG. 7 is a circuit diagram showing an example of a detailed configuration of the display system shown in FIGS. 1 and 2.

[Explanation of symbols]

1 ... Display control device, 2 ... CPU, 3 ... Graphic memory, 4 ... Video DAC, 5 ... CRT display device (CRT), 6 ... Flat panel display device (F
PD), 10 ... Horizontal display control circuit, 11 ... Parameter register, 12 ... Graphic / video data generation circuit,
Reference numeral 13 ... Text / video data generating circuit, 14 ... Mode setting circuit, 15 ... Transmission control circuit, 20 ... Text memory, 21 ... Flat panel display conversion circuit, 30 ...
Color palette, 32, 37 ... Multiplexer, 33-
36 ... Flip-flop (F / F), 103 ... Kanji text memory, 105 ... Video memory, 107-113 ...
Multiplexers, 115 ... OR gates, 117 ... Transparent control circuits, 119 ... Mode setting circuits, 121 ... Clock generation circuits, 123 ... AND gates, 125 ... Flip-flops, 127 ... Selection signal generation circuits.

Claims (3)

[Claims] 1. A text data supply means for supplying text data of m-bit width which is an integer of 2 or more, a graphic data supply means for supplying graphic data of n-bit width larger than m, and the graphic data supply means. A text that is connected to the text data supply means and that multiplexes the graphic data into m-bit width data and connects the text data and predetermined data to output n-bit text data. The multiplexed graphic data is output to the data output means and to the multiplexing means, and the multiplexed graphic data is transferred to n based on the timing at which the text data selecting means outputs the n-bit text data.
Graphic data selecting and outputting means for restoring the data having a bit width and outputting the restored data to the display device, and displaying the graphic data and the text data having different bit widths on the display device in a superimposed manner. Display controller. 2. Text data supplying means for supplying text data of m-bit width, graphic data supplying means for supplying graphic data of n-bit width larger than m, and a plurality of dots constituting one pixel of a display device. The m supplied by the text data supply means for one of the
(N-m) -bit data is concatenated to the bit-width text data to generate and output n-bit width text data, and the graphic data supply means supplies the data for another one of the plurality of dots. Graphic data and text data are provided, which include conversion / selection means for outputting the graphic data having the above-mentioned m-bit width, and video DAC means for converting the n-bit data output from the conversion / selection means into an analog video signal. A display control device characterized by displaying in a superimposed manner. 3. The conversion / selection means sets the upper bit and the lower bit of the graphic data to 1
First multiplexer means for outputting in order for each dot display period, and output GX of the first multiplexer means is delayed by 1 dot display period and 2 dot display period to obtain delay data FG.
1 and FG2, and for the first dot of the plurality of dots forming the one pixel, the n-bit width text data is generated and output, and for the second dot. , Data FG2 and FG1
Or output the data FG1 and GX for the first dot, and generate and output the n-bit width text data for the second dot. 3. The display control device according to claim 2, further comprising: