JPH05190432A - Charged particle beam aligner - Google Patents

Abstract

PURPOSE:To achieve the high speed of the response speed of an amplifier without changing a resistance value regarding a charged particle beam aligner wherein an exposure pattern signal is applied to a deflector through a signal conversion circuit, a charged particle beam is deflected and run by scanning by using the deflector according to a piece of data and a pattern is drawn on a specimen. CONSTITUTION:Collector for switching transistors Tr1, Tr2 are connected, via resistances R3, R4, to a point where a collector for a transistor Q1 for amplification use at an amplifier 4 which outputs a deflection control signal is connected to a load resistance RD. A first differentiation circuit 21 and a second differentiation circuit 22 are installed at the side of bases for the transistors Tr1, Tr2. Input signals are differentiated by using the first differentiation circuit 21 and the second differentiation circuit 22; the switching transistors Tr1, Tr2 are switching-controlled. Thereby, the rise and the fall of an output voltage are made steep.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charged particle beam exposure apparatus, and in particular, it applies an exposure pattern signal to a deflector through a signal conversion circuit, and this deflector deflects and scans a charged beam according to data to scan a sample. The present invention relates to a charged particle beam exposure apparatus that draws a pattern on a substrate.

In recent years, along with the increase in density of integrated circuits, photolithography, which has been a mainstream for fine pattern formation for many years, has been studied for a new exposure method using a charged particle beam such as an electron beam or an ion beam or an X-ray. , Is actually being used.

In the charged particle beam exposure apparatus, an exposure pattern digital signal is digital-analog converted, and the analog signal is converted into a deflector via a signal conversion circuit such as an amplification circuit, a current-voltage conversion circuit, and a voltage-current conversion circuit. It is applied as a deflection control signal. As a result, the charged particle beam passing through the deflector is deflected and scanned on the sample according to the deflection control signal to draw a desired pattern. When the charged particle beam is an electron beam, the electron beam itself can be narrowed down to about a few Å, and thus it has a great feature that a fine pattern of about a micron or less can be formed.

However, the electron beam exposure apparatus is a so-called "one-stroke writing" exposure in which a desired pattern is decomposed into a size equal to or smaller than the maximum shot that can be generated by the electron optical system and exposed one by one. Therefore, the finer the pattern, the smaller the beam must be exposed. Therefore, how fast the exposure is performed is important, and it is an essential issue to shorten the exposure time for exposing one shot at a time. Therefore, it is necessary to increase the response speed in the signal conversion circuit.

[0005]

2. Description of the Related Art FIG. 7 is a block diagram showing an example of a main part of a conventional charged particle beam exposure apparatus. In the figure, an exposure pattern digital signal generated by a pattern generator 1 is converted into an analog current by a DA converter (DAC) 2 and then supplied to a current-voltage (IV) conversion circuit 3 to be converted into an analog voltage. To be done.

The analog voltage extracted from the IV conversion circuit 3 is amplified by the amplifier 4 and then applied to the deflector 5.
An electron beam is deflected and scanned according to the pattern on the sample 7 placed on the stage 6 through the deflector 5.

Here, the amplifier 4 is conventionally the circuit shown in FIG.
It is configured. In the figure, N-channel field effect transistor
Register Q₁Is an amplifying transistor whose gate is
Anti-R ₁Is connected to the input terminal 8 via
Resistance R_DThrough the high potential side power supply voltage V_HOne connected to
One, resistance R₂Connected to the output terminal 9 via
Resistance is R_sThrough the low potential side power supply voltage V_LConnected to
ing.

As a result, the voltage Ein input to the input terminal 8 is applied to the gate of the transistor Q ₁ through the resistor R ₁ , where it is amplified by the amplification factor R _D / R _S and taken out from the drain. It is output to the output terminal 9 via the resistor R ₂ . The output voltage Eout of the output terminal 9 is Ein
It is represented by ( _RD / _RS ).

FIG. 9 shows the waveform of the output voltage Eout, where a is the waveform when the input voltage Ein falls from the high level to the low level in 4V steps, and FIG. 9b is the input voltage Ein from the low level to the high level. The waveform when rising to the level in 4V steps is shown. Settling time is 200 nse
c (However, the settling time of the input voltage itself is 25n
sec. ). The delay time at this time is mainly the delay of the transistor Q ₁ itself and the deflector 5 connected to the output terminal.
Is determined by the time constant generated by the capacitance component of R and the resistance R _D.

[0010]

By the way, in an electron beam exposure apparatus, generally, data to be exposed is stored in a memory, and after a shot is generated, it is digitally read by a DAC2.
After being converted into analog, it is further amplified through an IV conversion circuit 3 by an amplifier 4 to a voltage necessary for beam deflection and applied to a deflector 5. The applied voltage at this time is about ± 50 V at maximum. The maximum current output to the refocusing coil instead of the deflector 5 is about 100 mA. However, actually, as shown in FIGS. 9A and 9B, even if the input voltage Ein changes stepwise, it takes time for the output voltage Eout waveform to settle to the desired value. If an electron beam is irradiated and exposure is performed during settling, misalignment and blurring (focus failure) occur, so it is necessary to stop exposure and wait until settling. Therefore, the exposure time in the electron beam exposure apparatus is determined by the sum of the actual exposure time and the waiting time described above.

In the case of the most sensitive photosensitizer (resist) in the current technology, D = about 5 to 10 μC, and the current density of the exposure apparatus is about E = 50 A / cm ² . Therefore,
The time required to expose the light is D / E, 100 to 2
It will be about 00 nsec. In this case, the exposure frequency (when waiting time is not taken into consideration) is 5 to 10 MHz. 6
The number of shots is 70 to 10 in case of pattern drawing of 4MDRAM (Dynamic Random Access Memory)
Since it is about 0 × 10 ⁶ , exposure at 10 MHz results in exposure in only about 7 to 10 seconds.

However, in reality, as described above, a waiting time is added to the above exposure time. The types of waiting time include a sub-deflector jump waiting time corresponding to the response speed of the amplifier 4, a slit deflector deflection waiting time, a refocus coil settling waiting time, etc., and the waiting time is the deflection distance ΔA (= At _{= The} value is about 400 nsec to ₁ μsec depending on ( _n −At _{= n−1} ).

Therefore, the actual exposure time is 500 nsec.
~ 1.2μsec, exposure frequency is 2-1MH
It will be less than z. If the exposure frequency is 1MHz,
It takes 70 to 100 seconds to expose a 64M DRAM. Therefore, in order to improve the throughput, it is essential to reduce the waiting time, that is, to increase the response speed of the amplifier 4.
And it becomes an important issue.

Therefore, it is conceivable to reduce the resistance R _D shown in FIG. 8 in order to increase the response speed of the amplifier 4, but if the value of the resistance R _D is reduced, the current flowing through the transistor Q ₁ increases. Therefore, the allowable drain-source current I _{DS of} the transistor Q ₁ becomes _{equal to} or _larger than the current I _DS .

As a result, the value of the resistor R _D is limited to a value such that the current flowing through the transistor Q ₁ is a drain-source current less than the allowable I _DS, and the response speed of the amplifier 4 is similarly limited. Will be done. Therefore, conventionally, the response speed of the amplifier 4 is restricted by the time constant of the resistance R _D which is determined to be within the allowable I _DS , and there is a problem that the drawing speed cannot be increased.

The present invention has been made in view of the above points,
An object of the present invention is to provide a charged particle beam exposure apparatus which can speed up the response speed of an amplifier without changing the value of the resistance R _D.

[0017]

In order to achieve the above object, the present invention converts an exposure pattern digital signal generated by a pattern generator into an analog signal by a DA converter, and then converts the analog voltage or the analog voltage by a signal conversion circuit. In the charged particle beam exposure apparatus, which converts the electric current, further amplifies it by an amplifier, and applies it as a deflection control signal to the deflecting means to deflect the charged particle beam passing through the deflecting means to scan the sample for exposure. And a second switching transistor,
The configuration has first and second differentiating circuits.

The collectors of the first and second transistors are connected to the common connection point of the output terminal of the amplifying transistor constituting the amplifier, the load resistance, and the output terminal via the first and second resistors, respectively. In addition, the transistors have different conductivity types.

The first and second differentiating circuits separately differentiate the output signals of the signal converting circuit input to the amplifying transistor, and the differentiating signals are separately formed in the first and second switching transistors. To enter.

[0020]

The output signal of the signal conversion circuit is applied to the input terminal of the amplifying transistor of the amplifier while the first signal is applied to the first transistor.
And are supplied to the second differentiating circuit and differentiated. First
The output signal of the differentiating circuit is input to the base (or gate) of the first switching transistor, and the output signal of the second differentiating circuit is input to the base (or gate) of the second switching transistor.

Since the first and second switching transistors have different conductivity types, the output differential signals of the output differentiating circuits of the first and second differentiating circuits have a narrow width when the output signal of the signal converting circuit rises. A positive pulse is generated, so that one of the first and second switching transistors is turned on and the other is turned off.

When the output signal of the signal conversion circuit falls, the differential signal output from the first and second differentiating circuits becomes a negative pulse having a narrow width, so that one of the first and second switching transistors is turned off. Turns the other on.

Since the collectors of the first and second switching transistors are commonly connected to the load resistor and the output terminal of the amplifier via the first and second resistors, the first switching transistor is turned on. When, the current flows between the first switching transistor and the output terminal, and when the second switching transistor is on, the current flows between the second switching transistor and the output terminal. Therefore, when the input signal sharply changes, such as when the input signal of the amplifier rises or falls, the signal output to the output terminal also sharply changes.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of the first embodiment of the essential parts of the present invention. 7, those parts that are the same as those corresponding parts in FIG. 7 are designated by the same reference numerals, and a description thereof will be omitted. This embodiment is an apparatus applied to the electron beam exposure apparatus shown in FIG. 6, and this electron beam exposure apparatus will be described first. In FIG. 6, the exposure apparatus is roughly divided into an exposure section A and a control section B. The exposure unit A includes a charged particle beam generation source 60 having a cathode electrode 61, a grid electrode 62, and an anode electrode 63, and a first slit 6 that shapes charged particles (hereinafter, referred to as a beam) into, for example, a rectangular shape.
4 and a first electron lens 6 for converging the shaped beam
5, a slit deflector 66 for deflecting the position where the beam shaped according to the deflection signal S1 is irradiated onto the second slit 68, the second lens 67, and the second lens 67 are installed on the sample side. , A second slit 68 for shaping the beam into, for example, a rectangular shape, and a blanking deflector 6 for blocking or passing the beam according to a blanking signal.
9, a third lens 70 for reducing the beam, an aperture 71, a refocus coil 72, a fourth lens 73, a dynamic focus coil 74, a dynamic stig coil 75, and a beam on the sample. The projection lens 76 for projecting, the main differential coil 77 for beam positioning on the wafer W according to the exposure position determination signals S2, S3 from the control unit B, the sub deflector 78, and the wafer W are mounted on the X-axis. A stage 79 movable in the −Y direction and first to fourth alignment coils 80
.About.83.

On the other hand, the control unit B is loaded by a storage device 90 which stores design data of the integrated circuit device and which is composed of a disk or an MT recorder, a central processing unit (CPU) 91 which controls the entire charged particle beam, and a CPU 91. For example, the drawing information, the wafer W on which the pattern is to be drawn
An interface circuit 92 for transferring various information such as the drawing position information above, and a data memory 93 for holding the drawing pattern information transferred from the interface circuit 92.
Then, the overlapping state of the beams of the first slit 64 and the second slit 68 is determined according to the drawing pattern information, and as a result, a deflection signal S1 that determines the beam size is output, and the position of the beam on the wafer W is determined. A pattern controller 94 as a data designating unit, a holding unit, a computing unit and an output unit for performing a process of calculating and outputting S2 and S3 information for determining whether to expose, a sequence controller 95, a DA converter (DAC) and an amplifier ( AMP)
96, blanking control circuit 97, DAC and AMP9
8, deflection control circuit 99, DAC and AMP100, stage movement correction circuit 101, DAC and AMP102,
103, stage moving mechanism 104, and laser interferometer 10
5 and.

The sequence controller 95 receives a command from the interface circuit 92 and the pattern controller 94.
To output a signal S2 to be applied to the main differential coil 77 from the pattern control controller 94 and to output the signal S3 from the pattern controller 94 after the output signal is settled. As a result, the drawing processing sequence is controlled according to the drawing position information. To do. The stage control mechanism 104 for moving the stage as necessary and the laser interferometer 105 for detecting the stage position constitute a stage control unit.

The DAC and AMP 98 output a blanking signal S _B , and the DAs and AMPs 102 and 103 output exposure position determining signals S2 and S3, respectively. Where DAC
The AMP 103 includes the DAC 2, the IV conversion circuit 3, the amplifier 4 and the differentiating and switching circuit 11 shown in FIG. In addition, the sub deflector 7
Reference numeral 8 is an electrostatic deflector corresponding to the deflector 5 in FIG. The storage device 90, the CPU 91, the interface circuit 92, and the data memory 93 form the pattern generator 1.

Next, the operation of this exposure apparatus will be described. The electron beam emitted from the electron gun 60 is shaped into a rectangular shape by the first slit 64, and then the lenses 65, 6
It is converged by 7 and is irradiated on the second slit 68. The beam size is determined by the overlap between the first slit 64 and the second slit 68, and for this reason, the rectangular beam passing through the first slit 64 is deflected by the slit deflector 66.

The beam that has passed through the second slit 68 passes through a blanking deflector 69 and is then reduced by a third lens 70. Thereafter, the beam is 100 μm by a Sazu deflector 78.
Deflection is performed in a small deflection area (subfield) of about m.
Before the actual exposure, the deflection control circuit 99 and the DAC / DAC are controlled under the instruction of the sequence controller 95.
The exposure position determination signal S2 is output through the AMP 102 and supplied to the main differential coil 77, so that the small deflection region (subfield) is largely deflected by electromagnetic deflection within the exposure field of about 2 mm □.

On the other hand, in the control section B, the data to be exposed is read from the recording device 90 by the CPU 91 prior to the exposure and stored in the data memory 93 through the interface circuit 92. This is to avoid the action of reading the storage device 90 during exposure (because it takes time to read from the storage device 90).

When the exposure is started, first, the signal S2, which is the main differential deflection data, is read from the data memory 93 according to the instruction of the sequence controller 95, and is output to the main differential coil 77 through the deflection control circuit 99 and the DAC / AMP 102. It After the output value is stabilized (the sequence controller 95 manages the time until the output is stabilized). The pattern controller 94 uses the S1 signal and the S signal stored in the data memory 93.
Output 3 signals.

The data read from the storage device 90 (that is, the data stored in the data memory 93 before the start of exposure) is pattern data. Therefore,
When the start signal is output from the sequence controller 95, the pattern controller 94 reads the data from the data memory 93, inputs the data to the pattern generation unit in the pattern controller 94, generates shot data from the pattern data, and further generates the shot data. The shot data thus obtained is supplied to a stage movement amount correction circuit 101 for performing rotation correction and the like when the stage 79 of the wafer W is mounted,
Here, the deflection data to be actually output to the DAC / AMP 103 is created.

The output deflection data of the stage movement correction circuit 101 is DAC / AMP 103, which will be described later in FIG.
2. After being converted into an analog voltage through the IV conversion circuit 3, it is amplified by the amplifier 4 and the differentiation and switching circuit 11 and then applied to the non-grounded electrode of the sub deflector 78 (deflector 5). Data is also input from the pattern controller 94 to the DAC / AMPs 96 and 100, respectively. This data is DA-converted and amplified by the DAC / AMP 96 and 100, and then the slit deflector 66 and the refocusing coil 72 are used as a deflection control signal.
Applied to. At this time, the movement of the stage 79 (corresponding to the stage 6 in FIG. 1) is controlled by the sequence controller 95 via the stage moving mechanism 104. The moving position of the stage 79 is measured by the laser interferometer 105, and the measurement result is supplied to the stage moving amount correction circuit 101. As a result, the electron beam is irradiated to a predetermined position on the wafer W corresponding to the sample 7,
Draw the desired pattern on top.

In this embodiment, the main part of such an electron beam exposure apparatus is constructed as shown in FIG. In the figure, the amplifier 4
Is connected to the differential and switching circuit 11 and is configured to minimize the delay in the response of the amplifier 4.

Amplifier 4 and differentiation and switching circuit 11
FIG. 2 shows an embodiment of the circuit section including the above. In the figure, an amplifier 4 is similar to the amplifier 4 of the conventional device shown in FIG. 8 and has an N-channel field effect transistor Q ₁ and a drain resistance R _D.
And a source resistor R _S , the gate of the transistor Q ₁ is connected to the input terminal 12, and the connection point between the drain of the transistor Q ₁ and the resistor R _D is connected to the output terminal 13.

The differentiating and switching circuit 11 includes a first differentiating circuit 21, a second differentiating circuit 22, a switching PNP transistor Tr ₁ , a switching NPN transistor Tr ₂ , a first resistor R ₃ and a second resistor. R ₄
Consists of. The first differentiating circuit 21 is a capacitor C connected between the input terminal 12 and the base of the transistor Tr _1.
1 and a variable resistor R ₁ connected between the base and emitter of the transistor Tr ₁ . Second differentiating circuit 22 and the capacitor C ₂ which is connected between the base of the input terminal 12 and the transistor Tr _2, consisting of the variable resistor R ₂ connected between the base and emitter of the transistor Tr _2.

The collectors of the transistors Tr ₁ and Tr ₂ are connected to the transistor Q via resistors R ₃ and R ₄ , respectively.
It is connected to the common connection point of the drain of _1, the resistor R _D and the output terminal 13. The emitters of the transistors Tr ₁ and Tr ₂ have a high potential side power source voltage V _H terminal and a low potential side power source voltage V
It is connected to the _L terminal.

In the present embodiment, as an example, the capacitors C ₁ and C ₂ are each 82 pF, and the values of the resistors R _{1 to} R ₄ are 2 respectively.
A voltage output with a gain of 10 is obtained by setting 00Ω, the resistance R _D to 2 kΩ, and the resistance R _S to 200Ω.

Next, the operation of this circuit will be described. When the rectangular wave voltage Ein is input to the input terminal 12, the input voltage E is applied to the connection point X between the capacitor C ₁ and the variable resistor R _1.
A narrow negative polarity differential pulse is generated for a predetermined time (which is determined by the time constant of the capacitor C ₁ and the variable resistor R ₁ ) from the falling time of in, and for a predetermined time from the rising time of the input voltage Ein. A narrow positive differential pulse generated by a constant is generated.

Similarly, the capacitor C ₂ and the variable resistor R ₂
At a connection point Y with the input voltage Ein, the capacitor C ₂ and the variable resistor R ₂
A differential pulse having a negative polarity and a positive polarity with a width according to the time constant is generated. The differential pulse generated at the connection point X is applied to the base of the transistor Tr ₁ , and the differential pulse generated at the connection point Y is applied to the base of the transistor Tr ₂ .

As a result, when the input voltage Ein falls when the negative differential pulse is generated, the transistor T
Since r ₁ is turned on and the transistor Tr ₂ is turned off, the current i ₁ flows from the power supply voltage V _H through the emitter and collector of the transistor Tr ₁ and the resistor R ₃ , so that the output voltage Eout of the output terminal 13 rises. ..

Further, at the time of rise of the input voltage Ein in which positive differential pulse is generated, since the transistor Tr ₁ is turned off, the transistor Tr ₂ is turned on, the resistor R ₄ from the output terminal 13, the collector of the transistor Tr _2, an emitter Since the current i ₂ flows to the power supply voltage V _L through
The output voltage Eout drops.

A voltage Eout obtained by amplifying the input voltage Ein with the transistor Q ₁ is output to the output terminal 13.
As a result, when the input voltage Ein is a rectangular wave of ± 4 V steps (settling time is 25 nsec), the output voltage Eout that steeply falls at the output terminal 13 near the rising time of the rectangle is obtained as shown by the solid line I in FIG. In the vicinity of the falling edge of the rectangular wave, an output voltage Eout that rises more steeply than in the conventional case is obtained as shown by the alternate long and short dash line II in FIG.

Here, the rise settling time is 125 ns.
ec, output voltage Eo with falling settling time of 40 nsec
ut was obtained, and the settling time could be greatly shortened compared to the conventional settling time of 200 nsec. Therefore, according to the present embodiment, the response speed of the amplifier 4 can be significantly increased as compared with the conventional one, so that the throughput of the electron beam exposure apparatus can be greatly improved.

Next, a second embodiment of the essential part of this embodiment will be described with reference to the block diagram of FIG. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 4, the pattern generator 1 has a current time t.
The exposure pattern digital signal of = n is supplied to the DAC 2 and at the same time is supplied to one input terminal of the subtracter 31. Further, the pattern generator 1 supplies the exposure pattern digital signal generated at the previous time t = n−1 to the other input terminal of the subtractor 31.

As a result, difference data indicating the difference between the current data (t = n) and the previous data (t = n-1) is extracted from the subtractor 31. The difference data is digital-to-analog converted by the DAC 32 to be an analog voltage having a level corresponding to the difference. The analog output voltage of the DAC 32 is applied as a control voltage to the variable resistors R ₁ and R ₂ shown in FIG. 2 in the differentiating and switching circuit 11 to variably control the resistance values of the variable resistors R ₁ and R ₂ .

Since the DAC 32 is a circuit for generating the control voltage of the variable resistors R ₁ and R ₂ , if the DAC ₂ has, for example, 12 bits, about 6 bits will suffice.
Since the response speed of 2 is faster than that of DAC 2, it can be synchronized.

In this way, according to this embodiment, the first pattern is changed according to the degree of change of the exposure pattern digital signal.
By variably controlling the time constants of the second differentiating circuits 21 and 22, the output voltage Eout having an optimum response according to the change of the input voltage Ein can be obtained.

By the way, in each of the embodiments shown in FIGS. 1 and 4, the deflector 5 is composed of two parallel electrodes, of which the output voltage Eout of the amplifier 4 is applied to the non-grounded electrode. However, the present invention can also be used in a deflector in which neither of the two parallel electrodes is grounded. FIG. 5 is a block diagram of the third embodiment of the essential part of the present invention in this case. In the figure, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 5, the output voltage Ein of the IV conversion circuit 3 is applied to the non-inverting amplifier 41 and the inverting amplifier 42, respectively.

Each of the non-inverting amplifier 41 and the inverting amplifier 42 is connected to the differential and switching circuits 11a and 11b having the same circuit configuration as the differential and switching circuit 11 shown in FIG. The output voltage of the non-inverting amplifier 41 is applied to one electrode 43a of the deflector 5, and the output voltage of the inverting amplifier 42 is applied to the other electrode 43b of the deflector 5.

As a result, the electrostatic deflection directions given to the electron beam by the electrodes 43a and 43b are the same. Also in the case of this embodiment, since the response speeds of the non-inverting amplifier 41 and the inverting amplifier 42 can be made faster than in the conventional case as in the above-described embodiments, high speed exposure can be performed.

The present invention is not limited to the above embodiment, and various other modified examples are possible. For example, the deflector 5 to be controlled is not limited to the electrostatic deflector such as the sub deflector 8, but may be an electromagnetic deflector such as the refocusing coil 72 or the main diff coil 77. However, in this case, a VI conversion circuit is used instead of the IV conversion circuit 3, and a current amplifier is used as the amplifier 4.

In FIG. 2, the amplifying transistor may be a bipolar transistor, and _{one of the} switching transistors Tr ₁ and Tr ₂ is on and the other is off for the same input voltage. It may be a transistor. Further, the differentiating and switching circuit 11 can be provided in the IV conversion circuit to minimize the delay due to the IV conversion circuit 3.

[0054]

As described above, according to the present invention, the amplifier for applying the control signal to the deflecting means for deflecting the charged particle beam,
Since the circuit configuration is such that the output control signal also changes abruptly in response to the abrupt change of the input signal, the response speed of the amplifier can be improved as compared with the conventional one, and thus the throughput of the exposure apparatus is improved as compared with the conventional one. In addition, by variably controlling the response speed of the amplifier according to the degree of change of the input signal of the amplifier, the degree of correction can be optimized according to the degree of change of the input signal. Is.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a main part of the present invention.

FIG. 2 is a circuit diagram of an embodiment of a main part of the device of the present invention.

FIG. 3 is a diagram showing an example of the output voltage waveform of FIG.

FIG. 4 is a configuration diagram of a second embodiment of the main part of the present invention.

FIG. 5 is a configuration diagram of a third embodiment of the main part of the present invention.

FIG. 6 is a configuration diagram of an example of an electron beam exposure apparatus to which the present invention is applied.

FIG. 7 is a configuration diagram of an example of a main part of a conventional device.

FIG. 8 is a circuit diagram of an example of the amplifier shown in FIG.

9 is a diagram showing an output signal waveform in FIG. 7.

[Explanation of symbols]

1 pattern generator 2,32 DA converter (DAC) 3 current-voltage conversion circuit (IV conversion circuit) 4 amplifier 5 deflector 6 stage 7 sample 11, 11a, 11b differential and switching circuit 21 first differential circuit 22 Second differentiation circuit 31 Subtractor 41 Non-inverting amplifier 42 Inversion amplifier R ₁ , R ₂ Variable resistances C ₁ , C ₂ Differentiation capacitors R ₃ , R ₄ Resistance Q ₁ N-channel field effect transistor for amplification Tr ₁ Switching PNP Transistor Tr ₂ NPN transistor for switching

Claims (6)

[Claims] 1. An exposure pattern digital signal generated by a pattern generator (1) is converted into an analog signal by a converter (2), then converted into an analog voltage or current by a signal conversion circuit, and further, an amplifier (4). In the charged particle beam exposure apparatus which amplifies the light beam and applies it to the deflecting means as a deflection control signal, deflects the charged particle beam passing through the deflecting means to scan on the sample (7) to perform exposure, the amplifier (4) Of the amplifying transistor (Q ₁ ), the load resistance (R _D ) and the output terminal (1
3) at the common connection point with the first and second resistors (R ₃ ,
First and second switching transistors (Tr ₁ , Tr ₂ ) having different conductivity types, each collector of which is connected via R ₄ ), and the signal conversion input to the amplification transistor (Q ₁ ). First and second differentiating circuits (21, 22) for differentiating the output signals of the circuits separately and separately inputting the differentiating signals to the first and second switching transistors (Tr ₁ , Tr ₂ ), A charged particle beam exposure apparatus comprising: 2. A detection means (31) for detecting a change amount of an exposure pattern digital signal generated by the pattern generator (1), and the first and the first depending on the detection change amount of the detection means (31). 2. The charged particle beam exposure apparatus according to claim 1, further comprising a control means (32) for variably controlling each time constant of the second differentiation circuit (21, 22). 3. The first and second differentiating circuits (21, 2)
2) are variable resistors (R ₁ and R ₂ ) and capacitors (C
₁ , C ₂ ) and the control means (32) variably controls the resistance value of the variable resistors (R ₁ , R ₂ ) according to the analog signal level obtained by DA converting the detected change amount. D
The charged particle beam exposure apparatus according to claim 2, wherein the charged particle beam exposure apparatus is an A converter (32). 4. The deflecting means has one electrode grounded,
The charged particle beam exposure apparatus according to claim 1, wherein the charged particle beam exposure apparatus is an electrostatic deflector (5) to which an output deflection control signal of the amplifier (4) is input to the other electrode. 5. The electrostatic deflector (5), wherein the deflecting means has first and second electrodes (43a, 43b) facing each other.
And the amplifier (4) non-inverts and amplifies the output analog voltage of the signal conversion circuit to generate the first electrode (43a).
A non-inverting amplifier (41) applied to the second electrode (43) by inverting and amplifying an analog voltage output from the signal conversion circuit.
2. The charged particle beam exposure apparatus according to claim 1, further comprising an inverting amplifier (42) applied to b). 6. The charged particle beam exposure apparatus according to claim 1, wherein the deflection means is an electromagnetic deflector that deflects the charged particle beam by electrode deflection.