JPH05190078A - Planar electric field emitting device - Google Patents

Abstract

PURPOSE:To improve controllability and facilitate the manufacture by forming an emitter and a collector out of silicon single crystals, by the use of an SOI substrate as a substrate, and forming each electrode, using self-alignment technology. CONSTITUTION:An emitter 4 and a collector 3 are made a specified interval apart on the same plane of a substrate, and lower and upper gates 1 and 6 are made between the emitter 4 and the collector 3. In this case, the emitter 4 and the collector 3 are made of silicon single crystals, using an SOI substrate as a substrate, and the top of the emitter 4 is pointed in the direction of thickness. And, using the SOI substrate, it becomes possible to apply the fine processing technology of silicon, and further the pointing of the top by thermal oxidation becomes easy by making the emitter 4 single crystals. That is, the controllability improves and the manufacture can be facilitated by forming the emitter 4 and the collector 3 out of silicon single crystals and forming each electrode, using self-alignment technology.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar field emission device which is improved in performance of a planar field emission device provided on a substrate and facilitates a manufacturing method.

[0002]

2. Description of the Related Art FIG. 8 is a perspective view showing the concept of a flat vacuum tube formed of a thin film on a quartz substrate. In the figure,
Reference numeral 11 is an emitter (cathode), and 12 is a collector (anode), which are formed at a predetermined distance. Reference numeral 13 denotes a gate (grid) formed between the emitter 11 and the collector 12, which are formed by a thin film of tungsten (W), for example.

FIG. 9 shows a structure in which a hole is formed in the gate so that the extension of the tip of the emitter is located substantially in the center of the gate hole, so that electrons emitted from the emitter can easily escape to the collector side and controllability is improved. Is intended.
FIG. 1A is a perspective view of a main part, and FIG. 1B shows a schematic manufacturing process. The manufacturing process will be described with reference to FIG.

Step (1) A plurality of holes 21 each having a side of 5 × 10 μm and a depth of about 1 μm (only one is shown in the figure) are formed on the substrate 20 by patterning and etching. Step (2) W is formed on the substrate 20 including the hole 21 to a thickness of about 0.1 μm by sputtering or the like, and the emitter, collector and gate are patterned (the figure shows a cross section of the lower gate). In this case, the thickness between the substrate and W is 0.
A low resistance metal (for example, Al, Ni, a silicide thin film, etc.) of about 5 μm is formed. In addition, the width of the gate 13 is the hole 21
Is formed in the vicinity of the center with a width of, for example, about 7 μm.

Step (3) A resist 22 is applied to the entire surface of the substrate including the holes 21 to remove the resist 22 'which is a leg portion of the upper gate. Step (4) A W thin film 13a to be the upper gate is formed on the entire surface of the substrate. Is formed by sputtering or the like, and the W thin film is removed except for the leg portion of the gate and the portion to be the upper gate.

Step (5) The through hole 14 is formed by removing the resist in the hole 21 including the portion sandwiched between the gates 13 and 13a. The thickness of the resist formed in step 3 is about 2 μm, and when the tip of the emitter is extended, the extension is located near the center of the through hole 14.

According to the above construction, the electrons flying from the emitter pass through the through hole 14 without colliding with the gate, so that the electrons can be controlled. In the field emission device having such a structure, it is desirable for the controllability that the distance between the emitter and the gate and the distance between the gate and the collector are formed as narrow as possible.

[0008]

However, in the above-mentioned conventional example, since the emitter, gate and collector are formed by sputtering and patterning, there is a problem that there is a limit in narrowing the distance between the electrodes.
When forming the gate having the through hole 14, there is a problem that patterning is difficult because a hole is formed in the substrate and the lower gate 13 is formed at the bottom of the hole. The present invention has been made to solve the above-mentioned problems of the prior art. By using an SOI substrate, forming an emitter and a collector of silicon single crystal, and forming each electrode by a self-alignment technique, It is an object of the present invention to provide a planar field emission device which has improved controllability and is easy to manufacture.

[0009]

In order to solve the above-mentioned problems, according to the present invention, an emitter and a collector are formed on the same plane of a substrate at a predetermined interval, and a gate is formed between the emitter and the collector. In the planar field emission device, an SOI substrate is used as the substrate, the emitter and the collector are formed of silicon single crystal, and the tip of the emitter is sharpened in the thickness direction.

[0010]

By using the SOI substrate, silicon microfabrication technology can be applied. Then, by using silicon single crystal as the emitter, it becomes easy to sharpen the tip portion by thermal oxidation.

[0011]

The present invention will be described below with reference to the drawings. Figure 1
(A), (b) is a block diagram which shows one Example of this invention, (a) is a perspective view, (b) is an AA sectional view of (a). In these figures, 1 is a lower gate made of Si, 2 is an insulating film made of SiO ₂ formed on the lower gate 1, 3 is a collector made of Si formed on the insulating film, and 4 is an emitter made of Si. The emitter and collector are arranged so as to face each other with a predetermined distance.
Reference numeral 5 is an insulating film made of SiO ₂ formed on the emitter and collector, 6 is an upper gate provided in a U shape on the lower gate to form a through hole 8, and the extension of the tip of the emitter 4 is a through hole. It is formed so as to be located near the center of 8. Reference numeral 9 denotes a case formed so as to cover the emitter, gate and collector portions, and the inside of this case is evacuated.

According to the above structure, the electrons flying from the emitter pass through the through hole 14 without colliding with the gate, so that the electrons can be controlled. next,
A schematic manufacturing method of the planar field emission device using the SOI substrate will be described with reference to FIGS. Step (1) See FIG. 2 (a is a plan view, b is a sectional view taken along line AA of a,
(c is a BB sectional view of a).

SOI substrate (Si (1), SiO ₂ shown in FIG. 1)
(2), a predetermined concentration (for example, 1 × 10 ²⁰ c) on Si (3), which is the main surface of Si (3) constituting the collector and emitter
m ⁻³ ) is doped with impurities. Next, thermal oxidation or an oxide film is deposited on the doped surface to form a SiO ₂ film 2a, and a plurality of SiO ₂ films 2a are formed at the positions where gates are to be formed, for example, to reach Si (1) by RIE (reactive ion etching). Holes 8a (only two are shown in the figure) are formed.

Step (2) See FIG. 3 (a is a plan view, b is a
A is a sectional view taken along line AA, and c is a sectional view taken along line BB of a). Next, thermal oxidation is performed to form an insulating film 2c having a thickness of S on the side surface of Si (3) exposed by the hole 8a. Next, a polysilicon 6a containing impurities of about 1 × 10 ²⁰ cm ⁻³ is formed on the substrate including the hole 8a, and the resist 15 is formed on the polysilicon 6a filled in the hole 8a. Pattern the width. Step (3) See FIG. 4 (a
Is a plan view, b is an A-A sectional view of a, and c is a BB sectional view of a).

The resist 15 is removed, and then the insulating film Si
O ₂ (2a) and 2 are etched. This etching is performed until the oxide film 2a under the polysilicon 6a is completely removed and most of the SiO ₂ (2) under the Si (3) remains. By this etching, the polysilicon gate is formed in a bridge shape and the surface of Si (1) is exposed.

Step (4) See FIG. 5 (a is a plan view, b is a
A is a sectional view taken along line AA, and c is a sectional view taken along line BB of a). SiO ₂ (2b) is formed on the surface of the substrate including the polysilicon gate 6a by sputtering. In this sputtering, the portion shown below the polysilicon 6a is not sputtered, and the thickness of the sputtering is determined to the extent that the gap e is formed. In this state, Si under the polysilicon 6a is exposed.

Next, when the substrate is dipped in an anisotropic etching solution, the etching solution penetrates through the clearance e and anisotropic etching is performed on the portion g to separate the emitter from the collector. That is, since the SOI substrate is used in the present invention, the distance between the gate, the emitter and the collector is determined in a self-aligned manner. ，

Step (5) See FIG. 6 (a) to (c) are cross-sectional views of essential parts showing the step of sharpening the tip of the emitter (and collector). That is, FIG. 5A shows the state immediately after anisotropic etching of Si (3) in the step 4 (FIG. 5), in which Si (3) sandwiched between SiO ₂ (2) and (2b) The end face is 54.7 °. Next, thermal oxidation is performed in this state. It is generally known that when there is stress in the thermal oxidation, the thermal oxidation of that portion is delayed, and here, as shown in Fig. (B), J which is in contact with SiO ₂
Oxidation of the parts K and K is slow, and thermal oxidation of the part L, which is the central part, progresses quickly. Figure (c) shows the state of etching the oxide film after thermal oxidation for an appropriate time.
The state in which the tip portion m is sharpened is shown.

Step (6) See FIG. 7 (a is a plan view, b is a
A is a sectional view taken along line AA, and c is a sectional view taken along line BB of a). Finally, predetermined portions of the oxide film 2b (here, portions indicated by n and n'and portions forming the electrode 10 of FIG. 1B) are removed by etching.

[0020]

According to the present invention, an SOI substrate is used, an emitter and a collector are formed of a silicon single crystal, and each electrode is formed by a self-alignment technique, thereby improving controllability and facilitating manufacture. It is possible to realize a flat-type field emission device having the above-mentioned structure.

[Brief description of drawings]

1A and 1B show an embodiment of a planar field emission device of the present invention, FIG. 1A is a perspective view, and FIG. 1B is a sectional view taken along line AA of FIG.

FIG. 2 is a cross-sectional view showing a schematic manufacturing process 1 of the planar field emission device of the present invention.

FIG. 3 is a cross-sectional view showing a schematic manufacturing step 2 of the flat-type field emission device of the present invention.

FIG. 4 is a cross-sectional view showing a schematic fabrication process 3 of the flat-type field emission device of the present invention.

FIG. 5 is a cross-sectional view showing a schematic manufacturing step 4 of the flat-type field emission device of the present invention.

FIG. 6 is a cross-sectional view showing a schematic manufacturing step 5 of the flat-type field emission device of the present invention.

FIG. 7 is a cross-sectional view showing a schematic manufacturing step 6 of the flat-type field emission device of the present invention.

FIG. 8 is a perspective view showing the concept of a conventional example formed of a thin film.

FIG. 9 shows a conventional example in which a hole is provided in a gate (a).
Is a perspective view of a main part, and FIG.

[Explanation of symbols]

1 Lower Gate 2, 2a, 2b Insulating Film (SiO ₂ ) 3 Collector (Silicon Single Crystal) 4 Emitter (Silicon Single Crystal) 6 Upper Gate 10 Electrode (Al)

Claims (1)

[Claims] 1. A planar field emission device in which an emitter and a collector are formed on the same plane of a substrate at a predetermined distance and a gate is formed between the emitter and the collector, and an SOI substrate is used as the substrate, A planar field emission device characterized in that the emitter and the collector are formed of silicon single crystal and the tip of the emitter is sharpened in the thickness direction.