JPH05189980A - Associative memory device - Google Patents

Abstract

PURPOSE:To perform the coincidental retrieval of a large number of cells without generating mutual intervention and at high speed by specifying the voltage of each signal line and the threshold voltage of nonvolatile memory in data retrieval. CONSTITUTION:First and second nonvolatile memory cells 11, 12 which define electrical connection/disconnection from first and second data lines 1a, 1b and 2a, 2b to a coincidental retrieval line 16 are provided. and those cells and a control word line 15 form a pair of retrieval memory word blocks. In the data retrieval, the voltage of each signal line and the threshold voltage of the nonvolatile memory cell are set so as to satisfy following equation: VW=VH<VtL <VW-VL<VtH and also, VW-VS<VtL. Where, VtL, VtH: low threshold voltage, high threshold voltage of memory cells 11, 12, VW: control word line voltage. VH, VL: data line voltage representing 0 data, and Vs: coincidental retrieval voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an associative memory device, and more particularly to a CAM (Content Addressable Memor) including a cell having a new structure based on a nonvolatile memory device.
y: content access memory), ie, an associative memory device.

[0002]

2. Description of the Related Art Conventionally, an associative memory, that is, a complete parallel type CAM (as a semiconductor memory circuit having a function of performing match detection of search data and stored data in parallel for all bits and outputting a stored address or data of the matched data Content accessable memory is well known (edited by Takuo Sugano, edited by Tetsuya Iizuka, “CMO
Design of S ultra-LSI ", Baifukan, P176-P177).

However, the configuration example per bit of the conventional CAM is composed of an SRAM cell and an exclusive NOR circuit, and it is impossible to construct a CAM having a large cell size and a practical capacity. Met.

In the case of IC cards and the like as personal databases that have been commercialized in recent years, the CA as described above is used.
RO with pre-stored data instead of M configuration
The structure is such that the data of M (read only memory) is sequentially searched one by one to find the desired data. For this reason, the more data such as the Japanese dictionary and the English-Japanese dictionary, the more time it takes to perform a search, and there is no one that has a fast and flexible search function.

In consideration of the above-mentioned conventional techniques, data retrieval stored in a conventional ROM or the like is performed by software.
C is not done sequentially for each data
If all data can be searched at a time like AM, future data search for IC cards and the like having a large-capacity memory can be made faster and more flexible.

Therefore, as a suggestion of the possibility of a large-capacity associative memory, US Pat. No. 3,701,980 (USPatent 3,701,980, Oct.1972) or Japanese Patent Laid-Open No. Hei 1
The invention and the like described in JP-A-194196 can be cited. First, the former US patent is DRAM-based
It has a CAM cell structure with one bit memory as a set, and the latter one is based on EPROM non-volatile memory.
They make up a set of CAMs. Therefore, each of them can be highly integrated as compared with the SRAM-based CAM.

[0007]

The DRAM base disclosed in US Pat. No. 3,701,980 still has a problem in area. On the other hand, Japanese Patent Laid-Open No. 1-1
In the EPROM non-volatile memory base disclosed in Japanese Patent Publication No. 94196, E is simply structurally set as a 2-bit set.
Only using the PROM memory and using the common ground line as the match search line, the details of the operation at the time of match search are not sufficiently considered, and there is a problem that flexible writing and reading cannot be performed.

In view of the above points, the present invention makes it possible to search a large number of memory cells at high speed without mutual interference, and to construct an associative memory device capable of constructing a database of high speed and large capacity. The purpose is to provide.

[0009]

In order to achieve the above object, the present inventor has conducted earnest research on an associative memory using a nonvolatile memory as one set of 2 bits, and as a result, the following problems in the conventional CAM structure have been found. I found that there is a point.

That is, (1) this Japanese Patent Laid-Open No. 1-1941
In the CAM structure disclosed in Japanese Patent Laid-Open No. 96, when a matching cell and a mismatching cell coexist during a matching search, the potential of the row “0” data and the potential of the high “1” data are connected via a common matching search line. A collision occurs and the operation cannot be guaranteed.

Not only that, (2) As the degree of integration becomes higher, the number of memory cells becomes enormous, and a large number of matching cells and non-matching cells exist, so that an extremely large current flows as a whole. I will end up.

The present inventor has arrived at the present invention based on the above findings. That is, the present invention relates to a first non-volatile memory cell that defines electrical connection or non-connection from the first data line to the match search line, and, in contrast, to the match search line from the second data line. An associative memory device in which a second non-volatile memory cell that defines electrical connection or non-connection and a control word line that controls the first and second non-volatile memory cells are a set of search memory word blocks. The associative memory is characterized in that the voltage of each signal line and the threshold voltage of the non-volatile memory cell at the time of data retrieval are adjusted so as to simultaneously satisfy the following formulas (I) and (II). A device is provided. _{V W -V H <V tL <} V W -V L (I) V W -V S <V tL (II) , however, V _tL: low threshold voltage V _W of the nonvolatile memory cell: the control word Line voltage V _H : voltage indicating “1” data of the data line _VL : voltage indicating “0” data of the data line V _S : voltage of the match search line

Here, it is preferable that the non-volatile memory cell is composed of a non-volatile transistor having a threshold voltage that satisfies the above formulas (I) and (II). Further, it is preferable that the associative memory device further comprises means for setting the voltage at the time of detecting the data so as to simultaneously satisfy the expressions (I) and (II).

[0014]

According to the associative memory device of the present invention, the first and second data lines defining the electrical connection or non-connection between the first and second data lines and the matching search line in one set of search memory word blocks. The non-volatile memory cell is controlled by the control word line. On the other hand, the voltage applied to the signal lines such as the first and second data lines, the match search line, and the control word line, and the low threshold voltage of the first and second nonvolatile memory cells. Are adjusted so as to satisfy the above formulas (I) and (II). Therefore, even when a large number of search memory word blocks are connected to one control word line, the search data added from the first and second data lines and the memory data of the search memory word block In the block in which the first and second non-volatile memory cells are connected, the first and second non-volatile memory cells are controlled by the control word line regardless of the connection definition state of the first and second non-volatile memory cells.
Connection of the first and second non-volatile memory cells by the control word line only in a block where the search data and the memory data do not match. It is possible to connect or disconnect the first data line and the second data line to the match search line, respectively, depending on the definition state.

By detecting the potential of the coincidence search line with a sense amplifier connected to the coincidence search line, the first data of each block according to the search data applied to the first and second data lines. Further, it is possible to obtain a match search result with the second non-volatile memory cell. Therefore,
Even if there are both a search memory word block that does not match the search data and a matching search memory word block in a large number of search memory word blocks that are controlled by the same control word line It is possible to eliminate the electrical collision of the above, obtain a match search result with extremely high accuracy, and have an extremely high degree of freedom of memory cell selection.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An associative memory device according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

First, before the description of the present invention, a problem similar to the problem that occurs in the conventional CAM structure using a non-volatile memory also exists when the non-volatile memory cell is applied to a highly integrated CAM. A description will be given using the newly considered 2-bit 1-set CAM Flash EEPROM memory structure shown in FIG. 3, a new device is added, and the main points of the present invention are clarified.

In the figure, the memory pair 31 in which the memory cells 31a and 31b are one set and the memory pair 32 in which the memory cells 32a and 32b are one set are respectively one CAM cell. The example given in this example is called a stack cell structure, in which the control gate 34 is laminated immediately above the floating gate 33 for accumulating charges, and has a structure suitable for high integration. ..

FIG. 4 shows variations in the threshold voltage Vt depending on the charge storage state of the floating gate 33 of each memory cell. The low threshold voltage V _tL of a memory cell having a normal stack structure is about 0.5 to 3.5 V, and has a variation of about 3 V. However, in the case of the CAM structure, this variation is fatal. The following explanation will be continued with this point as one of the issues.

Electrons are injected into the floating gate 33 of the memory cell 31a, and a high threshold voltage V _tH (this is defined as data "0" L (row)) is generated in the memory cell 3a.
1b has its inverted low threshold voltage _VtL (defined as data "1" H (high)), memory cell 32a has a low threshold voltage _VtL , and memory cell 32b has a high threshold voltage. The voltage V _tH is defined. That is, it is assumed that "0" L (low) data is defined in the CAM cell formed by the memory pair 31 and "1" H (high) data is defined in the CAM of the memory pair 32. In this state, the data “0” L (row) of the match search data 39 is stored in each CAM cell,
Consider the case where "0" L (row) is detected as a match.

First, the ground transistor 38 is turned off,
The match search sense amplifier 37 is activated. The coincidence search amplifier 37 is a current drive type amplifier and has a drive capability by itself. Therefore, the match search line 36 is 1.
The potential is set to about 5 to 2.0V. It is desirable that this set potential has a small value so as not to affect the charges accumulated in the floating gate 33, and it is generally considered to be 2 V or less.

Here, as a general CAM operation, the charges of the match search line precharged to a high potential are not matched C
The data line of the AM cell is discharged by "0" L (low) and is changed to a low potential. A match search line that has caused this change indicates a mismatch, and conversely, a match search line that maintains a high potential without a change in potential indicates a match. In this example, the data “1” H (high) of the CAM cell of the memory pair 32 is different from the search data “0” L (low), and the match search line 36 is the data line 2a (“0” L (row)). Discharge occurs and the potential becomes low.

As a specific search operation, the data line 1a
Is applied with 0 V of "0" L (low) potential of the match search data, and 1.5 to 2.0 V of opposite "1" H (high) potential is applied to the data line 1b. Similarly, 0V of the “0” L (low) potential of the match search data is applied to the data line 2a.
Is applied, and the opposite "1" H (high) potential of 1.5 to 2.0 V is applied to the data line 2b. Also at this time,
For the above reason, the potential in the high state is set as low as about 1.5 to 2.0V.

In this state, when the select word line 35 becomes active, the threshold voltage Vt becomes V _tH (> 6.5).
V: see FIG. 4) memory cells 31a, 32b are kept in the off state. However, memory cell 31b and memory cell 32a
In case of, it operates differently.

First, attention is paid to the memory cell 32a. The memory cell 32a must be turned on in order to extract the charge from the match search line 36 and detect the mismatch. However, the threshold voltage Vt of this transistor
Has a value of 0.5 to 3.5 V (see FIG. 4). Also,
At this time, the source electrode side becomes the data line 2b, and 0V is applied. Therefore, the voltage V _W of the select word line 35 needs to be 3.5 V or higher, and normally 4.5 V, which is higher by 1 V, seems to be appropriate.

That is, the voltage V _W of the select word line 35
Only when ≧ 4.5V, the potential of the match search line 36 is dropped by the 0V potential of the data line 2a. On the other hand, the coincidence search sense amplifier 37 is a current drive type and has a drive capability. Therefore, the potential of the match search line 36 finally drops to about 1.0 to 1.5 V, and the mismatch is detected by the voltage drop of about 0.5 V. Of course, this potential drop detects a mismatch, but the memory cell 31 of the CAM cell storing the match data is detected by this.
Inconvenience will occur in b.

Considering the potential of each of the three electrodes (drain, gate, source) of the memory cell 31b, first, the gate is 4.5 V or more of the select word line 35, and the source is 1. 0 to 1.5V, and the drain becomes 1.5 to 2.0V of the data line. That is,
The gate-source potential difference V _GS of this transistor is 3.
It becomes 0-3.5 (4.5- (1.0-1.5)) V or more.

The threshold voltage V _t of the memory cell 31b is at least 0.5 V (see FIG. 4). That is, V _GS (= 3.0 to 3.5)> V _t (= 0.5), and the memory cell 3 due to the substrate bias effect at this time is obtained.
Even considering the increase in the threshold voltage of 1b, the transistor of the memory cell 31b is turned on. For this reason,
A through current flows from the high potential of the data line 1b to the low potential of the data line 2a.

Generally, in the case of an associative memory, the matching search operation is simultaneously performed over a plurality of select word lines. Therefore, the shoot-through current in each select word line becomes an extremely large value in the entire chip, which is a fatal problem of inoperability. Further, the high potential of the data line 1b raises the potential of the data coincidence search line 35, which causes a problem that the potential difference detection by the coincidence search sense amplifier 37 becomes difficult.

Based on such a new consideration, the associative memory device according to the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 shows an embodiment of the associative memory device of the present invention. The CAM memory shown in FIG. 1 is, as described above, a 2-bit 1-set EE which is a unit of CAM.
It is composed of PROM memory cells. CAM
The memory cell 11 is, for example, a stack type FlashEEPRO.
EEPROM cell 11 comprising M cells 11a and 11b
a and 11b are written so as to have mutually opposite memory states. Here, the EEPROM cell 11a
Is data “0” L (low), 11b is data “1”
H (high) is written, data "1" is stored in the EEPROM cell 12a and data "0" is stored in 12b.
It is assumed that (row) is written. These EEPRO
M memory cells 11a and 11b and memory cells 12a and 12
Each of b's constitutes a memory pair, and each becomes a 2-bit CAM memory cell 11, 12.

EEPROM memory cells 11a, 11b,
Each of 12a and 12b is composed of an EEPROM memory cell 20 having a specific structure as shown in FIG. EEPR
The OM memory cell 20 includes a P substrate 21, a source 22 of n,
A drain 23 is formed, a tunnel oxide film 24 is formed on the P substrate 21 between them, a floating gate 25 is formed thereon, and a control gate 26 is formed thereon. Writing is performed by applying a high voltage pulse 27 to the control gate 26 and
By injecting hot electrons into 5, and raising the threshold voltage V _t to a predetermined voltage equal to or higher than V _W , the data state of “0” L (low) is defined. Also,
The writing of "1" H (high) is performed by extracting electrons from the floating gate to the source 22 or drain 23 side. In the present application, data “0” L
The threshold voltage of the EEPROM memory cell written with (low) is a high threshold voltage V _tH , and the threshold voltage of the EEPROM memory cell written with data “1” H (high) is a low threshold voltage. Let V _tL be taken.

Therefore, the symbol "H" written in the floating gates 13 of the EEPROM cells 11a and 12b in FIG. 1 indicates a state in which electrons are injected, and the transistors of these cells have a high threshold voltage V _tH . It indicates that it has and stores data “0” L (low). on the other hand,
The symbol "L" written in the floating gates 13 of the EEPROM cells 11b and 12a indicates a state in which electrons have been extracted, the transistors of these cells have a low threshold voltage _VtL , and data "1" H ( High) indicates that it is remembered.

In the CAM memory cell 11, the EEPR
The drain of the OM memory cell 11a is connected to the data line (bit line) 1a, the drain of the EEPROM memory cell 11b is connected to the data line (bit bar line) 1b, and the control gates 14 of both memory cells 11a and 11b are the same select word line. 15 connected to both memory cells 11a,
The source of 11b is connected to the match search line 16. CAM
As for the memory cell 12, the data contents of the constituent EEPROM memory cells 12a and 12b and the connection of the drains of both the memory cells 12a and 12b are the data line 2 respectively.
The configuration is exactly the same except that it is a and the data line 2b. Further, the match search line 16 is provided with a match search sense amplifier 17 including a precharge transistor 17a and a ground transistor 18. A plurality of such CAM memory cells are arranged with the coincidence search line 16 and the select word line 15 in common.

First, the data read operation of the CAM memory cell will be briefly described. The normal read operation is performed using the selection circuit 5 and the sense amplifier 6 provided ahead of the data lines 1a, 1b, 2a, 2b. The selection circuit 5 connects the sense amplifier 6 to the data line 1b, for example. This amplifier is a current detection type, and the data line 1b is kept at, for example, 1.5 to 2.0 V when not read. Then, when V _W , for example, 5 V is applied to the select word line 15, since V _w > V _tL is set, the memory cell 11 b between the data line 1 b and the coincidence search line 16 is turned on. On the other hand, at this time, the coincidence search line 16 is fixed to the ground potential by the ground transistor 18, so that the potential of the data line 1b decreases and changes to about 1.0 to 1.5V. This change is detected by the sense amplifier 6 and the result is output.

On the other hand, the sense amplifier 6 is connected to the data line 1a by the selection circuit 5, and the data line is similarly V.
_It is kept at _S '(1.5 to 2.0V). Then, a voltage of V _W (5 V) is applied to the word line 15 as well, but the EEPROM memory cell 11a between the data line 1a and the coincidence search line has a high threshold voltage V _tH and V _W <V. Since it is set to _tH , it does not turn on. Therefore, the potential of the data line 1a does not change. This is detected by the sense amplifier 6 and the result is output. In this way, the data stored in each memory cell is read. Where data line 1
The reason why the potentials of a and 1b are set to 2 V or less is to suppress the influence on the charges accumulated in the memory cell at the time of data reading.

Next, in the CAM memory having the above-mentioned structure, it will be explained below that the coincidence search with the input data can be carried out without causing the trouble such as the potential interference between the memory cells as mentioned above. To do.

In the present invention, the applied voltage V _W of the select word line at the time of matching search, the applied voltage V _L of the data line to which the data “0” L (low) is input, and the data “1” H.
The applied voltage V _H of the data line to which (high) is input, the applied voltage V _S of the coincidence search line, and the low threshold voltage of the EEPROM cell storing the data “1” of the 2-bit 1-set CAM memory. The relationship with V _tL is adjusted so as to satisfy the following equation. _{V W -V H <V tL <} V W -V L (I) V W -V S <V tL (II) of course, conventionally, stores data "0" of 2 bits set of CAM memory It goes without saying that the EEPROM cell has a high threshold voltage V _tH and is set so as not to be turned on even when the applied voltage V _W of the select word line is applied (high state). That is,
It is set here as _{V tH> V W -V L>} V W -V H and _{V tH> V W -V S (} III) as.

Next, the coincidence detecting operation will be described. First, data is written in the memory cells 11a, 11b, 12a, 12b as a memory pair of two cells. This set does not necessarily have to be adjacent memory cells, but in this example, contradictory data is written to the adjacent cells for ease of explanation.

CAM cell 1 composed of a memory pair
1 is “0” L (low), CAM cell 1 which is a memory pair
2 is "1" H (high). The match search data 19 is
"0" for each of these CAM memory cells 11 and 12
L (low) and "0" L (low) are detected.
Therefore, the CAM cell data of the memory pair 11 matches the search data, but the CAM cell data of the memory pair 12 does not match.

First, "0" L (low) is applied to the data line 1a.
Voltage _VL (normally OV), "1" H (high) voltage _VH is applied to the data line 1b, and "0" L is applied to the data line 2a.
(Low) voltage _VL , "1" H (high) on the data line 2b
The voltage V _H is applied. Further, the ground transistor 18 is turned off, and the match search line 16 is connected to the precharge transistor 17
It is set to the "1" H (high) state by a. Here, the voltage of the match search line 16 is represented as V _S.

In this state, the select word line 15 is "1".
When it becomes H (high), the voltage V _W is applied, and the memory pair 1
Each of the memory cells 11a, 11b,
"1" H on the control gate 14 of 12a, 12b
A (high) voltage V _W is applied.

In the memory cells 11a and 11b, electrons are injected into the floating gate 13, and a high threshold voltage V _tH that does not turn on at the H (high) voltage V _W of the select word line is given as shown in the above formula (III). In the same manner as the above-described data reading, the off state is maintained (this is because the EEPROM memory cell having V _tH > 6.5 V as shown in FIG. 4 is used, V _W = 5 V, V _H = 1.5 to 2). .0 V, V _L = 0
The same applies when V and V _S = 1.5 to 2.0 V). Therefore, the "0" L (low) state of the data line 1a and the "1" H (high) state of the data line 2b are the match search line 16
Does not affect. However, the low threshold voltage V
The case of the memory cell 11b and the memory cell 12a having _tL is different. The low threshold V _tL and the voltage V of each signal line
_W, V _H, V _L, no relationship between V _S becomes important problem to satisfy the above formula (I) and (II).

A detailed description will be given below. First, in the case of the memory cell 12a, the accumulated data "1" H (high) is different from the search data "0" L (low). Therefore, data line 2
It is necessary to extract the charges in the “1” H (high) state of the match search line 16 depending on the “0” L (low) state of a.

Here, the data line voltage is set to V _L (L state), the match search line 16 voltage is set to V _S (H state), and V _W (H state) is applied to the select word line. Suppose Then, the drain of the memory cell 12a,
The gate potential difference V _GD becomes V _W −V _L. That, (H voltage of the select word lines 15) V _GD = - Meanwhile = V _W -V _{L (L} voltage of the data line 2a), the threshold voltage V _t of the EEPROM memory cell 12a is a low threshold voltage V _tL .

In the present invention, the above formula (I) is used.
Is adjusted to satisfy V _W -V _L > low threshold voltage V _tL , the memory cell 12a is turned on, and the potential of the coincidence search line 16 precharged by the precharge transistor 17a is lowered. Match search sense amplifier 1
Reference numeral 7 is also a current detection type amplifier like the sense amplifier 6 at the time of data reading, and a voltage drop occurs due to the current drawing from the data line 2a, and it falls to a predetermined potential.
This detects a mismatch.

On the other hand, in order to prevent potential interference between the memory cells of the memory pair connected to the same select word line, in the case of the memory pair 11, the accumulated data “0” L (row) and the search data “0”. Since L (row) is the same, the memory cell 11b must be kept off and the data line 1b and the match search line 16 must be kept unconnected.

Here, the drain-gate potential difference V _GD of the memory cell 11b is V _W -V _H and the source, and the gate potential difference is V _W -V _S. That is, V _GD = (H voltage of select word line 15)-(H voltage of data line 1b) = V _W -V _H V _GS = (H voltage of select word line 15)-(voltage of match search line) = Meanwhile V _W -V _S, the threshold voltage V _t of the EEPROM memory cell 11b is a low threshold voltage V _tL. In the present invention, since it is adjusted so as to satisfy the above formulas (I) and (II), V _GD = V _W −V _H <V _tL and V _GS = V _W −
Since V _S <V _tL , the EEPROM memory cell 11b
Does not turn on. Therefore, the data line 1b and the match search line 1b
Keeps disconnected.

That is, in the match search operation, the voltages V _W , V _H , _VL , V _S and EEPR of the signal lines (the word line 15, the data lines 1a, 1b, 2a, 2b and the match search line 16) are set.
Since the relationship with the threshold voltage of the OM memory cells 11a, 11b, 12a, 12b, especially the low threshold voltage V _tL of the cells 11b and 12a, is adjusted, the memory cell 12a
Only the memory cells 11b can be turned on and the memory cells 11b can be turned off. As a result, it is possible to prevent or control the through current from the "1" H (high) potential V _{H of} the data line 1b to the "0" L (low) potential V _{L of the} data line 2a.

Therefore, even if a large number of CAM cells 11, 12, ... Controlled by the same select word line 15 include cells in which search data and stored data do not match and cells in which they match, the matching cells Since neither of the EEPROM memory cells are turned on, and only one of the EEPROM memory cells of the non-matching cells is turned on, the potential of the match search line 16 can be surely lowered without causing potential interference. By detecting with the sense amplifier 17, the mismatch can be detected.

On the other hand, in all of a large number of CAM cells 11, 12, ... Controlled by the same select word line 15, when the retrieved data and the stored data match, all the EEPROM memory cells of all the CAM cells are Since the data line and the coincidence search line 16 are not electrically connected without being turned on, the potential of the coincidence search line 16 does not change from the precharge voltage V _S by the precharge transistor 17a. Therefore, by detecting this voltage with the sense amplifier 17, it is possible to detect the coincidence.

As described above, in order to surely perform the match search operation without causing the potential interference between the memory cells, the non-volatile type in which the threshold voltage of the conventional memory and the voltage of each signal line are not adjusted is used. With the associative memory of, it is impossible. The adjustment of the threshold voltage of the nonvolatile memory and the voltage of each signal line is performed by (1) adjusting the low threshold voltage of the EEPROM according to the above formulas (I) and (II) according to the voltage of each signal line. Or (2) the threshold voltage of the nonvolatile memory to be used, especially when the low threshold voltage is determined, the voltage of each signal line, especially This can be done by adjusting or setting the voltages of the control word line, the first and second data lines, and the coincidence search line so as to satisfy the above formulas (I) and (II).

The adjustment or setting of the low threshold voltage V _tL of the EEPROM of (1) above can be performed by the high voltage pulse applying means 27 shown in FIG. For example, as in the conventional case, the control word line voltage V _W = 5 V, the data “0” input data line L voltage V _L , the data “1” input data line H voltage V _H , and the match search line voltage V _S = 1.5 ~
When the voltage is 2.0V, the high threshold voltage of EEPROM is V
_{The tH} > 5V and the low threshold voltage may be set to 3.0V < _VtL <5V. The adjustment or setting of the threshold voltage V _t is performed by changing the number of high voltage pulses applied to the control gate 14 by the high voltage pulse applying means 27 or the number of times of application, as in the EEPROM 20 shown in FIG. The amount of hot electrons injected into the gate 13 may be adjusted or set, or the electrons may be extracted from the floating gate 13, and the amount of extracted electrons may be adjusted or set. Good.

Further, when the voltage of each signal line is adjusted or set in the above (2), as shown in FIG. 1, the data "1" H voltage V _H and data "1" of the first and second data lines are set. 0 "L voltage _VL is applied to each voltage control means 3 by
The drive voltage V _W of the control word line 15 can be adjusted by the voltage control means 4 and the voltage of the coincidence search line 16 can be adjusted or set by the precharge transistor 17a. Here, the voltage control means 3 and 4 are not particularly limited, and conventionally known ones can be used. For example, when using an EEPROM as shown in FIG. 4, that is, when V _tH > 6.5 V and V _tL = 0.5 to 3.5 V, for example, V _W = 4.0 V, V _H = 4.0 V, V _L = 0
It suffices to set V and V _S = 4.0V.

In the above-mentioned example, the CAM cell in which the EEPROM memory cell is a set of 2 bits is described as a representative example. However, the present invention is not limited to this, and a normal nonvolatile memory cell ( Mask ROM, EPROM, etc.)
It goes without saying that it can be applied to

In addition, the associative memory device of the present invention has a match search line and a sense amplifier (S.
A. ), The first data line (bit line) and the second data line (bit bar line) are commonly used (Japanese Patent Application No. 3-232).
No. 073 specification).

Although all the NOR type memory cells have been described so far, the present invention is also applicable to NAND type CAM cells (for this NAND type structure, Japanese Patent Application No. 3-239890). See description).

[0057]

According to the present invention, through-current between memory cells is prevented or controlled at the time of matching search in a CAM structure in which a non-volatile memory is a set of 2 bits, and matching search of a large number of memory cells is performed. It can be performed at high speed without mutual interference. Even if the voltage of each signal line cannot be largely changed, by setting the low threshold voltage of the memory cell to a required value, each of the CAs can be made different from the conventional memory cell.
Even if there is a large variation in the threshold voltage of the memory cells that form the M cell, by adjusting the voltage of each signal line, it is possible to eliminate the electrical collision between the CAM cells at the time of matching search. There is an extremely high degree of freedom in memory cell selection.

Further, by using this CAM as a database memory, which has been regarded as important in recent years, a large-capacity database system having an extremely high-speed arbitrary keyword search function can be realized.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of an associative memory device according to the present invention.

FIG. 2 E used in an associative memory device according to the present invention
FIG. 3 is a configuration diagram of an example of an EPROM memory cell.

FIG. 3 is a configuration diagram of a stack type memory for explaining an associative memory device according to the present invention.

FIG. 4 is a distribution diagram of threshold voltages of stack type memory cells used in the associative memory device shown in FIG.

[Explanation of symbols]

 1a, 1b, 2a, 2b Data line 3, 4 Voltage control means 5 Selection circuit 6 Sense amplifier 11a, 11b, 12a, 12b EEPROM cell 11, 12 CAM memory cell 13 Floating gate 14 Control gate 15 Select word line 16 Match search line 17 Match Search Sense Amplifier 17a Precharge Transistor 18 Ground Transistor 19 Match Search Data 20 EEPROM Memory Cell 21 P Substrate 22 Source Electrode 23 Drain Electrode 24 Tunnel Oxide 25 Floating Gate 26 Control Gate 27 High Voltage Pulse Applying Means

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[Procedure amendment]

[Submission date] January 29, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

The present inventor has arrived at the present invention based on the above findings. That is, the present invention relates to a first non-volatile memory cell that defines electrical connection or non-connection from the first data line to the match search line, and, in contrast, to the match search line from the second data line. An associative memory device in which a second non-volatile memory cell that defines electrical connection or non-connection and a control word line that controls the first and second non-volatile memory cells are a set of search memory word blocks. The associative memory is characterized in that the voltage of each signal line at the time of data retrieval and the threshold voltage of the nonvolatile memory cell are adjusted so as to simultaneously satisfy the following formulas (I) and (II). A device is provided. _{V W -V H <V tL <} V W -V L <V tH (I) V W -V S <V tL (II) , however, _{V tL:} low threshold voltage V _tH of the nonvolatile memory cells: the high threshold voltage V W of the nonvolatile memory _cell: voltage V H of the control word _lines: voltage indicating "1" data of the data lines V _L: voltage V _S indicating "0" data of the data lines : The voltage of the match search line.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

First, attention is paid to the memory cell 32a. The memory cell 32a must be turned on in order to extract the charge from the match search line 36 and detect the mismatch. However, the threshold voltage Vt of this transistor
Has a value of 0.5 to 3.5 V (see FIG. 4). Also,
At this time, the source electrode side becomes the data line 2a, and 0V is applied. Therefore, the voltage V _W of the select word line 35 needs to be 3.5 V or higher, and normally 4.5 V, which is higher by 1 V, seems to be suitable.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0030

[Correction method] Change

[Correction content]

Based on such a new consideration, the associative memory device according to the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 shows an embodiment of the associative memory device of the present invention. The CAM memory shown in FIG. 1 is, as described above, an EE of 2 bits, which is a unit of CAM and is a set.
It is composed of PROM memory cells. CAM
The memory cell 11 is, for example, a stack type FlashEEP.
It is composed of ROM cells 11a and 11b, and the EEPROM cells 11a and 11b are written so as to have mutually opposite memory states. Here, the EEPROM cell 1
Data “0” L (low) is written in 1a and data “1” H (high) is written in 11b.
It is assumed that data "1" H (high) is written in a and data "0" L (low) is written in 12b. These E
EPROM memory cells 11a and 11b and memory cell 12
a and 12b each form a memory pair, and a 2-bit CA
It becomes M memory cells 11 and 12.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction content]

On the other hand, the sense amplifier 6 is connected to the data line 1a by the selection circuit 5, and the data line is similarly maintained at 1.5 to 2.0V. Then, a voltage of V _W (5V) is applied to the word line 15 in the same manner, but the data line 1a
The EEPROM memory cell 11a between the line and the coincidence search line has a high threshold voltage V _tH and is set to V _W <V _tH , so that it does not turn on. Therefore, the potential of the data line 1a does not change. This is detected by the sense amplifier 6 and the result is output. In this way, the data stored in each memory cell is read. Here, the data line 1a,
The reason why the potential of 1b is set to 2 V or less is to suppress the influence on the charge accumulated in the memory cell at the time of data reading.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction content]

Here, the voltage of the data line is set to V _L (L state), the voltage of the match search line 16 is set to V _S (H state), and V _W (H state) is applied to the select word line. Suppose Then the gates of the memory cell 12a, source potential difference _{V GS} becomes _V W -V _L. That is, V _GS = (H voltage of select word line 15) − (L voltage of data line 2 a) = V _W = V _L On the other hand, the threshold voltage Vt of this EEPROM memory cell 12 a is the low threshold voltage V _tL .

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0045

[Correction method] Change

[Correction content]

In the present invention, the above formula (I) is used.
Is adjusted to satisfy V _W −V _L > low threshold voltage V _tL , the memory cell 12a is turned on,
The potential of the match search line 16 precharged by the precharge transistor 17a is lowered. The potential drop is detected by the coincidence search sense amplifier 17, and a non-coincidence signal is output.

[Procedure Amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction content]

Here, the gate-drain potential difference V _GD of the memory cell 11b becomes V _W -V _H and the gate-source potential difference V _GS becomes V _W -V _S. That is, V _GD = (H voltage of select word line 15) − (H voltage of data line 1 b) = V _W −V _H V _GS = (H voltage of select word line 15) − (voltage of match search line) = Meanwhile V _W -V _S, the threshold voltage Vt of the EEPROM memory cell 11b is a low threshold voltage _{V tL.} In the present invention, since it is adjusted so as to satisfy the above formulas (I) and (II), V _GD = V _W −V _H <V _tL and V
Since in _{GS = V W -V S <V} tL, EEPROM memory cell 11b is not turned on. Therefore, the data line 1b and the match search line 1b are kept unconnected.

[Procedure Amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction content]

The adjustment or setting of the low threshold voltage V _tL of the EEPROM of (1) above can be performed by the high voltage pulse applying means 27 shown in FIG. For example,
As in the conventional case, the control word line voltage V _W = 5 V, the data “0” input data line voltage V _L , the data “1” input data line voltage V _H , and the match search line voltage V _S = 1.5. ~ 2.
When 0V is set, the high threshold voltage of the EEPROM is set to _VtH
> 5V and the low threshold voltage may be set to 3.0V <V _tL <5V. The threshold voltage Vt is adjusted or set by changing the magnitude or the number of times of applying the high voltage pulse to the control gate 14 by the high voltage pulse applying means 27 as in the EEPROM 20 shown in FIG. It may be performed by adjusting or setting the amount of hot electrons to be injected into 13, and may be performed by extracting electrons from the floating gate 13, and further by adjusting or setting the amount of extracted electrons. Good.

[Procedure Amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction content]

When the voltage of each signal line is adjusted or set in the above (2), as shown in FIG. 1, the voltage V _H and the data “1” of the data “1” of the first and second data lines are set. The voltage V _{L of} 0 ″ is controlled by each voltage control means 3.
The drive voltage V _W of the control word line 15 can be adjusted by the voltage control means 4 and the voltage of the coincidence search line 16 can be adjusted or set by the precharge transistor 17a. Here, the voltage control means 3 and 4 are not particularly limited, and conventionally known ones can be used. For example, when an EEPROM as shown in FIG. 4 is used, that is, when V _tH > 6.5 V and V _tL = 0.5 to 3.5 V, for example, V _W = 4.0 V, V _H = 4.0 V, V _L =
It may be set to 0 V and V _S = 4.0V. As the match search sense amplifier, a current drive (detection) type sense amplifier similar to the sense amplifier 6 at the time of data reading may be used instead of the dynamic type match search sense amplifier 17 in the illustrated example. Rather, the current drive type sense amplifier is preferable because it does not have a steady drive current and is easier to adjust or set the potential of the match search line 16 than the dynamic type match search sense amplifier 17 which consumes less power.

[Procedure Amendment 12]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 13]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (3)

[Claims] 1. A first non-volatile memory cell defining electrical connection or non-connection from a first data line to a match search line, and an electrical connection from a second data line to the match search line. A associative memory device in which a second non-volatile memory cell that defines a physical connection or a non-connection and a control word line that controls the first and second non-volatile memory cells are a set of search memory word blocks. The associative memory device is characterized in that the voltage of each signal line at the time of data retrieval and the threshold voltage of the non-volatile memory cell are adjusted to simultaneously satisfy the following formulas (I) and (II). .. _{V W -V H <V tL <} V W -V L (I) V W -V S <V tL (II) , however, V _tL: low threshold voltage V _W of the nonvolatile memory cell: the control word Line voltage V _H : voltage indicating “1” data of the data line _VL : voltage indicating “0” data of the data line V _S : voltage of the match search line 2. The non-volatile memory cell has the above formula (I).
2. The associative memory device according to claim 1, wherein the associative memory device comprises a non-volatile transistor having a threshold voltage satisfying the conditions (II) and (II). 3. The associative memory device according to claim 1, further comprising means for setting a voltage at the time of detecting the data so as to simultaneously satisfy the above expressions (I) and (II). Associative memory device.