JPH05189548A - Image processor - Google Patents

Abstract

PURPOSE:To update the image data displayed on e monitor TV even in an image processing mode by connecting a reduction control circuit and a reduced image memory between a pipeline bus and a CPU bus. CONSTITUTION:The image memories 4 and output the holding image date to a pipeline bus 1. Then an image processing circuit 3 inputs the image data to carry out the image processing and then outputs the image data, i.e., the processing result to the bus 1 to store these data in both memories 4 and 5. Meanwhile a reduction control circuit 9 inputs the image date (processing result) through the line 1 to reduce the data and then stores the reduced data in a reduced image memory 10. When a CPU 6 transfers the reduced image data to a display control circuit 7 with input/output of a CPU bus 2, the circuit 7 can update the image displayed on a monitor TV 8 based on the reduced image data. Therefore the image can be updated on the TV 8 even in a continuous image processing mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus capable of updating a reduced image displayed on a monitor TV independently of an image processing operation.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, when an image processing apparatus is performing image processing such as inter-screen calculation or filtering, the image memory 4 or 5 stores the image data held therein in a pipeline bus. 1 and the image processing circuit 3 inputs the image data to perform image processing, and then outputs the image data which is the image processing result to the pipeline bus 1 and the image data which is the image processing result. The image memory 4 or 5 is input from the pipeline bus 1 and held. During this time, C
The PU 6 could not input the image data stored in the image memory 4 or 5. Therefore, after the image processing is completed, the CPU 6 inputs the image data stored in the image memory 4 or 5 and outputs the reduced image data created by performing the reduction processing to the display control circuit 7 and the monitor TV 8. The displayed reduced image was being updated.

[0003]

However, in the prior art, during continuous image processing, the CPU cannot input the image data held in the image memory and displays it on the monitor TV. However, there is a drawback that the reduced image cannot be updated and the reduced image in the state before the image processing is still displayed on the monitor TV while the image processing is being performed. Further, the image processing is interrupted, the CPU inputs the image data held in the image memory, and the reduced image data created by performing the image processing is output to the display control circuit to display the reduced image on the monitor TV. However, there is a drawback in that the image processing time is lost when is updated.

An object of the present invention is to provide an image processing apparatus capable of independently performing image processing and image reduction processing.

[0005]

In order to solve the above problems, the present invention has a configuration in which image data output to a pipeline bus can be input to both an image memory and a reduction control circuit. The reduced image of the image displayed on the monitor TV can be updated even during image processing.

[0006]

With the above-described configuration, the image data output to the pipeline bus can be input to both the image memory and the reduction control circuit, and the reduction processing can be performed even during image processing. The image data can be transferred from the reduction control circuit that is performing to the reduced image memory. As a result, the reduced image of the image displayed on the monitor TV can be updated.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the drawings. In FIG. 1, the image processing circuit 3 performs image processing on the image data input from the pipeline bus 1 and outputs the image data to the pipeline bus 1 after the image processing is completed. The reduction control circuit 9 reduces the image data input from the pipeline bus 1 and stores the reduced image data in the reduced image memory 10. In this embodiment, 1/1, 1/2, 1/4, 1/8, 1/16
Can be reduced. The image memories 4 and 5 are memories for holding image data, and input / output to / from the pipeline bus 1. The reduced image memory 10 is a memory that holds image data reduced by the reduction control circuit 9, and outputs the reduced image data to the CPU bus 2. The CPU 6 can transfer the reduced image data from the reduced image memory 10 to the display control circuit 7 by inputting / outputting the CPU bus 2. The display control circuit 7 can update the image data displayed on the monitor TV 8 each time the image data input from the CPU bus 2 is input. The pipeline bus 1 is used to transfer image data between a plurality of image memories, between image processing circuits, and between them and a reduction control circuit at high speed in a sequential and bidirectional manner. CPU bus 2 is C
It is used to transfer image data randomly and bidirectionally between the PU 6, the monitor TV 8, and the reduced image memory 10.

Next, the operation of this circuit will be described. When the image data stored in the image memories 4 and 5 is output to the pipeline bus 1, the image processing circuit 3 inputs the image data from the pipeline bus 1 to perform image processing such as inter-screen calculation and filtering. After the image processing is completed, the image data as the image processing result is output to the pipeline bus 1 and stored in the image memories 4 and 5.
At that time, the reduction control circuit 9 inputs the image data which is the image processing result from the pipeline bus 1, reduces the image data, and stores the reduced image data of the image data which is the image processing result in the reduced image memory 10 for image reduction. ..

Since the series of operations described above is executed every time image processing is performed, the reduced image data of the image data which is the image processing result at that time is the reduced image image memory 10.
It is stored in. When the CPU 6 inputs / outputs the CPU bus 2 to transfer the reduced image data to the display control circuit 7, the display control circuit 7 can update the image displayed on the monitor TV 8 with the reduced image data. .. Therefore, even when image processing is continuously performed, the image displayed on the monitor TV 8 can be updated.

Here, the reduction control circuit 9 is composed of two PLDs (programmable devices), and a 256-kbyte FIFO (first-in / first-out memory) is used as the reduced image memory, but it is not limited to these. ..

[0011]

As described above, according to the present invention, the reduction control circuit is connected between the pipeline bus and the CPU bus,
Further, since the reduced image memory is connected, there is an effect that the image data displayed on the monitor TV can be updated even during image processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus of the present invention.

FIG. 2 is a block diagram showing a conventional image processing apparatus.

[Explanation of symbols]

 1 Pipeline Bus 2 CPU Bus 3 Image Processing Circuit 4 Image Memory 5 Image Memory 6 CPU 7 Display Control Circuit 8 Monitor TV 9 Reduction Control Circuit 10 Reduced Image Memory

Claims (1)

[Claims] 1. At least a CPU, a CPU bus for controlling the input / output of data by the CPU, a monitor TV capable of displaying an image, and the CPU for transmitting the image data to the C.
A display control circuit that can output to the PU bus to update the image displayed on the monitor TV; a reduced image memory that can output to the CPU bus and hold image data; A pipeline bus capable of serially transferring image data at high speed; and a reduction control circuit for reducing the image data input from the pipeline bus and storing the image data in the reduced image memory.
An image memory that is capable of performing input / output of the pipeline bus and that is capable of holding image data, and that is capable of performing image processing on the image data input from the pipeline bus and is an image that is the result of image processing. An image processing apparatus comprising: an image processing circuit capable of outputting data to the pipeline bus.