JPH05189395A - Method and device for evaluating performance of parallel computer - Google Patents

Abstract

PURPOSE:To obtain the working set number or the working rate of entire processors at an arbitrary time point. CONSTITUTION:When a message is transmitted or received among plural processors, the respective processors execute a parallel processing. In such a case, a storing procedure 50 stores starting time and ending time when the respective processors are in an operating state and the time when the processors are in an non-operating state in the parallel processing, and a calculation procedure 60 gains the operating set number of the processors at the arbitrary time point based on the time information obtained in the storage means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer performance evaluation method and apparatus for executing parallel processing in each processor by transmitting or receiving a message between a plurality of processors.

[0002]

2. Description of the Related Art With the recent demand for high-speed and large-capacity computer systems, there is a demand for a technique for connecting a large number of processors to distribute processing. Therefore, a parallel computer in which a large number of processors each having a simple configuration are connected is provided. In such a parallel computer, each processor performs parallel processing by message communication, but the operating rate of the entire processor is particularly important.

Therefore, the following method has been conventionally used as this performance evaluation method. That is, the communication time between each processor, the barrier synchronization time for making the processors wait until all the processors issue the barrier synchronization, the execution time, etc. are measured when the parallel processing is executed, and the communication time based on the measurement result, The performance of the parallel computer was analyzed by calculating the ratio of the barrier synchronization time.

In such a performance evaluation method, the operating rate of the entire processor in the time from the start of processing to the end of processing is obtained.

[0005]

However, as a performance evaluation of a parallel computer, it is more important to know at which time the operating rate of the entire processor is decreasing. Therefore, it has been desired to obtain the operating rate of the entire processor at any time.

An object of the present invention is to provide a method and apparatus for evaluating the performance of the processing of a parallel computer which can obtain the operating number or operating rate of the entire processor at any time.

[0007]

In order to solve the above problems and achieve the object, the present invention is as follows. FIG. 1 is a principle flowchart of a performance evaluation method for a parallel computer according to the present invention. The present invention relates to a performance evaluation method for a parallel computer that executes parallel processing in each processor by transmitting or receiving a message between a plurality of processors, and a storage procedure 5
In 0, the start time and the end time when the processor is in the operating state and the time when the processor is in the non-operating state are stored for each processor in the parallel processing.
In 0, the operating number of processors at an arbitrary time is obtained based on the time information obtained in the storage procedure 50.

Further, the storage procedure 50 is such that, for each processor, the message transmission start time, transmission end time, reception start time, reception end time, interrupt process start time, end time, The time of the task switch for selecting the task to be executed while observing the priority of the task is stored, and the start time and end time of the process are stored as the time information of the operating state of the processor.

Further, in the calculation procedure 60, in the procedure 61,
In each processor, time information is searched in order from the earliest time information among the time information, and in step 62, it is determined whether each processor is in the operating state based on each time information obtained in step 61. In step 63, Based on the judgment output of step 62, the operating number of processors at an arbitrary time is obtained, and the processing from step 61 to step 63 is repeated to obtain the temporal change of the operating number.

Further, a temporal change in the number of operating machines is recorded, and based on the recorded number of operating machines, the operating rates of all processors at an arbitrary time are obtained. Further, the calculation procedure 60 prepares a message transmission flag, a message reception flag, and an interrupt flag for indicating the state of each task for each task of each processor, and uses each time information obtained in the storage procedure 50 to calculate each task. At the beginning of message transmission,
At the start of reception and at the start of an interrupt, each flag is set, and at the end, each flag is reset. Based on the time between setting and resetting each flag, the message transmission time, reception time, interrupt time of each processor at an arbitrary time, I tried to find the execution time.

FIG. 2 is a principle diagram of a performance evaluation apparatus for a parallel computer according to the present invention. In a performance evaluation device for a parallel computer that executes parallel processing in each processor 2 by transmitting or receiving a message among a plurality of processors 2,
The timer 1 measures, for each processor 2, the operation start time and the operation end time when the processor is in the operating state and the time when the processor is in the non-operation state, and the storage unit 21 measures the time for each processor 2. The time information measured by the timer 1 is stored, and the operation unit 4 determines the operating number of the processors 2 at an arbitrary time based on the time information stored in the storage unit 21.

Further, in the calculating means 4, the retrieving means 42 retrieves the time information in order from the earliest time information among the respective time information in each processor 2, and the determining means relies on each processor based on the retrieved time information. It is determined whether or not No. 2 is in the operating state, and the operating unit number calculation unit obtains the operating unit number of the processor at an arbitrary time from the determination output, and obtains the temporal change of the operating unit number.

Further, the arithmetic means 4 has an output means 45 for outputting a temporal change in the number of operating processors 2. Further, the calculating means 4 is provided with an operating rate calculating section 46 for calculating the operating rate of the processor at an arbitrary time based on the temporal change in the operating number of each processor 2 output from the output means 45.

Further, the arithmetic means 4 prepares, for each task of each processor 2, a message transmission flag, a message reception flag and an interrupt flag for indicating the state of each task, and the time information obtained by the storage means 21 is obtained. For each task, each task has a flag generator 47 that sets each flag at the start of message transmission, at the start of reception, and at the start of interrupt, and resets each flag at the end, and sets each flag by this flag generator 47. It is characterized by having a time calculation unit 48 for calculating a message transmission time, a reception time, an interrupt time, and an execution time of each processor 2 at an arbitrary time based on the time between the reset and the reset.

Further, each processor 2 has a storage means 2
1. Search means 42 for searching the time information in order from the earliest time information among the time information in each processor 2, and determining whether each processor 2 is in the operating state based on each time information searched by the search means 42. Determining unit 43, and an operating unit number calculating unit 44 that determines the operating unit number of the processor at an arbitrary time based on the determination output of the determining unit 43,
An output unit 45 that outputs a temporal change in the operating number of each processor 2, and an operation that calculates an operating rate of the processor at an arbitrary time based on the temporal change in the operating number of each processor 2 output from the output unit 45. The rate calculating unit 46 is provided, and the processing in each unit and each unit is performed in parallel in each processor 2.

[0016]

According to the present invention, in the arithmetic procedure, the number of operating processors at any time can be obtained based on the start time and end time time information when the processor obtained in the storing procedure is in the operating state. , Performance evaluation of parallel computers can be performed.

In each processor, the time information is searched in order from the earliest time information among the time information, and it is determined whether each processor is in the operating state based on the time information. It is also possible to obtain the number of operating processors and repeat these processes to obtain a temporal change in the number of operating processors.

Further, it is also possible to record a change in the number of operating machines over time and obtain the operating rates of all the processors at an arbitrary time based on the recorded number of operating machines. Also, using each time information, each flag is set at the time of message transmission start, message reception start, and interrupt start for each task, and each flag is reset at the end, and the time between setting and resetting each flag is set. It is also possible to obtain the message transmission time, the reception time, the interrupt time, and the execution time of each processor based on the above.

Further, the time information measured by the timer is stored in the storage means for each processor, and the operating means obtains the operating number of processors at any time based on the time information stored in the storage means. be able to.

Further, the searching means searches the time information in order from the earliest time information among the time information in each processor, and the judging means determines whether or not each processor is in the operating state based on the searched time information. Then, the operating unit number calculation unit determines the operating unit number of the processor at an arbitrary time based on the determination output, so that the temporal change of the operating unit number can be obtained.

Further, the output means can output a temporal change in the number of operating processors. Furthermore, the operating rate calculation unit can calculate the operating rate of the processor at an arbitrary time based on the temporal change in the operating number of each processor output from the output means.

Furthermore, by using each time information obtained by the storage means, each flag is set by the flag generator at the start of message transmission, at the start of reception, and at the start of interrupt for each task, and reset at the end. However, based on the time between the setting and resetting of each flag, the time calculation unit can determine the message transmission time, reception time, interrupt time, and execution time of each processor at an arbitrary time.

Further, since each processor has each means and each part, the processing in each means and each part can be performed in parallel by each processor 2.

[0024]

EXAMPLES Specific examples of the present invention will be described below.
FIG. 3 is a configuration block diagram of a first embodiment of a performance evaluation apparatus for realizing a performance evaluation method for a parallel computer according to the present invention, and FIG. 4 is a flow chart of the performance evaluation method for the parallel computer.

In FIG. 3, the performance evaluation device for a parallel computer is constructed as follows. Multiple processors 2 (2-
1 to 2-N) are connected to the clock generator 1, and the clock generator 1 generates a clock signal, and the message transmission start time and the message transmission end for each of the processors 2-1 to 2N. Task switch to select the task to be executed while checking the time, message reception start time, message reception end time, interrupt processing start time that interrupts during processing execution, interrupt processing end time, task priority The time, execution process start time, and execution process end time are measured.

The processors 2-1 to 2-N are connected to an interconnection network (network NW) 3, and the interconnection network 3 connects the processors 2-1 to 2-N to each other. Message communication can be performed between -1 to 2-N.

The control circuit 4 is connected to the interconnection network 3,
The mutual connection network 3 is instructed as to which processor should perform message communication. Each processor 2
-1 to 2-N operate in parallel, and are information memories 21 (21-1 to 21-N) that store various kinds of information.
Is equipped with.

Each of the information memories 21-1 to 21-N stores the following information when parallel processing is executed. Information (1) Store the message transmission start time. Information (2) The message transmission end time is stored. Information (3) The message reception start time is stored. Information (4) The message reception end time is stored. Information (5) The interrupt processing start time is stored. Information (6) The interrupt processing end time is stored. Information (7) The time of the task switch is stored. Information (8) The execution process start time is stored. Information (9) The execution processing end time is stored.

Each information has the following format. The types of information include information (1) to information (7), and the task number is the number given to the task currently being executed.

The determination of the operating state of the application task of each processor is performed as follows. The transmission time of the message is the time of information (1) and (2), and the reception time of the message is the time of information (3) and (4). The interruption time is the time of the information (5) and (6), and the tasks other than the application task, for example, the null task are the times of the information (7) and (7).

The time from the information (8) to the information (9) excluding these times becomes the operating state. Using this information, the operating number P of the processors 2 is obtained. The number of processors is N.

The control circuit 4 controls the above-mentioned mutual coupling network 3 and has the following parts and devices. The information collecting memory 41 stores the respective times collected from the information memories 21-1 to 21-N of the processors 2-1 to 2-N via the mutual connection network 3.

The control circuit 4 is constructed as follows. The search unit 42 sequentially searches the time information from the earliest time information among the time information in each processor 2, and outputs the search result to the operation determination unit 43.

The operation judging unit 43 judges whether each processor 2 is in the operating state based on each time information searched by the searching unit 42, and outputs the judgment output as the operating unit number calculating unit 44.
Output to.

The operating machine number calculating unit 44 obtains the operating machine number of the processor at an arbitrary time from the judgment output of the operation judging unit 43, and outputs it to the recording unit 45. Recording unit 45
Is a printer or the like, which outputs a temporal change in the operating number of each processor 2 from the operating number calculating unit 44. As shown in FIG. 5, the horizontal axis indicates time and the vertical axis indicates operating number. Set and record the change in the number of operating machines over time.
The display may be displayed on the display device.

The operating rate calculating section 46 calculates the operating rate of the processor at an arbitrary time based on the temporal change in the operating number of each processor 2 output from the recording section 45.
At this time, the operating rate from time A to time B is the period T
It is obtained by the ratio of the area (area / TN).

The program 40 is an instruction for performing the flow shown in FIG. 4, and gives this instruction to the information collecting memory 41 and each section. Next, a first embodiment of a performance evaluation method for a parallel computer according to the present invention will be described with reference to FIGS.

In the parallel processing, the information generators 21-1 to 21-N in the processors 2-1 to 2-N have message transmission start time, message transmission end time, message reception start time, and The message reception end time, interrupt process start time, interrupt process end time, task switch time, execution process start time, and execution process end time are measured.

At this time, each time information measured by the clock generator 1 for each processor 2-1 to 2-N is stored in each information memory 21-1 to 21-N (step 51). .. That is, each of the information memories 21-1 to 21-1
In 21-N, time information is stored in order from the earliest time.

Next, each time information stored in each information memory 21-1 to 21-N is collected in the information collecting memory 41 via the mutual connection network 3 (step 52). The following processing is performed using each time information from the information collecting memory 41. 0 is set as the initial value of the operating number P (step 53). The search unit 42 searches the information collecting memory 41 for each time information from the earliest time information among the time information of all the processors (step 54). Then, the operation determining unit 43 determines whether the processor 2 is in the operating state (step 55), and the operating unit number calculating unit 44 determines that the processor 2 is not in the operating state.
Only one is subtracted from the operating number P (step 57), and the process proceeds to step 58.

If it is in the operating state, 1 is added to the operating number P (step 56), and the operating number P at this time is written in the recording unit 45 together with the time (step 58).
It is judged whether or not the processing of the information of all the processors 2 is completed (step 59), and when the processing is completed, the processing returns to step 54 and the processing from step 54 to step 58 is repeated every time.

By doing so, a temporal change in the operating number as shown in FIG. 5 can be obtained, and it is possible to recognize at which time the operating rate is decreasing. Therefore, the cause of the performance degradation of the parallel computer can be understood, and the bottleneck of the program can be known.

At this time, the operating rate from the time A to the time B is obtained by the operating rate calculating section 46 by the ratio of the area of the shaded portion in the period T shown in FIG. 5 and the area / TN. Can be used to determine the operating rate at any time.

FIG. 6 is a block diagram showing the configuration of the second embodiment of the performance evaluation apparatus for a parallel computer. Second Embodiment Next, a second embodiment will be described with reference to the drawings. The feature of the second embodiment is that each of the processors 2-1 to 2-N has an information memory 21-
1 to 21-N, search units 42-1 to 42-N, operation determination units 43-1 to 43-N, operating unit number calculation units 44-1 to 44-
N, the operation rate calculation units 45-1 to 45-N, and the control circuit 4 includes the program 40 and the recording unit 45.

According to such a configuration, each processor 2
In -1 to 2-N, the processing of each unit is performed in parallel, and the number of operating machines and the operating rate are obtained. Therefore, the same effect as that of the first embodiment is obtained.

FIG. 7 is a block diagram showing the configuration of the third embodiment of the performance evaluation device for a parallel computer, and FIG. 9 is a flow chart of the performance evaluation method for a parallel computer of the third embodiment. In FIG. 7, the flag generator 47 prepares, for each task of each processor 2, a message transmission flag, a message reception flag, and an interrupt flag for indicating the status of each task, and time information obtained by the information collection memory 41. Is used to set each flag at the start of message transmission, at the start of reception, and at the start of interrupt for each task, and reset each flag at the end.

The time calculator 48 calculates the time between the setting and resetting of each flag by the flag generator 47.
The message transmission time, the reception time, the interrupt time, and the execution time of each processor 2 at an arbitrary time are obtained.

Next, a third embodiment of the present invention will be described with reference to the drawings.
A method of obtaining the message transmission time, the interrupt time, and the execution time of the task of each processor at an arbitrary time by using the information of each time stored in the information memory when executing the processing will be described below.

First, three types of flags, that is, a message transmission flag, a message reception flag, and an interrupt flag are prepared for each task of each processor. The program 40 is started (step 70), and it is determined whether or not there is any event from the above information (1) to information (9) (step 71). If there is no event, the process ends (step 72).

If there is an event, the difference between the event time and the previous event time, that is, the time is calculated by the time calculation unit 48 (step 73), and it is determined whether or not the interrupt flag is set (step 74). .. If the interrupt flag is set, the time is added to the interrupt time (step 75) and the process proceeds to step 81.

If the interrupt flag is not set, it is judged whether or not the message transmission flag is set (step 76). If the message transmission flag is set, the time is set in the message transmission time. Add (step 77) and proceed to step 81.

Next, it is judged whether or not the message transmission is started (step 81). If the message transmission is started, the flag generator 47 sets the message transmission flag (step 82) and step 71.
Return to.

When the message transmission is not started, it is judged whether or not the message transmission is completed (step 83). When the message transmission is completed, the message transmission flag is reset by the flag generator 47. (Step 84) and the process returns to Step 71.

If the message has not been transmitted, it is judged whether or not the message has been received (step 85). If the message has been received, the message reception flag is set by the flag generator 47. Then (step 86), the process returns to step 71.

If the reception of the message is not started, it is judged whether or not the reception of the message is completed (step 87). If the reception of the message is completed, the message reception flag is reset by the flag generator 47. Then (step 88), the process returns to step 71.

When the reception of the message is not completed, it is judged whether or not the interrupt is started (step 89). When the interrupt is started, the interrupt processing flag is set by the flag generator 47. (Step 90) and returns to Step 71.

If the interrupt is not started, it is judged whether or not the interrupt is ended (step 9
1) If the interrupt is completed, the interrupt processing flag is reset by the flag generator 47 (step 92) and the process returns to step 71.

If the interrupt has not ended, a task switch for selecting while looking at the priority is generated (step 93), the state of the task to be executed is changed (step 94), and the process proceeds to step 71. Return.

Since the processing is performed in this manner, the message transmission time, the message reception time, the interrupt time, and the execution time at any time can be obtained. Further, the second and third embodiments may be used in combination.

[0060]

According to the present invention, the operating rate or the number of operating processors of a processor at an arbitrary time can be obtained. As a result, it can be seen that the operating rate of the processor is decreasing, and the bottleneck of the program can be known.

Further, the message transmission time, message reception time, interrupt time, and execution time of each processor can be known by using the information stored at the time of execution.

[Brief description of drawings]

FIG. 1 is a principle flow chart of a performance evaluation method for a parallel computer according to the present invention.

FIG. 2 is a principle diagram of a performance evaluation device for a parallel computer according to the present invention.

FIG. 3 is a configuration block diagram of a first embodiment of a performance evaluation apparatus for realizing a performance evaluation method for a parallel computer according to the present invention.

FIG. 4 is a flowchart of a performance evaluation method for a parallel computer according to the first embodiment.

FIG. 5 is a diagram showing a temporal change in the number of operating machines.

FIG. 6 is a configuration block diagram of a second embodiment of the performance evaluation apparatus.

FIG. 7 is a configuration block diagram of a third embodiment of the performance evaluation apparatus.

FIG. 8 is a flowchart of a performance evaluation method for a parallel computer according to a third embodiment.

FIG. 9 is a flowchart of a performance evaluation method for a parallel computer according to the third embodiment.

[Explanation of symbols]

 1. Clock generator 2. Processor 3. Mutual interconnection network 4. Control circuit 21. Information memory 40 .. Program 41 .. Information collecting memory 42 .. Operating rate calculation unit 43 .. Operating rate memory 44.・ ・ Operating number calculation unit 45 ・ ・ Recording unit 46 ・ ・ Operating ratio calculation unit 47 ・ ・ Flag generation unit 48 ・ ・ Time calculation unit

Claims (11)

[Claims] 1. A method for evaluating the performance of a parallel computer, wherein a parallel processing is executed by each processor by transmitting or receiving a message between a plurality of processors, wherein the processor is in an operating state for each processor in the parallel processing. A storage procedure for storing the start time and the end time and the time when the processor is in the inactive state (5
0) and a calculation procedure (60) for obtaining the number of operating processors at an arbitrary time based on the time information obtained in the storage procedure (50). 2. The storage procedure (50) includes, for each of the processors, transmission start time, transmission end time, reception start time, reception end time, interrupt processing of the message as time information of the non-operation state of the processor. The start time, the end time, and the time of the task switch for selecting the task to be executed while checking the priority of the task are stored, and the start time and the end time of the process are stored as the time information of the operating state of the processor. The performance evaluation method for a parallel computer according to claim 1. 3. The calculation procedure (60) includes a procedure (61) for searching the time information in order from the earliest time information among the time information in each processor, and time information obtained in the procedure (61). Based on the procedure (62), it is determined whether or not each processor is in the operating state.
A procedure (63) for obtaining the number of operating processors at an arbitrary time based on the determination output of 2), and the processing from the procedure (61) to the procedure (63) is repeated to change the temporal change of the operating number. The performance evaluation method for a parallel computer according to claim 1, wherein the method is obtained. 4. Recording the change in the number of operating machines over time,
4. The performance evaluation method for a parallel computer according to claim 3, wherein the operating rates of all the processors at an arbitrary time are calculated based on the recorded operating numbers. 5. The calculation procedure (60) prepares, for each task of each processor, a message transmission flag, a message reception flag, and an interrupt flag for indicating the state of each task, and the storage procedure (50) Using the obtained time information, each flag is set at the start of message transmission, at the start of reception, and at the start of interrupt for each task, and each flag is reset at the end, and at the time between setting and resetting each flag. 3. The performance evaluation method for a parallel computer according to claim 2, wherein the message transmission time, the reception time, the interrupt time, and the execution time of each processor are calculated based on the arbitrary time. 6. A performance evaluation apparatus for a parallel computer, wherein each processor (2) executes parallel processing by transmitting or receiving a message between a plurality of processors (2), wherein each processor (2) is a processor. (1) that measures the operation start time and operation end time when the processor is in operation and the time when the processor is not in operation
And the timer (1) for each processor (2)
Storage means (21) for storing each time information measured in
And a computing means (4) for obtaining the number of operating processors (2) at an arbitrary time based on the time information stored in the storage means (21). 7. The calculating means (4) comprises a searching means (42) for searching time information in order from the earliest time information among the time information in each processor (2), and the searching means (42). A determination unit (43) that determines whether or not each processor (2) is in the operating state based on the retrieved time information, and the number of operating processors at any time based on the determination output of the determination unit (43). 7. The performance evaluation device for a parallel computer according to claim 6, further comprising a required operating number calculation unit (44) for determining a temporal change in the operating number. 8. The parallel computer according to claim 6, wherein the computing means (4) has an output means (45) for outputting a temporal change in the number of operating processors (2). Performance evaluation device. 9. The calculating means (4) calculates the operating rate of the processor at an arbitrary time based on the temporal change in the operating number of each processor (2) output from the output means (45). The performance evaluation device for a parallel computer according to claim 6, further comprising an operation rate calculation unit (46). 10. The computing means (4) prepares, for each task of each processor (2), a message transmission flag, a message reception flag and an interrupt flag for indicating the status of each task, and the storage means ( Using the time information obtained in 21), at the start of message transmission for each task,
Flag generator (47) that sets each flag at the start of reception and interrupt and resets each flag at the end
And a time for obtaining a message transmission time, a reception time, an interrupt time, and an execution time of each processor (2) at an arbitrary time based on the time between setting and resetting each flag by the flag generator (47). Calculation unit (4
8. The performance evaluation device for a parallel computer according to claim 6, further comprising: 11. The processor (2) includes: the storage means (21); and a search means (42) for sequentially searching the time information from the earliest time information among the time information in each processor (2). , Each processor (2) based on each time information retrieved by the retrieval means (42)
Determination means (43) for determining whether or not is in operation
And an operating unit calculation unit (44) for obtaining the operating unit number of the processor at an arbitrary time based on the determination output of the determining unit (43), and an output unit for outputting a temporal change in the operating unit number of each processor (2). (45), and an operation rate calculation unit (46) for calculating the operation rate of the processor at an arbitrary time based on the temporal change of the operating number of each processor (2) output from the output means (45). 7. The performance evaluation apparatus for a parallel computer according to claim 6, further comprising: and each processor (2) performing the processing in each of the means and each unit in parallel.