JPH05183435A - Pll frequency synthesizer - Google Patents

Abstract

PURPOSE:To reduce the transient response caused when an output frequency is selected, to converge the response at a high speed and to decrease noise in the vicinity of a carrier in the steady state by decreasing an open loop gain of an active filter at the frequency changeover. CONSTITUTION:A variable frequency divider 105 frequency-divides an output of a VCO 108 based on a frequency division signal inputted from a frequency division input terminal 101. A frequency phase comparator 106 compares an output of the frequency divider 105 with a reference signal inputted from a reference frequency input terminal 102 and outputs the result. An active loop filter 107 smooths an output of the frequency phase comparator 106 and selects the amplification factor based on a gain switching signal and amplifies the signal for the output. The VCO 108 outputs a signal with a frequency based on an output voltage of the filter 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL frequency synthesizer, and more particularly to a PLL frequency synthesizer capable of switching output frequencies at high speed and reducing output phase noise.

[0002]

2. Description of the Related Art Conventionally, as a PLL frequency synthesizer of this type, there is a loop circuit shown in FIG. In FIG. 5, a frequency division number signal which is a signal for controlling the frequency division number in the variable frequency divider 105 is input to the frequency division number input terminal 101. The reference frequency input terminal 102 has a PLL shown in FIG.
A reference frequency signal having a reference frequency in the frequency synthesizer is input. A band switching signal for switching the pass frequency band in the loop filter 507 is input to the band switching input terminal 503. When the band switching signal is input, the loop filter 507 increases the gain, changes the filter character, or both. As a result, the output frequency in the loop circuit shown in FIG. 5 rapidly converges to a certain range.

Next, when a band switching signal for returning to the original band is input from the band switching input terminal 503, the loop filter 507 lowers the gain, narrows the filter character, or both. To do.
As a result, the output frequency band in the loop circuit shown in FIG. 5 is narrowed, and noise near the carrier is reduced.

Here, in the PLL frequency synthesizer shown in FIG. 5, the variable frequency divider 105 includes a frequency division number input terminal 1
The output of the voltage controlled oscillator 108 is frequency-divided on the basis of the frequency division signal input from 01. The frequency phase comparator 106 is
The output of the variable frequency divider 105 is compared with the reference frequency signal input from the reference frequency input terminal 102, and this result is output. The loop filter 507 is the frequency phase comparator 1
The output of 06 is smoothed, and the voltage for controlling the output frequency of the voltage controlled oscillator 108 is output.

[0005]

However, in the above-mentioned conventional PLL frequency synthesizer, the frequency characteristic of the loop circuit is largely switched, which causes a problem that a large transient response is likely to occur at the time of switching. Further, during the transient response, the loop circuit is switched to have a small gain or a narrow output frequency band, so that the large transient response has a problem of slow convergence.

The present invention has been made in view of the above problems, and it is possible to reduce the transient response that occurs when the output frequency is switched and to converge it at high speed. It is an object of the present invention to provide a PLL frequency synthesizer capable of reducing the noise.

[0007]

A PLL frequency synthesizer according to the present invention includes a reference frequency input section for inputting a reference frequency signal, a voltage controlled oscillator whose oscillation frequency is controlled by the input voltage, and a voltage controlled oscillator for the voltage controlled oscillator. A variable frequency divider that divides the output by a value based on the input frequency division signal,
A frequency phase comparator that compares the output of the variable frequency divider with the reference frequency signal and outputs the result, and a loop filter that smooths the output of the frequency phase comparator and outputs the smoothed output to the voltage controlled oscillator. In the PLL frequency synthesizer that has, it is characterized in that the loop filter is an active loop filter that changes an open loop gain by a signal input from the outside.

[0008]

In the PLL frequency synthesizer according to the present invention, the active loop filter smoothes the output of the frequency phase comparator when the output frequency is switched,
Furthermore, the open loop gain can be changed by a signal input from the outside. When switching the output frequency, keep the open loop gain of the active loop filter high until the frequency of the output of the voltage controlled oscillator stabilizes, and after the output frequency stabilizes, open the active loop filter. Lower the loop gain. As a result, the transient response that occurs when the frequency is switched can be reduced, and it can be converged at high speed. Further, it is possible to reduce noise near the carrier in the steady state.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a PLL frequency synthesizer according to an embodiment of the present invention. In the present embodiment, the main difference from the conventional PLL frequency synthesizer shown in FIG. 5 is that an active loop filter 107 is provided instead of the loop filter 507 shown in FIG. The active loop filter 107 can input a gain switching signal from the gain switching input terminal 103 to switch the amplification degree.

Next, the operation of the PLL frequency synthesizer according to this embodiment constructed as described above will be explained.
The variable frequency divider 105 divides the output of the voltage controlled oscillator 108 based on the frequency division number signal input from the frequency division number input terminal 101. The frequency / phase comparator 106 includes the variable frequency divider 10
5 is compared with the reference frequency signal input from the reference frequency input terminal 102, and this result is output. The active loop filter 107 includes a frequency phase comparator 106.
Output is smoothed, and the amplification degree is switched based on the gain switching signal to be amplified and output. The voltage controlled oscillator 108 outputs a signal having a frequency based on the output voltage of the active loop filter 107. First, in order to switch the output frequency at the output terminal 104, when a frequency division number signal different from the frequency division number set up to now is input from the frequency division number input terminal 101, the active loop is input from the gain switching input terminal 103. A gain switching signal for increasing the open loop gain of the filter 107 is input. After that, when the output frequency in the loop circuit of the present embodiment becomes stable, the active loop filter 107
A gain switching signal for lowering the open loop gain of is input from the gain switching input terminal 103.

For example, even if the output frequency is stable without such gain switching, leaving the open loop gain in a high state causes a problem in the following design. Noise in the vicinity of the case where the band band is widened to shorten the output frequency switching time is generated by the variable frequency divider 105, the frequency phase comparator 106 and the active loop filter 107, assuming that the characteristics of each block are linear. Noise that is converted into a reference frequency signal input from the reference frequency input terminal 102 and noise that is generated by the voltage controlled oscillator 108 is converted into noise at the output terminal 104.
The relationship between each of these noises and the noise output from the output terminal 104 is represented by the following mathematical formulas 1-3.

[0013]

[Equation 1] Reference frequency signal conversion output = N ² | H
(ω) ｜ ² PNref

[0014]

## EQU00002 ## Output of the voltage controlled oscillator 108 = | 1-
H (ω) ｜ ² PNvco

[0015]

## EQU3 ## H (ω) = (KdKvF (ω) / Nω) / (1+
KdKvF (ω) / Nω) where PNref: reference frequency signal conversion noise PNvvco: V of noise generated by the voltage controlled oscillator 108
CO output conversion noise Kd: Gain of frequency phase comparator 106 [V / rad] Kv: Gain of voltage controlled oscillator 108 [rad / V] F (ω): Transfer function of active loop filter 107 N: Variable frequency divider Dividing number of 105 ω: Angular frequency

Next, the case where the active loop filter 107 is configured as shown in FIG. 2 will be described. Figure 2
FIG. 2 is a circuit diagram showing an embodiment of active loop filter 107 shown in FIG. 1. Set the gain of amplifier 206 to G [d
B], the relationship between the input 201 and the output 202 is expressed by the following mathematical formula 4.

[0017]

(4) F (ω) = VOUT / VIN = {-(R2 + 1 / ωC) /
G} / {1- (1+ (R2 + 1 / ωC) / R1) / G} where VIN: input voltage of input 201 VOUT: output voltage of output 202 R1: resistance value of resistor 203 R2: resistance 204 Resistance value C: capacitance value of the capacitor 205

As the above equation shows, the voltage controlled oscillator 108
When the noise of is low near the output frequency, the reference frequency signal conversion noise has a large value. Figure 4 shows Kv
= 2π × 10 7, Kd = 75, N = 8000, R1 = 10
0K, R2 = 3.9K, C = 0.022μF, G
= 100 and G = 1000, N2 | H (ω) | 2
It is a graph which shows the characteristic of. As shown in FIG. 4, by decreasing the open loop gain G of the amplifier 206,
The output noise level can be lowered. Here, the only characteristic that changes in this loop circuit is the gain,
Other properties are not affected. Active loop filter 1
When the gain at 07 decreases, the noise near the output frequency at the output terminal 104 decreases, and therefore the phase noise for the carrier is reduced. As a means for reducing the open loop gain of the amplifier 206, there is, for example, a means for lowering the power supply voltage of the amplifier.

As described above, the PL according to this embodiment
Since the L frequency synthesizer can reduce the output noise level without affecting other characteristics by reducing the open loop gain of the amplifier 206, the influence of the gain switching on the entire loop circuit is significantly reduced. ..

FIG. 3 shows an embodiment of a circuit for switching the open loop gain in the PLL frequency synthesizer according to this embodiment. The difference between the signals input from the first differential input terminal 301 and the second differential input terminal 302 is output from the first differential output terminal 303 and the second differential output terminal 304. At this time, when a switching signal for selecting the resistors 314 and 316 is input from the first switching input terminal 305 and the second switching input terminal 306, the first N-channel MOSFET
When the transconductance of both 310 and the second N-channel MOSFET 311 is gM and the resistance values of the resistors 314 and 316 are R1, the voltage gain of the amplifier shown in FIG. 3 is proportional to gMR1.

On the other hand, the first switch 312 and the second switch 3 are selected so that the resistors 315 and 317 are selected.
When 13 is switched, the voltage gain of the circuit for switching the open loop gain shown in FIG. 3 is proportional to gMR2 when the resistance values of the resistors 315 and 317 are R2. That is, the first switch 312 and the second switch 3
By switching 13 the voltage gain is R1 /
Change to R2.

Therefore, the circuit for switching the open loop gain shown in FIG. 3 is R when the frequency is switched in the PLL frequency synthesizer according to the present embodiment.
The open loop gain can be switched to 1 by switching to R2 when stable (R1> R2).

[0023]

As described above, the PLL according to the present invention
According to the frequency synthesizer, by reducing the open loop gain of the active loop filter at the time of frequency switching, it is possible to reduce the transient response generated at the time of frequency switching, and it is possible to quickly converge. Further, it is possible to reduce noise near the carrier in the steady state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a PLL frequency synthesizer according to an embodiment of the present invention.

2 is a circuit diagram showing an embodiment of an active loop filter 107 shown in FIG.

FIG. 3 is an embodiment of a circuit for switching the open loop gain in the PLL frequency synthesizer according to the embodiment of the present invention.

FIG. 4 is a graph showing frequency characteristics of output noise power in the PLL frequency synthesizer according to the embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional PLL frequency synthesizer.

[Explanation of symbols]

 101; Frequency division number input terminal 102; Reference frequency input terminal 103; Gain switching input terminal 104; Output terminal 105; Variable frequency divider 106; Frequency phase comparator 107; Active loop filter 108; Voltage controlled oscillator

Claims (3)

[Claims] 1. A reference frequency input section for inputting a reference frequency signal, a voltage controlled oscillator whose oscillation frequency is controlled by an input voltage, and an output of the voltage controlled oscillator with a value based on the input frequency division signal. A variable frequency divider that divides the frequency, a frequency phase comparator that compares the output of the variable frequency divider with the reference frequency signal and outputs the result, and an output of the frequency phase comparator is smoothed to obtain the voltage. A PLL frequency synthesizer having a loop filter for outputting to a controlled oscillator, wherein the loop filter is an active loop filter that changes an open loop gain according to a signal input from the outside. 2. When the output of the voltage controlled oscillator is switched, the open loop gain of the active loop filter is kept high until the frequency of the output of the voltage controlled oscillator becomes stable, and the output frequency becomes stable. 2. The P ratio according to claim 1, wherein the open loop gain of the active loop filter is lowered after the operation.
LL frequency synthesizer. 3. The active loop filter comprises an amplifier section having a differential pair of two transistors, a gain switch having a plurality of switches and a plurality of resistors for changing the amplification degree of the amplifier section by a signal from the outside. The PLL frequency synthesizer of claim 1, further comprising: