JPH05182419A - Address detection system of optical disk - Google Patents

Abstract

PURPOSE:To speedily perform an error check by comparing the decoded signals of a first track address and encoding it again and the reproduced signals of a second track address so as to detect an address detection error. CONSTITUTION:The address data of the reproduced signals from an optical disk 1 are supplied to an address decoder 10 through a decoder 8, non-gray coded, inputted to registers 11A to 11E, extract track addresses MSB to LSB as a total output and perform a desired track jump based on the output. On the other hand, the outputs of the resisters 11 are inputted to an address encoder 12, the track addresses are gray coded and at a comparator 13, a coincident detection is performed between the output data of the decoder 8 and the output of the address encoder 12. By these operations, an error generation detection is completed almost at the same time of the completion of an address reproduction scanning resulting in a faster error check.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address detection system for an optical disc in which address information having the same content is continuously written and added to each track of the optical disc.

[0002]

2. Description of the Related Art A recording layer for storing data in response to light is provided on a recording surface of an optical disk to record information optically.
An optical recording / reproducing device capable of reproducing this information has been put into practical use. As such an optical disk, a read-only ROM disk (CD), a magneto-optical disk whose data can be rewritten by the user, and the like are well known. The magneto-optical disk as described above is generally provided with concentric or spiral recording tracks on the recording surface side, and each track is divided in the circumferential direction, and one track is divided into a plurality of sectors. Has been done.

As shown in FIG. 7 (a), the data recorded in one sector is divided into, for example, 32 segments, and the tip of each segment is preliminarily processed by embossing or the like to form a sample servo pit. Is recorded in the servo byte area SB.

Address information is recorded in the header 1 at the tip of each sector, and the latter half of the header 1 has an ALPC area (Automatic Laser Power Control Are).
a). Further, recording information is input to the next header 2, and a pre-write area in which data can be experimentally written can be secured in the header 2 portion. Then, 30 segments SG _{1 to} S capable of recording the input data will be described below.
G ₃₀ is provided.

As shown in the enlarged view of FIG. 7 (b), the header 1 is first provided with a servo byte area SB, followed by a track address TA consisting of a 10-digit word indicating a track address, and a sector. A 2-digit sector address SA indicating the mark is recorded.

In the servo byte area SB of each segment in one track, 1 is set to indicate the relative position of the track.
A hexadecimal gray code GC is provided, and this code is used as an access code during traverse, and wobbling pits P ₁ and P ₃ and clock pits P ₂ that provide tracking information to the optical head are formed in advance. ing.

Data indicating the track address in the header 1 is MSB, 2SB, 3SB, 4SB, LS.
Data of 5 words consisting of B is recorded as a track address 1. In addition, continue to LSB, 4SB, 3S
Data of 5 words is recorded as a track address 2 in the order of B, 2SB, and MSB. Since the addresses are double-written in this way, it is possible to perform the address detection error check by detecting the coincidence between the track address 1 and the track address 2 during the address reproduction. There is also a system in which the track address 2 is composed of parity data for the track address 1 and the address detection error check is performed by the parity check.

By the way, the track address 1 is pre-formatted from the MSB side, and the track address 2 is LSB.
The reason for pre-formatting from the side is to make it easier to read the LSB side, which has a large change even during seeking. In other words, both track addresses 1 and 2 are MSBs
When recording is performed from the side, accurate reading on the LSB side is difficult when pickup scanning is performed as shown by the dotted arrow in FIG. 8A, but as shown in FIG.
Having B adjacent to each other facilitates accurate reading of the LSB.

In the optical disc on which the address information as described above is recorded, the track address at the beginning of each sector is read at the time of traverse to access the desired track from the current track. By reading the gray code located at the beginning of each segment showing the low order bits,
You can know the current position during the traverse.

By the way, in recent years, when the laser beam can move rapidly in the radial direction of the optical disk due to the weight reduction of the optical head and the improvement of the seek speed, the track address recorded in the header 1 encountered during the seek is changed. It becomes more and more difficult to read out accurately, and misreading of this track address may result in a failure in smooth high-speed seek.

If the absolute address of the track cannot be read at the seek end point, smooth landing is hindered, resulting in a longer seek time. For this reason, it has been considered that the address information recorded in the header 1 is partially gray-coded so that the track position does not greatly differ from a data reading error.
Even in this case, since the gray code is not arranged as the entire address code, the track position may be largely erroneous due to a defect or the like generated in the data portion.

Therefore, the m-ary gray code forming each digit of the track address is arranged so as to change from positive logic to negative logic by twisting it into an odd number or even number of binary numbers shown in the upper word. The present applicant has previously proposed a method of forming the entire address code from MSB to LSB to be a gray code as a prior art. For example MS
Assuming that B and 2SB are odd numbers, 2SB and 3SB are logically inverted.

[0013]

As described above, since the MSB to LSB address code is set to positive logic or negative logic depending on whether the upper bits are odd or even and the gray coded address code is recorded, Even if the address data read from the header during a seek is incorrect, the change in gray code is a 1-bit difference between adjacent tracks, so the absolute position of the track during seek does not differ greatly. Although an advantage occurs, on the other hand, there is a problem that it takes time for error check processing at the time of address reproduction, and quick address reproduction cannot be performed.

That is, although the address code 2 is recorded from the LSB side for the above-mentioned reason, the process of decoding the reproduction signal of the gray coded address code into the address code of the normal bit stream (non-gray coded) Can be executed only after the reproduction scan from the LSB to the MSB is completed. This is because whether or not each word is logically inverted cannot be determined unless the even or odd of the decoded data of the upper word is obtained.

Therefore, for address code 2, LS
Values from the B side to the MSB are reproduced and stored as binary data in registers, and when the reproduction (binary decoding) of the MSB is completed, 2SB is output based on the even or odd.
Is decoded (non-gray coded), and then 3SB is decoded based on whether the decoded data of 2SB is even or odd. Then, only when the decoding up to the LSB is completed, the comparison processing with the decoded data concerning the reproduction scanning of the address 1 is performed, and the presence or absence of the read error is detected.

[0016]

In order to solve such a problem, the present invention has at least first and second address areas.
In the optical disc in which the track addresses are continuously written, after decoding the reproduction signal at the first track address, the decoded data is encoded again to the state before decoding, and the encoded data is reproduced as the reproduction signal at the second track address. The presence or absence of an address detection error is detected by comparing with

[0017]

If the first track address to be reproduced first is decoded (non-gray coded) and then encoded again (gray coded), the reproduced signal of the second address before decoding ( It is possible to detect coincidence with binary data).

[0018]

1 is a block diagram of an optical disk reproducing apparatus in which an embodiment of the present invention is adopted for reading a track address provided in an address area of a sector, and 1 is an optical disk. , This optical disc 1
As described with reference to FIG. 7, in the header 1, the track address is double written as the address 1 and the address 2. Further, the address 1 is recorded as MSB to LSB, while the address 2 is recorded as LSB to MSB, and the LSBs are adjacent to each other. Furthermore, this address 1
The address 2 is entirely gray-coded, and each word of MSB to LSB is pre-formatted in a state in which logical inversion processing is performed when the upper word is an odd number.

Reference numeral 2 denotes a spindle motor that drives the optical disk so that the angular velocity is constant, and reference numeral 3 denotes an optical head that irradiates the optical disk with a laser beam and reads the recorded data of the optical disk from the reflected light. The head 3 is subjected to tracking control and focus control by a control signal (not shown).

In the case of a magneto-optical disk recording / reproducing device, a magnetic head is arranged on the other surface of the disk facing the optical head 3 to record data. Reference numeral 4 denotes an amplifier for the reproduction RF signal output from the detector, and the recorded data portion of the reproduction RF signal is supplied to the reproduction signal processing circuit 5. Then, the reproduction signal processing circuit performs various kinds of signal processing such as data sampling, generation of a read clock signal, and other demodulation of recorded data.

Next, the reproduced RF signal obtained from the header 1 and the servo byte area SB is extracted by the difference detection circuit 6 by the pit position detection method or the edge position detection method and recorded in each servo byte area SB. The servo pits are supplied to the servo circuit 7 to form a tracking error signal, a focus error signal, etc., and a control signal for controlling the objective lens, actuator, etc. of the optical head 3. Further, the gray code recorded in the servo byte SB area is detected, and this data is decoded to form access data for counting the number of tracks in the traverse.

The data of the track address recorded in the header 1 is supplied to the decoder 8 and converted into a binary code (binary data). The 4-bit access code recorded in the servo byte area SB is supplied to the register 9 as a traverse signal, and the 5-digit track address data (address 1) recorded in the header 1 is input to the address decoder 10. ing.
The address decoder 10 is a unit for non-Gray-coded an address code which is gray-coded and recorded as a whole and restored to a normal code form. That is, for each word of MSB to LSB, an upper word is an odd number. If there is, a process for reversing the logic is performed again.

The track address non-gray coded by the address decoder 10 is fetched by the control signal into the registers 11A to 11E corresponding to the respective digits, and the total output of each register 11A to 11E is 5.
Digit track address MSB, 2SB, 3SB, 4S
B and LSB are taken out. Then, a desired track jump is performed based on this data. In addition,
The sector mark is detected similarly, but this point is omitted because it is not directly related to the present invention.

Reference numeral 12 represents an address encoder,
The track addresses MSB, 2SB, 3SB, 4SB, LSB output from the registers 11A to 11E are input, and a process of gray coding them again is performed. That is, the logical inversion is performed only when the upper word is an odd number. The signal S _EO indicates even / odd information, and is decoded and non-gray coded MSB, 2SB, 3SB, 4S.
The even / odd information about the value of B is supplied to the address decoder 10 and the address encoder 12. Reference numeral 13 denotes a comparator, and the comparator 13 is adapted to perform coincidence detection between the output data of the decoder 8 and the output data of the address encoder 12.

Here, gray coding of the track address will be described. FIG. 4A shows an example in which a quaternary gray code is configured by 2 out of 4. That is,
The bit array of each value 0 to 3 (word) is shifted by 1 bit between adjacent words.
Further, FIG. 4 (b) also shows a quaternary gray code, but this figure shows the gray code of FIG. 4 (a) in negative logic. On the optical disc 1, an array of positive logic gray codes and negative logic gray codes is used so that the entire gray code is obtained.

FIG. 6 shows an example of forming a 5-digit track address with the above-mentioned quaternary gray code.
The gray code pattern in the above table is used for each digit, MSB, 4SB, 3SB, 2SB, LSB, and as a whole 4 ⁵
You can display the exact track address. The quaternary gray code indicating the value of each digit is a negative logic gray code pattern when the value of the upper digit of the digit is odd. That is, track addresses 5 to
In 8 and 13-16, the gray code of 4SB is 1 or 3
Since it is an (odd number), the lower LSB is configured to be developed with a negative logic gray code pattern.

Similarly, since the 3SB gray code indicating the track addresses 17 to 32 indicates 1 (odd number),
The subordinate 4SB uses a gray code that adopts a negative logic array. As described above, when the word of a certain digit is an odd number in binary number, if the gray code of the lower digit of the digit is configured to be indicated by the negative logic, the track address is grayed out as a whole. Can be shown in code. Needless to say, the word of each digit is also partially arranged in the gray code.

FIG. 5 shows an example of arrangement when an octal gray code (2 out of 8) is used in place of the above-mentioned quaternary gray code. FIG. 5 (a) is positive logic and FIG. ) Is an example of a negative logic gray code pattern. By adding a 5-digit track address as shown in FIG. 6 using the gray code in this table, it becomes possible to specify 8 ⁵ track positions.

As described above, since the track address is gray-coded, the address 1 and the address 2 are double-written, and the address 2 is recorded from the LSB side, various advantages occur as described above. On the other hand, on the other hand, there is a problem that the decoding process of the address 2 takes time and the detection of the error occurrence is eventually delayed. However, in the present embodiment, the error occurrence detection is almost the same point as the completion of the reproduction scanning of the address 2. Can be completed in. This will be described with reference to the timing chart of FIG. In this figure, "msb" to "lsb" indicate gray-coded address codes and "Mb"
The symbols "SB" to "LSB" indicate the address codes in the normal bit stream form in which the logical inversion is released and the gray code is not applied.

FIG. 2 (a) shows scanning of the track address. First, from the optical disc 1, "ms" of the address 1 is read.
Reproduction scanning is performed in the order of "b" to "lsb", and then "lsb" to "msb" of address 2 are sequentially scanned.
Address 1 "msb" to "lsb" are sequentially decoder 8
After being binarized by, it is input to the address decoder 10,
It is non-gray coded at the timings shown in FIGS.

That is, first, since "msb" is not logically inverted, the input value is held as it is in the register 11A as "MSB". For example, when each of the five words (msb, 2sb, 3sb, 4sb, lsb) is an octal gray code as shown in FIG. 5, “msb”
The 3-bit data (D
_{0 to} D ₂ ) are input to and held in the register 11A.

Next, the 3-bit data of "2sb" is input to the address decoder 10. Here, "M"
SB's even-odd, that is, the least significant bit of "MSB" is "1"
If so, "2sb" is logically inverted and becomes "2SB".
Is taken into the register 11B. Similarly,
For "3sb" to "lsb", a decoding process of logically inverting when the upper word is an odd number is executed, and "3SB" to "LSB" are stored in the registers 11C to 11E.
Is retained. At this stage, the data "MSB" to "LSB" held in the registers 11A to 11B become the reproduction data of the track address of the sector read during the seek of the optical disk, and after the error occurrence detection operation described below, various controls are performed. Will be used for.

Here, the data "MSB" to "LSB" held in the registers 11A to 11B are supplied to the address encoder 12 and are again gray-coded into "msb" to "lsb". Then, the output of the address encoder 12 and the reproduced (binary) data of the address 2 are compared by the comparator 13 at the timings shown in FIGS.

That is, "msb" to "ls of address 1"
After "b", "lsb" to "msb" at address 2 are sequentially scanned and binarized by the decoder 8. When "lsb" at address 2 is reproduced and scanned, the data is It is not captured by the address decoder 10 but directly supplied to the comparator 13. Then, in accordance with the timing, the address encoder 12 outputs "lsb" data obtained by encoding "LSB". Comparator 13
Then, "ls" which is the reproduction data of the supplied address 2
b ”and“ lsb ”which is the re-encoded data of the decoded data of address 1 are compared to detect the coincidence. If they do not match, the address read error occurrence information is output. Hereafter, at address 2, “4
Similarly, for "sb" to "msb", the coincidence with the output of the address encoder 12 is detected, and it is sequentially confirmed whether or not a read error has occurred.

Therefore, in the case of the present embodiment, as can be seen from FIG. 2, immediately after the scanning of the address 2 is completed, the confirmation of the occurrence of the read error is also completed. That is, the reading of the track address and the error detection are performed very quickly. In addition, "lsb" of address 2 ~
Since "msb" is not subjected to decoding processing (non-Gray coding), a register for holding each word data before decoding processing is not necessary, which leads to simplification of the circuit configuration.

In FIG. 3, as shown in FIG. 5, the octal gray code is divided into 5 words (MSB, 2SB, 3SB, 4SB, LS).
Address decoder 1 of FIG. 1 corresponding to B)
0, the address encoder 12 is specifically shown. In this case, in the address information read out while the optical disk is being sought, the gray code of each digit is converted into the 3-bit binary code (D _{0 to} D ₂ ) in the decoder 8 as described above. And first, the binary code indicating msb is
It is latched in the word register 10A by a control clock supplied from the outside and latched in the register 11A at a predetermined timing. The least significant bit of this MSB is passed through the EX-OR circuit 10f to the word register 10B of the next digit. It is configured to take the exclusive OR with the input data of.

Therefore, if the least significant bit of the MSB is "1" indicating an odd number, the EX-OR circuit outputs 2SB.
Data is converted into “0” → “1” and “1” → “0”, and the complement indicated by the gray code of negative logic is supplied to the second word register 10B.

Similarly, by detecting the lowest binary number of the upper digit (SB) by the EX-OR circuit (10g, 10h, 10i), the word of this digit becomes even or odd. The data of the word of the next digit is stored as it is or after being converted into a complement and stored in the word registers 10C, 10D, and 10E, and the output of each word register is stored in the address register 11 at a predetermined timing. By latching, the track address of the sector read during seek of the optical disk is detected.

The data held in the registers 11A to 11E are read out at the same timing immediately after the reproduction scanning of the address 1 portion is completed, and the 3-bit word registers 12A to 12E and the EX-OR circuit group 12 are read.
It is supplied to the address encoder 12 composed of f to 12i. That is, the least significant bit of the upper word is the EX-OR
By being supplied to the circuit groups 12f to 12i, the word register 1 that latches data at a predetermined timing
2A to 12E hold gray coded data (“msb” to “lsb”) again. Therefore, the data (lsb) of the word register 12E is first read at the scanning timing of the address 2, and the comparator 13
Is supplied to and the matching detection is executed. Thereafter, the data (4 sb to msb) in the word registers 12D to 12A are sequentially read at a predetermined timing, and the coincidence with the reproduced binary data is detected.

Although the above embodiment corresponds to the method of detecting an error occurrence by detecting the coincidence between address 1 and address 2, address 2 is composed of the parity data of address 1 and the parity check is performed. The present invention can also be applied to the method of performing error check by If the address is double or more (triple writing, 4
The same is true for various systems with different writing), word order, and coding.

[0041]

As described above, according to the address detecting method for the optical disk of the present invention, the first track address decoded (non-Gray coded) is re-encoded (Gray coded), and then the first track address is decoded. Since the coincidence detection is performed with the reproduction signal (binary data) at the stage before the decoding of the second address, it is not necessary to decode the second address, and the read error check can be completed very quickly. There is an effect that you can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a track address data reading circuit adopting an embodiment of an address detection system for an optical disc of the present invention.

FIG. 2 is an explanatory diagram of the operation timing of the address detection method for the optical disc of the present embodiment.

FIG. 3 is a more specific block diagram of the read circuit according to the present embodiment.

FIG. 4 is a pattern diagram showing a quaternary positive and negative logic Gray code array.

FIG. 5 is a pattern diagram showing octal positive and negative logic Gray code arrays.

FIG. 6 is an example of a pit pattern of track address data in which a quaternary gray code is one word.

FIG. 7 is an explanatory diagram of tracks showing a data array of an optical disc.

FIG. 8 is an explanatory diagram of an address format in which LSBs are adjacent to each other.

[Explanation of symbols]

 1 Optical Disc 2 Spindle Motor 3 Optical Head 6 Signal Extraction Section 8 Decoder 10 Address Decoder 11A-11E Register 12 Address Encoder 13 Comparator

Claims (1)

[Claims] 1. An optical disc in which a concentric or spiral track is divided in the circumferential direction, and at least first and second track addresses are continuously written in the address areas of the divided sectors. After decoding the reproduction signal according to the track address of No. 1, the decoded data is encoded again to the state before decoding, and the presence or absence of an address detection error is determined by comparing the encoded data with the reproduction signal of the second track address. An optical disk address detection method characterized by the above.