JPH05181747A - Data processing system - Google Patents

Abstract

PURPOSE:To shorten an excessive processing time generated due to the misreading cache of a cache memory at the time of transferring much data. CONSTITUTION:A microprocessor 9 compares data transfer frequency previously set up in a transfer frequency setting circuit 6 at the time of executing a data transfer instruction with the data transfer frequency of a data transfer counter 5 which is counted at the time of executing the data transfer instruction by means of a comparator 7, and when both the values are equal to each other, outputs a cache inhibition signal from a cache inhibition signal output part 4. Thereby the operation of the cache memory is inhibited until the execution end of the data transfer instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system equipped with a microprocessor for accessing data in a main memory or a cache memory for data processing, and more particularly to a configuration for efficiently using the cache memory. is there.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of a data processing system of this type. In FIG. 2, 10 is a main memory that stores data necessary for data processing, 11 is a cache memory that temporarily stores data when the main memory 10 is accessed, and 9 is an access to the main memory 10 or the cache memory 11. It is a microprocessor for performing data processing. 12 is data, address,
And various control signals to the microprocessor 9 and the main memory 1.
0 is a bus for exchanging data between the cache memory 11 and 13 is a cache inhibit signal line through which a cache inhibit signal for the microprocessor 9 to inhibit the cache operation of the cache memory 11 flows. The address width and data width in this data processing system are 32 bits, and 1WORD is defined as 32 bits.

The cache memory 11 monitors the address at which the microprocessor 9 accesses the main memory 10, and if the data corresponding to the address is in the cache memory 11, it responds to the access from the microprocessor 9 (this The data corresponding to the address (called cache hit) is returned to the microprocessor 9. If the data corresponding to the address does not exist in the cache memory 11 (this is called cache miss), the cache memory 11 accesses the main memory 10 and returns the address and data to the microprocessor 9 and at the same time the cache memory 11 Take it in. Further, the cache memory 11 accesses the remaining 3 words in succession from the address read by the microprocessor 9, fetches the address and data, and fetches the addresses and data in consecutive 4 words including the address read by the microprocessor 9.

FIG. 4 is a timing chart at the time of reading of the data processing system using the conventional microprocessor and cache memory.

Next, the operation of the conventional example will be described with reference to FIGS. The microprocessor 9 performs an operation of continuously reading a plurality of data stored at consecutive addresses one after another, and the cache memory 11 does not have all the data to be read. Consider the case. First, the main memory 10 is accessed in 3 clocks, and the cache memory is accessed in 2 clocks from the microprocessor 9. When accessing the main memory 10 in the case of a read cache miss, an extra 1 clock is required and the access is performed in 4 clocks.

From the clock CLK0, the microprocessor 9 performs an operation of continuously reading a plurality of data stored in consecutive addresses. The cache memory 11 determines a cache miss in one clock and starts reading from the main memory 10 at the clock CLK1. At the same time, the microprocessor 9 also reads. 1 with clock CLK4
The reading from the main memory 10 of WORD is completed. Since the cache memory 11 has missed the read cache, 3 words are generated between the clock CLK4 and the clock CLK13.
Data is continuously taken from the main memory 10. During this time, the microprocessor 9 is in the hold state and does not start the bus cycle. 4 words with cache memory 11
The microprocessor 9 starts the read at the clock CLK13 at which the read is finished. The data to be read at this time is a cache hit because the cache memory 11 fetches it from the main memory 10 in the clocks CLK4 to CLK7, and the microprocessor 9 reads the data from the cache memory 11 in two clocks of the clocks CLK13 to CLK15. To do. Continued 2
Similarly, the read of WORD hits the read CL as well.
At K19, the reading of the 4th word data from the beginning is completed. Since the data to be read next is not stored in the cache memory 11, a read cache miss occurs and the same operations as the clocks CLK0 to CLK19 are repeated.

When all the data to be read has a read cache miss in this way, the loss time due to the processing time for the cache memory 11 to read the data from the main memory 10 is longer than the time for increasing the access time of the cache memory 11. May become large. In this example, it takes 19 clocks to transfer 4 words, but if the cache memory 11 does not operate, then it will be 12 clocks of 3 clocks × 4 words.
When the cache memory 11 is used, even if a read cache miss occurs in the first read, if the number of times of reading the data of the same address is large, the data transfer time can be shortened as a whole. However, when a large amount of data is transferred at once without accessing the same address, such an effect may not be expected. For example, when the amount of data to be transferred exceeds the storage capacity of the cache memory 11, the first read data does not remain in the cache memory 11, and therefore the read cache hit does not occur even if the same data transfer is performed again.

[0008]

The microprocessor in the conventional data processing system is used for transferring a large amount of data (for example, executing a data transfer instruction).
However, since the cache memory was operating, there was a problem that it took a lot of time to transfer the data as compared with the case where the cache memory is not used.

The present invention has been made to solve the above problems, and a microprocessor capable of reducing the extra processing time generated by the operation of the cache memory even when a large amount of data is transferred. An object of the present invention is to provide a data processing system provided with.

[0010]

A data processing system according to the present invention includes a transfer number setting circuit 6 for presetting an arbitrary number of data transfers for inhibiting an operation of a cache memory 11, and a data transfer command for executing a data transfer instruction. The value of the data transfer counter 5 that counts the number of transfers and the value of the transfer number setting circuit 6 and the value of the data transfer counter 5 when the data transfer instruction is executed are compared, and the value of the data transfer counter 5 matches the value of the transfer number setting circuit 6. The microprocessor 9 is provided with a comparator 7 which sometimes outputs a coincidence signal and a cache inhibit signal output unit 4 which outputs a cache inhibit signal for inhibiting the operation of the cache memory 11 by the coincidence signal from the comparator 7. It is a thing.

[0011]

When the data transfer instruction is executed, the microprocessor 9 uses the comparator 7 to compare the data transfer number set in advance in the transfer number setting circuit 6 and the data transfer number of the data transfer counter 5 counted when the data transfer instruction is executed. If they are compared with each other and they match each other, the cache inhibition signal output unit 4 outputs a cache inhibition signal. As a result, the operation of the cache memory 11 is prohibited until the execution of the data transfer instruction is completed.

[0012]

1 is a block diagram showing the internal configuration of a microprocessor according to an embodiment of the present invention. The configuration of the data processing system including this microprocessor is shown in FIG. In FIG. 1, 1 is an instruction fetch unit that fetches an instruction from an external bus 12, 2 is an instruction decoding unit that recognizes the fetched instruction and outputs the decoding result to the control unit, 3 is the entire microprocessor 9 based on the instruction decoding result. The control unit 4 generates a control signal for controlling the control signal, and outputs a signal indicating execution of the instruction to the logic gate 8 during execution of the data transfer instruction. The cache inhibition signal output units 5 that output inhibition signals are data transfer counters that are reset at the start of execution of a data transfer instruction and whose number of data transfers is incremented by a signal from the control unit 3 for each transfer. 6 is a transfer number setting circuit for setting an arbitrary value (arbitrary data transfer number for inhibiting the operation of the cache memory 11) to be compared with the data transfer counter 5, and 7 is a value and a transfer number setting for the data transfer counter 5. The comparator 6 compares the values of the circuit 6 and outputs a coincidence signal to the logic gate 8 when the two coincide with each other, and 8 inputs the signal output from the control unit 3 and the signal output from the comparator 7 to input both signals. Is a logic gate that outputs the valid signal to the cache inhibit signal output unit 4 when both are effectively output.

FIG. 3 is a timing chart at the time of reading of the data processing system using the microprocessor and the cache memory according to the embodiment of the present invention.

Next, the operation of the microprocessor of the embodiment will be described with reference to FIG. The user writes in advance a data transfer count value for which the cache operation is to be prohibited when the data transfer instruction is executed, in the transfer count setting circuit 6. In the microprocessor 9, the instruction fetch unit 1 fetches an instruction from the external bus 12, the instruction decoding unit 2 recognizes the instruction, and outputs the decoding result to the control unit 3. The control unit 3 outputs a signal indicating the instruction execution to the logic gate 8 during the execution of the data transfer instruction. Therefore, for instructions other than the data transfer instruction, the logic gate 8 causes the cache inhibit signal output unit 4 to
Since the valid signal is not output to, the cache inhibit signal is not output. The comparator 7 is the data transfer counter 5
Is compared with the preset value of the transfer number setting circuit 6, and when the two match, a match signal is output to the logic gate 8. Therefore, during execution of the data transfer instruction, while the value of the data transfer counter 5 is less than the value of the transfer number setting circuit 6, the valid signal from the logic gate 8, that is, the cache prohibition signal output unit 4 does not output the cache prohibition signal. When the data transfer instruction is being executed and the value of the data transfer counter 5 becomes equal to or greater than the value of the transfer number setting circuit 6,
Since the valid signal is output from the logic gate 8, the cache inhibit signal output unit 4 outputs the cache inhibit signal. As a result, the operation of the cache memory 11 is prohibited.

Next, the operation of the data processing system using the microprocessor and cache memory of this embodiment will be described with reference to FIGS. When the microprocessor 9 executes a data transfer instruction to transfer a large amount of data, the addresses are continuous and the same address is not referred to until the execution of the instruction is completed. The capacity of the data specified by the data transfer instruction is the cache memory 1
When the capacity of 1 is exceeded, a cache miss occurs for the access of data that is read beyond the cache capacity, and a cache miss occurs for all subsequent accesses. Main memory 10 has 3 clocks, cache memory 11
Is accessed from the microprocessor 9 in 2 clocks, and when the read cache miss occurs, an extra 1 clock is required to access the main memory 10, and access is performed in 4 clocks. In this case, if the cache memory 11 operates to read 4 words, it takes 19 clocks as in the conventional example. However, if the cache inhibit signal is output in response to the access and the cache memory 11 is not operated, it takes only 3 clocks × 4 words = 12 clocks.

The user can optimize the program execution speed by setting the value of the data transfer number in the transfer number setting circuit 6 and adjusting the output timing of the cache inhibit signal when the data transfer instruction is executed.

Although the logic gate 8 and the cache inhibit signal output section 4 are described separately in the above embodiment, it may be considered that the logic gate 8 is included in the cache inhibit signal output section 4.

[0018]

As described above, according to the present invention, when the data transfer instruction is executed, the number of times of data transfer set in advance in the transfer number setting circuit and the number of times of data transfer of the data transfer counter which is counted when the data transfer instruction is executed, The microprocessor is configured to output the cache prohibition signal from the cache prohibition signal output unit when the two are compared and the cache prohibition signal output unit outputs the cache prohibition signal. Therefore, the cache memory will not operate after the set number of data transfers. Even if a large amount of data is transferred, it is possible to reduce the extra processing time caused by a read cache miss in the cache memory. That is, according to the present invention, it is possible to obtain an effect that it is possible to reduce a decrease in the data transfer rate due to a large number of consecutive read cache misses.

[Brief description of drawings]

FIG. 1 is a block diagram showing an internal configuration of a microprocessor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data processing system including a microprocessor of this embodiment or a conventional microprocessor.

FIG. 3 is a timing chart at the time of reading of the data processing system using the microprocessor and the cache memory of this embodiment.

FIG. 4 is a timing diagram at the time of reading of the data processing system using the conventional microprocessor and cache memory.

[Explanation of symbols]

 4 cache inhibit signal output unit 5 data transfer counter 6 transfer count setting circuit 7 comparator 9 microprocessor 10 main memory 11 cache memory

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[Procedure amendment]

[Submission date] August 27, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

The cache memory 11 monitors the address at which the microprocessor 9 accesses the main memory 10, and if the data corresponding to the address is in the cache memory 11, it responds to the access from the microprocessor 9 (this The data corresponding to the address (called cache hit) is returned to the microprocessor 9. The cache memory 11, if the data corresponding to the address is not in the cache memory 11 (this is called a cache miss), access to the main memory 10 returns the de <br/> over data of it to the microprocessor 9 And at the same time ,
Memory and its data are taken into the cache memory 11. Furthermore, the cache memory 11 has 3 consecutive words remaining from the address read by the microprocessor 9.
Is accessed, the address and data are fetched, and consecutive 4WORD addresses and data including the address read by the microprocessor 9 are fetched.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] Explanation of code

[Correction method] Change

[Correction content]

[Description of Codes] 1 instruction fetch unit 2 instruction decode unit 3 control unit 4 cache inhibit signal output unit 5 data transfer counter 6 transfer count setting circuit 7 comparator 9 microprocessor 10 main memory 11 cache memory 12 bus 13 cache inhibit signal line

Claims (1)

[Claims] 1. A main memory that stores data required for data processing, a cache memory that temporarily stores data when the main memory is accessed, and a data that is accessed by the main memory or the cache memory. In a data processing system including a microprocessor for performing processing, a transfer number setting circuit that presets an arbitrary data transfer number for inhibiting the operation of the cache memory, and a data transfer number when executing a data transfer instruction When the data transfer counter and the data transfer instruction are executed, the value of the transfer count setting circuit is compared with the value of the data transfer counter, and a match signal is output when the value of the data transfer counter matches the value of the transfer count setting circuit. The operation of the cache memory is prohibited by the comparator and the coincidence signal from this comparator. A data processing system, wherein the microprocessor is provided with a cache inhibit signal output section for outputting a cache inhibit signal for stopping.