JPH05181643A - Zero detecting circuit - Google Patents

Abstract

PURPOSE:To provide a circuit for deriving directly a zero signal for showing whether a result of addition and subtraction is zero or not, from two numerals which are given, to execute a zero detection in parallel with a computing element, and to execute the detection at a high speed as the whole computing element. CONSTITUTION:Two numerals A, B of (n) bits are divided into AH, BH of the high order nh bits and AL, BL of the lower order n1 bits. AH and BH are inputted to a zero detecting circuit 2 of nh bits and zero signals ZH0, ZH1 and carry signals CH0, CH1 are generated. In the same way, by using a zero detecting circuit 3 of n1 bits, zero signals ZL0, ZL1 and carry signal CL0, CL1 are generated from AL and BL. From these signals, zero signals Z0, Z1 and carry signals C0, C1 after coupling are generated by a zero detecting signal synthesizing circuit 1. Z0 and Z1 become a zero signal of A+B, and a zero signal of A+B+1, respectively. The zero detecting circuit of the same constitution can be used for detecting zero in each divided part, as well.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a zero detection circuit for an addition / subtraction result of a digital type adder / subtractor.

[0002]

2. Description of the Related Art Conventionally, whether or not an operation result such as addition and subtraction is zero can be obtained as a result of taking an inverted logical sum of all bits as a result of operation.

FIG. 8 is a block diagram of a zero detection circuit for explaining this conventional method. The arithmetic unit 31 inputs n-bit two numbers A and B and outputs n-bit. The inverting logical sum circuit 32 takes the inverting logical sum of all bits of the output of the arithmetic unit 31. As a result, the zero signal Z becomes 1 if the operation result is zero, and the zero signal Z if the result is not zero.
Is 0.

[0004]

However, in the conventional zero detection circuit, since the zero is detected after the calculation result is obtained, the zero signal is obtained only after the calculation result is obtained.
There is a drawback that it takes time to obtain the result. In particular, the addition and subtraction takes a calculation time because propagation of a carry occurs, and further, a time for zero detection is added, so that the calculation time as a whole increases.

In the case of subtraction, the result is zero when the two numbers are equal. Therefore, it can be substituted by checking whether the exclusive OR of each bit of the two numbers is zero. However, in the case of addition, the result is zero when the two numbers are in the two's complement relation, but a means for checking the two's complement relation is required.

An object of the present invention is to provide a circuit for directly obtaining a zero detection signal indicating whether or not the result of addition / subtraction of two numbers is zero, from the two numbers.

[0007]

According to a first aspect of the present invention, in a zero detection circuit for detecting whether the addition / subtraction result of two numbers of an arbitrary bit is zero, the two numbers are divided into upper and lower parts, and a lower part for each. The carry signal from the lower order lower signal is obtained by obtaining a zero signal indicating whether or not the result of addition and subtraction is zero and a carry signal indicating the presence or absence of carry depending on whether there is a carry from the If there is no carry signal when there is no carry signal, the logical product of the zero signal when there is no carry signal from the higher order lower order and the zero signal when there is no carry signal from the lower order lower order is described in 2 above.
When there is no carry from the lower order of the number addition / subtraction result, the zero signal is used, and the carry signal when there is no carry from the higher order lower order is used when there is no carry signal from the lower order of the two number addition / subtraction results. As a carry signal, if there is no carry signal when there is a carry signal from the lower order lower, the zero signal when there is no carry from the higher order lower order and the carry signal from the lower order lower order. The logical product of the zero signals in a certain case is taken as the zero signal when there is a carry from the lower order of the addition / subtraction result of the two numbers, and the carry signal when there is no carry from the above lower order is the addition / subtraction of the two numbers. If there is a carry signal from the lower order of the result, the carry signal is used. If there is a carry signal when there is no carry signal from the lower order, the carry signal from the lower order is zero. Signal and carry signal from the lower order of the lower order The logical product of the zero signal if the zero signal in the case where there is no carry from the lower of the two numbers addition and subtraction result,
A carry signal when there is a carry signal from the lower order of the higher order is a carry signal when there is no carry signal from the lower order of the addition / subtraction result of the two numbers, and there is a carry signal from the lower order of the lower order. When there is a carry signal, the logical product of the zero signal when there is a carry signal from the upper lower order and the zero signal when there is a carry signal from the lower order lower order is the lower order of the addition / subtraction result of the two numbers. Is used as a zero signal when there is a carry signal, and the carry signal when there is a carry from the higher order lower order is the carry signal when there is a carry signal from the lower order of the addition / subtraction result of the two numbers. Is characterized by.

A second aspect of the present invention is a zero detection circuit for detecting whether or not the addition / subtraction result of two numbers of arbitrary bits is zero.
The number is divided into upper and lower, and there is no carry from the lower and there is a carry for each, and a zero signal indicating whether the result of addition and subtraction is zero and a carry signal indicating the presence or absence of carry. If there is no carry signal when there is no carry signal from the lower order lower, there is no zero signal when there is no carry from the higher order lower order and there is no carry signal from the lower order lower order. The logical product of the zero signals of is the zero signal when there is no carry from the lower part of the addition / subtraction result of the two numbers, and the carry signal when there is no carry from the lower part of the upper number is the addition signal of the two numbers. A carry signal when there is no carry signal from the lower order, and a zero signal when there is a carry signal from the above lower order when there is no carry signal when there is a carry signal from the lower order. Of the zero signal when there is a carry signal from the lower The logical product is a zero signal when there is a carry from the lower order of the addition / subtraction result of the two numbers, and when there is a carry signal when there is no carry signal from the lower order lower order, the logical product from the higher order lower order The logical product of the zero signal when there is a carry and the zero signal when there is no carry signal from the lower order is the zero signal when there is no carry from the lower order of the addition / subtraction result of the two numbers, and If there is no carry signal from the lower order of the addition / subtraction result, the carry signal is set to logic 1, and if there is a carry signal when there is a carry signal from the lower order, carry from the lower order of the higher order. And the zero signal when there is a carry signal from the lower order lower order is the logical product of the zero signal when there is a carry from the lower order of the addition / subtraction result of the two numbers.

The zero detection circuit of the third invention is characterized in that, in the first invention or the second invention, each zero signal is obtained by dividing the number of two arbitrary bits into upper and lower.

According to the zero detection circuit of the fourth aspect of the present invention, 1 bit of 2 is used.
The exclusive inversion OR of the numbers is used as a zero signal when there is no carry from the lower side, and the exclusive OR of the two numbers is used as a zero signal when there is a carry from the lower side, and one of the two numbers is carried. It is characterized by detecting whether or not the result of the addition / subtraction of 1 bit is zero by using the raising signal.

A fifth aspect of the present invention is a zero detection circuit for detecting whether or not the result of addition / subtraction of two 1-bit numbers is zero. At the time of addition, the exclusive inversion OR of the two numbers is carried from the lower order. Is used as a zero signal, the exclusive OR of the two numbers is used as a zero signal when there is a carry from the lower order, one of the two numbers is used as a carry signal, and the two numbers are exclusively used for subtraction. The characteristic is that the logical inversion OR is used as a zero signal and the carry signal is used as no carry.

[0012]

In order to detect whether the addition / subtraction result of n-bit two numbers is zero, the carry signal propagates from the least significant bit to the most significant bit in the worst case during the operation.
Calculation time becomes long. When the number is 2 which is shorter than n bits, the number of stages of propagation of the carry signal becomes short, so that the operation time can be shortened. Therefore, the n bits are divided into the upper nh bits and the lower nl bits, and it is detected whether the addition / subtraction result of each is zero. Since both the nh bit and the nl bit are shorter than n bits, they can be detected in a shorter time than the zero signal of the addition / subtraction result of n bits.

Next, from each divided zero signal, n
Find the zero signal for all bits. To this end, it is necessary to prepare two high-order nh-bit zero signals in the case where there is a carry signal from the lower order and when there is no carry signal. Further, a carry signal indicating whether to carry in addition or subtraction of the lower nl bits is also required. If there is no lower carry signal, select the zero signal when there is no carry from the lower two out of the upper two zero signals, and if it is l together with the lower zero signal, the entire n bits The zero signal in addition and subtraction of may be set to l. When there is a lower carry signal, select the zero signal when there is a carry from the lower as the upper zero signal, and if it is l together with the lower zero signal, the zero signal in the addition / subtraction of all n bits is also selected. It should be l. In all other cases, the total zero signal is zero.

Since it is detected that the result of the addition and subtraction of the divided nh bits and nl bits is zero, it can be divided into shorter bits and the zero signal can be obtained by the same method. By repeating this, finally, all can be divided into 1 bit. In the case of 1-bit addition, if there is no carry from the lower order, the result is 0 when both numbers are 0 or 1, and if there is a carry from the lower side, one of the two numbers is 1 and the other is 0. The result is 0
Becomes Therefore, it can be obtained by a simple logic gate. These results are grouped by 2 bits, a 2-bit addition / subtraction zero signal is obtained, and further two are combined to perform zero detection of an arbitrary bit.

As described above, not only the zero signal of the addition / subtraction result but also the carry signal is necessary for the combination. In the case of 1-bit addition and subtraction, when the carry from the lower order is 0, it is 0 when both numbers are 1 or 0. Therefore, the carry signal is 1 when both numbers are 1 and 0 when both numbers are 0.
It should be done. If the two numbers are 1 and 0, the zero signal is 0
Therefore, the carry signal does not have to be correct because the upper zero signal becomes 0 when combined in any case. Therefore, it is sufficient to use one of the two numbers as it is as a carry signal. When there is a carry from the lower order, the zero signal becomes 1 when the number 2 is 1 and 0. Therefore, when the carry is added to the lower order, a carry signal is also generated from this bit. When the two numbers are both 1 or 0, the zero signal becomes 0, but it is not necessary to obtain the correct carry signal as in the case where there is no carry signal. Therefore, the carry signal in this case may be always 1. The following is a summary of these things. Input two numbers a, b, zero signal Z
0, Z1 and carry signals C0, C1. When the last character is 0, the value when the carry from the lower order is 0, and when the last character is 1 is the value when the carry from the lower order is 1. If ^ is an exclusive OR and ~ is an operator representing bit inversion, Z0 = ~ (a ^ b) (1) Z1 = a ^ b (2) C0 = a (or b) (3) C1 = It becomes 1 (4).

When the combination is repeated, the zero signal and the carry signal after the combination must be generated. In order to consider the presence or absence of a carry from the lower order in the combined zero signal, two kinds of signals, one with a carry from the lower order and one without a carry from the lower order, are prepared and used properly. You can deal with it. This is summarized in the formula as follows. The lower zero signal is ZL0, ZL1, the lower carry signal is CL0, CL1, the upper zero signal is ZH0, ZH1,
The upper carry signals are CH0 and CH1, the combined zero signals are Z0 and Z1, and the carry signals are C0 and C1. However, if the last character is 0, the carry signal from the lower order is 0.
The value of 1 is the value of 1 and the carry signal from the lower order is the value of 1. Also, & is a logical product, | is a logical sum, and ~ is an operator representing bit inversion.

Z0 = ZL0 & ((˜CL0 & ZH0) | (CL0 & ZH1)) (5) Z1 = ZL1 & ((˜CL1 & ZH0) | (CL1 & ZH1)) (6) C0 = (˜CL0 & CH0) | (CL0 & CH1) (7) C1 = (~ CL1 & CH0) | (CL1 & CH1) (8) Equations (5) and (6) show the case where there is no carry signal from the lower order when there is no carry from the lower order. This means that when there is a carry signal, one of the higher zero signals when there is no carry from the lower order is selected and the logical product is taken with the lower zero signal. For the lower zero signal and the carry signal used here, the value when there is no carry from the lower order is used in Equation (5), and the value when there is carry is used (6). It is an expression. As for the carry signal, if there is no carry signal from the lower order, the carry signal from the higher order carry signal if there is no carry signal from the lower order, and if there is a carry signal from the lower order, the carry carry signal from the lower order Select one of the signals that has a carry from the lower order. As for the carry signal from the lower order, the value when there is no carry from the lower order is used in the expression (7), and the value when there is a carry is used in the expression (8). These four equations make it possible to generate a zero signal and a carry signal in the block of connectors.

As can be seen from the equation (4), the value of C1 is always 1, so that the selector thereafter is always fixed when there is a carry. Rewriting the equations (6) and (8) in consideration of this, Z1 = ZL1 & CL1 (6 ′) becomes C1 = CH1 = 1 (8 ′). Thus, since the carry signal is 1 when the carry from the lower order is 1, this signal is not necessary when combining.

[0019]

EXAMPLES Next, examples of the present invention will be described with reference to FIGS.

FIG. 1 shows an embodiment of the present invention. n bits of 2 numbers A and B are converted to upper nh bits of AH and B
It is divided into H and AL and BL of lower nl bits. AH, B
H is input to the nh-bit zero detection circuit 2 and the zero signal ZH0,
ZH1 and carry signals CH0 and CH1 are generated. At the same time, the nl bit zero detection circuit 3 is used to generate zero signals ZL0 and ZL1 and carry signals CL0 and CL1 from AL and BL. Using these signals, the zero signals Z0 and Z1 and the carry signals C0 and C1 after combination are generated by the zero detection signal synthesizing circuit 1 which is a circuit that realizes the equations (5) to (8).
Here, Z0 is an A + B zero signal and Z1 is an A + B + 1 zero signal. Subtraction inverts B bit by bit to ~ B,
Since it is obtained by + (-B) +1, Z1 may be a zero signal.

FIG. 2 is a diagram showing a configuration example of the zero detection signal synthesizing circuit 1. The processing of the equation (5) is performed by the selector circuit 21 and the AND circuit 25, and the selector circuit 23 and the AND circuit 26 are used.
The processing of the equation (6) is performed by the selector circuit 22, the processing of the equation (7) is performed by the selector circuit 22, and the processing of the equation (8) is performed by the selector circuit 24.

FIG. 3 is a diagram showing a 1-bit zero detection circuit according to another embodiment of the present invention. 1-bit 2 number a,
Zero signal Z when there is no carry from the lower order by inputting b
0 is obtained from the exclusive-OR circuit 11 for a and b, and the zero signal Z1 when there is a carry from the lower order is obtained from the exclusive-OR circuit 12 for a and b. C0 outputs a as it is as shown in the equation (3). Further, as shown in the equation (4), C1 is set to 1 by using the logic 1 output circuit 13.

FIG. 4 shows another embodiment of the present invention. According to the equations (6 ') and (8'), the carry signal is always 1 when there is a carry signal from the lower order, so that the selector circuits 23 and 24 controlled by the signals are always.
Is not necessary because the value is fixed. Further, this carry signal is also unnecessary. Therefore, it is not necessary to use four signals as shown in FIG. 1, and a total of three signals, that is, two zero signals and one carry signal may be used. Therefore, FIG. 4 shows a zero detection signal synthesizing circuit 4 and an nh-bit zero detection circuit 5 which perform processing with three signals.
And the nl bit zero detection circuit 6 is a zero detection circuit.

FIG. 5 is a diagram showing a configuration example of the zero detection signal synthesizing circuit 4. The selector circuit 21 and the AND circuit 25 perform the processing of the equation (5), the AND circuit 26 performs the processing of the equation (6 ′), and the selector circuit 22 performs the processing of the equation (7). Since the carry signal when the carry signal from the lower order is 1 is unnecessary, there is no part corresponding to the processing of formula (8). Further, since there is no carry signal CH1 from the divided block, the logic 1 output circuit 27 takes its place.

FIG. 6 shows still another embodiment. Since there is no need for a carry signal when there is a carry from the lower order,
The output of C1 is deleted as compared with FIG.

FIG. 7 shows another embodiment. As an input, in addition to the 1-bit two numbers a and b, o is added as a control signal. When generating a carry signal, a may be output as it is for addition, and a and b for subtraction.
It suffices to detect whether or not match, so that the signal of Z0 which becomes 1 at that time may be selected. Therefore, the carry signal is fixed to 0 so that Z0 is always selected. The above processing can be performed by giving 1 to the input o at the time of addition and 0 at the time of subtraction. If this zero signal detector is used, a zero detection circuit corresponding to both addition and subtraction can be made.

[0027]

When the zero detection circuit of the present invention is used, a zero signal indicating whether or not the result of addition / subtraction is zero can be directly obtained from the given two numbers. Therefore, this zero detection circuit is used. By providing in parallel with the arithmetic unit, zero detection can be performed in parallel with the arithmetic unit. Therefore, the speed of the arithmetic unit as a whole can be increased. Also, when the number of bits is a power of 2, it can be divided into exactly half one after another, so the same circuit can be used multiple times.
Easy to design.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a zero detection circuit of the present invention.

FIG. 2 is a diagram showing a zero detection signal combining circuit.

FIG. 3 is a diagram showing an embodiment of a 1-bit zero detection circuit of the present invention.

FIG. 4 is a diagram showing another embodiment of the zero detection circuit of the present invention.

FIG. 5 is a diagram showing another zero detection signal synthesizing circuit.

FIG. 6 is a diagram showing an embodiment of another 1-bit zero detection circuit of the present invention.

FIG. 7 is a diagram showing an embodiment of another 1-bit zero detection circuit of the present invention.

FIG. 8 is a diagram showing an example of a conventional zero detection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 zero detection signal synthesis circuit 2 nh bit zero detection circuit 3 nl bit zero detection circuit 4 zero detection signal synthesis circuit 5 nh bit zero detection circuit 6 nl bit zero detection circuit 11 exclusive inversion OR circuit 12 exclusive OR circuit 13 Logical 1 output circuit 14 Logical sum circuit 21 Selector 22 Selector 23 Selector 24 Selector 25 Logical product circuit 26 Logical product circuit 27 Logical 1 output circuit 31 Operator 32 Inverting logical sum circuit

Claims (5)

[Claims] 1. A zero detection circuit for detecting whether an addition / subtraction result of two numbers of an arbitrary bit is zero or not, wherein the two numbers are divided into high order and low order, and there is no carry from the lower order and carry respectively. When there is a carry signal, the zero signal indicating whether the result of addition and subtraction is zero and the carry signal indicating the presence of carry are obtained, and there is no carry signal when there is no carry signal from the lower order. Is a logical product of the zero signal when there is no carry from the lower order of the upper order and the zero signal when there is no carry signal from the lower order of the lower order, and when there is no carry from the lower order of the addition / subtraction result of the two numbers. And the carry signal when there is no carry from the above lower order carry signal when there is no carry signal from the lower order of the addition / subtraction result of the two numbers, and carry from the above lower order If there is a signal and there is no carry signal, the above The logical product of the zero signal when there is no carry from the lower order and the zero signal when there is a carry signal from the lower order is the zero signal when there is a carry from the lower order in the addition / subtraction result of the two numbers. , The carry signal when there is no carry from the higher order lower order is the carry signal when there is a carry signal from the lower order of the addition / subtraction result of the two numbers, and when there is no carry signal from the lower order lower order When there is a carry signal, the logical product of the zero signal when there is a carry signal from the higher order lower order and the zero signal when there is no carry signal from the lower order lower order is the lower order of the addition / subtraction result of the two numbers. Is a zero signal when there is no carry, and the carry signal when there is a carry from the higher order lower order is the carry signal when there is no carry signal from the lower order of the addition / subtraction result of the two numbers. Digits when there is a carry signal from the lower order If there is a carry signal, the logical product of the zero signal when there is a carry from the higher order lower order and the zero signal when there is a carry signal from the lower order lower order is carried out from the lower order of the addition / subtraction result of the two numbers. When there is a carry, the carry signal when there is a carry from the higher order lower order is used as a carry signal when there is a carry signal from the lower order of the addition / subtraction result of the two numbers. Zero detection circuit. 2. A zero detection circuit for detecting whether or not the result of addition or subtraction of two numbers of arbitrary bits is zero. The two numbers are divided into high order and low order, and there is no carry from the lower order and carry respectively. When there is a carry signal, the zero signal indicating whether the result of addition and subtraction is zero and the carry signal indicating the presence of carry are obtained, and there is no carry signal when there is no carry signal from the lower order. Is a logical product of the zero signal when there is no carry from the lower order of the upper order and the zero signal when there is no carry signal from the lower order of the lower order, and when there is no carry from the lower order of the addition / subtraction result of the two numbers. And the carry signal when there is no carry from the above lower order carry signal when there is no carry signal from the lower order of the addition / subtraction result of the two numbers, and carry from the above lower order If there is a signal and there is no carry signal, the above The logical product of the zero signal when there is a carry from the lower order and the zero signal when there is a carry signal from the lower order is the zero signal when there is a carry from the lower order in the addition / subtraction result of the two numbers. , A zero signal when there is a carry signal when there is no carry signal from the lower order lower, and a zero signal when there is no carry signal from the higher order lower order and a zero signal when there is no carry signal from the lower order lower order. The logical product of the signals is a zero signal when there is no carry from the lower order of the addition / subtraction result of the two numbers,
If there is no carry signal from the lower order of the addition / subtraction result of the two numbers, the carry signal is set to logic 1. If there is a carry signal from the lower order lower order, if there is a carry signal, the higher order lower order And the zero signal when there is a carry signal from the lower order and the zero signal when there is a carry signal from the lower order lower order is defined as the zero signal when there is a carry from the lower order of the addition / subtraction result of the two numbers. Characteristic zero detection circuit. 3. The zero detecting circuit according to claim 1, wherein each zero signal is obtained by dividing the number of two of the arbitrary bit into upper and lower. 4. A 1-bit two-bit exclusive inversion OR is used as a zero signal when there is no carry from the lower order, and an exclusive OR of the two numbers is a zero signal when there is a carry from the lower order. age,
A 1-bit zero detection circuit, wherein one of the two numbers is used as a carry signal to detect whether or not the result of 1-bit addition / subtraction is zero. 5. A zero detection circuit for detecting whether or not the result of addition / subtraction of two 1-bit numbers is zero, in the case of addition, when the exclusive inversion OR of the two numbers is not carried from the lower order. As a zero signal, the exclusive OR of the two numbers is used as a zero signal when there is a carry from the lower order, one of the two numbers is used as a carry signal, and the exclusive OR of the two numbers is used for subtraction. Is a zero signal and the carry signal is no carry 1
Bit zero detection circuit.